ichlpcib.c revision 1.34.6.1
1 /* $NetBSD: ichlpcib.c,v 1.34.6.1 2015/01/16 08:22:25 snj Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.34.6.1 2015/01/16 08:22:25 snj Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 230 231 { 0, 0, 0, 0 }, 232 }; 233 234 /* 235 * Autoconf callbacks. 236 */ 237 static int 238 lpcibmatch(device_t parent, cfdata_t match, void *aux) 239 { 240 struct pci_attach_args *pa = aux; 241 struct lpcib_device *lpcib_dev; 242 243 /* We are ISA bridge, of course */ 244 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 245 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 246 return 0; 247 248 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 249 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 250 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 251 return 10; 252 } 253 254 return 0; 255 } 256 257 static void 258 lpcibattach(device_t parent, device_t self, void *aux) 259 { 260 struct pci_attach_args *pa = aux; 261 struct lpcib_softc *sc = device_private(self); 262 struct lpcib_device *lpcib_dev; 263 264 sc->sc_pa = *pa; 265 266 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 267 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 268 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 269 continue; 270 sc->sc_has_rcba = lpcib_dev->has_rcba; 271 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 272 break; 273 } 274 275 pcibattach(parent, self, aux); 276 277 /* 278 * Part of our I/O registers are used as ACPI PM regs. 279 * Since our ACPI subsystem accesses the I/O space directly so far, 280 * we do not have to bother bus_space I/O map confliction. 281 * 282 * The PMBASE register is alike PCI BAR but not completely compatible 283 * with it. The PMBASE define the base address and the type but 284 * not describe the size. 285 */ 286 if (pci_mapreg_submap(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 287 LPCIB_PCI_PM_SIZE, 0, &sc->sc_iot, &sc->sc_ioh, NULL, 288 &sc->sc_iosize)) { 289 aprint_error_dev(self, "can't map power management i/o space\n"); 290 return; 291 } 292 293 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 294 LPCIB_PCI_GEN_PMCON_1); 295 296 /* For ICH6 and later, always enable RCBA */ 297 if (sc->sc_has_rcba) { 298 pcireg_t rcba; 299 300 sc->sc_rcbat = sc->sc_pa.pa_memt; 301 302 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 303 LPCIB_RCBA); 304 if ((rcba & LPCIB_RCBA_EN) == 0) { 305 aprint_error_dev(self, "RCBA is not enabled\n"); 306 return; 307 } 308 rcba &= ~LPCIB_RCBA_EN; 309 310 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 311 &sc->sc_rcbah)) { 312 aprint_error_dev(self, "RCBA could not be mapped\n"); 313 return; 314 } 315 } 316 317 /* Set up the power management timer. */ 318 pmtimer_configure(self); 319 320 /* Set up the TCO (watchdog). */ 321 tcotimer_configure(self); 322 323 /* Set up SpeedStep. */ 324 speedstep_configure(self); 325 326 /* Set up HPET. */ 327 lpcib_hpet_configure(self); 328 329 #if NGPIO > 0 330 /* Set up GPIO */ 331 lpcib_gpio_configure(self); 332 #endif 333 334 #if NFWHRNG > 0 335 lpcib_fwh_configure(self); 336 #endif 337 338 /* Install power handler */ 339 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 340 lpcib_shutdown)) 341 aprint_error_dev(self, "couldn't establish power handler\n"); 342 } 343 344 static void 345 lpcibchilddet(device_t self, device_t child) 346 { 347 struct lpcib_softc *sc = device_private(self); 348 uint32_t val; 349 350 #if NFWHRNG > 0 351 if (sc->sc_fwhbus == child) { 352 sc->sc_fwhbus = NULL; 353 return; 354 } 355 #endif 356 #if NGPIO > 0 357 if (sc->sc_gpiobus == child) { 358 sc->sc_gpiobus = NULL; 359 return; 360 } 361 #endif 362 if (sc->sc_hpetbus != child) { 363 pcibchilddet(self, child); 364 return; 365 } 366 sc->sc_hpetbus = NULL; 367 if (sc->sc_has_ich5_hpet) { 368 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 369 LPCIB_PCI_GEN_CNTL); 370 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 371 case LPCIB_ICH5_HPTC_0000: 372 case LPCIB_ICH5_HPTC_1000: 373 case LPCIB_ICH5_HPTC_2000: 374 case LPCIB_ICH5_HPTC_3000: 375 break; 376 default: 377 return; 378 } 379 val &= ~LPCIB_ICH5_HPTC_EN; 380 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 381 LPCIB_PCI_GEN_CNTL, val); 382 } else if (sc->sc_has_rcba) { 383 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 384 LPCIB_RCBA_HPTC); 385 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 386 case LPCIB_RCBA_HPTC_0000: 387 case LPCIB_RCBA_HPTC_1000: 388 case LPCIB_RCBA_HPTC_2000: 389 case LPCIB_RCBA_HPTC_3000: 390 break; 391 default: 392 return; 393 } 394 val &= ~LPCIB_RCBA_HPTC_EN; 395 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 396 val); 397 } 398 } 399 400 static int 401 lpcibrescan(device_t self, const char *ifattr, const int *locators) 402 { 403 struct lpcib_softc *sc = device_private(self); 404 405 #if NFWHRNG > 0 406 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 407 lpcib_fwh_configure(self); 408 #endif 409 410 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 411 lpcib_hpet_configure(self); 412 413 #if NGPIO > 0 414 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 415 lpcib_gpio_configure(self); 416 #endif 417 418 return pcibrescan(self, ifattr, locators); 419 } 420 421 static int 422 lpcibdetach(device_t self, int flags) 423 { 424 struct lpcib_softc *sc = device_private(self); 425 int rc; 426 427 pmf_device_deregister(self); 428 429 #if NFWHRNG > 0 430 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 431 return rc; 432 #endif 433 434 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 435 return rc; 436 437 #if NGPIO > 0 438 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 439 return rc; 440 #endif 441 442 /* Set up SpeedStep. */ 443 speedstep_unconfigure(self); 444 445 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 446 return rc; 447 448 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 449 return rc; 450 451 if (sc->sc_has_rcba) 452 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 453 454 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 455 456 return pcibdetach(self, flags); 457 } 458 459 static bool 460 lpcib_shutdown(device_t dv, int howto) 461 { 462 struct lpcib_softc *sc = device_private(dv); 463 464 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 465 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 466 467 return true; 468 } 469 470 static bool 471 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 472 { 473 struct lpcib_softc *sc = device_private(dv); 474 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 475 pcitag_t tag = sc->sc_pcib.sc_tag; 476 477 /* capture PIRQ routing control registers */ 478 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 479 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 480 481 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 482 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 483 484 if (sc->sc_has_rcba) { 485 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 486 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 487 LPCIB_RCBA_HPTC); 488 } else if (sc->sc_has_ich5_hpet) { 489 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 490 } 491 492 return true; 493 } 494 495 static bool 496 lpcib_resume(device_t dv, const pmf_qual_t *qual) 497 { 498 struct lpcib_softc *sc = device_private(dv); 499 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 500 pcitag_t tag = sc->sc_pcib.sc_tag; 501 502 /* restore PIRQ routing control registers */ 503 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 504 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 505 506 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 507 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 508 509 if (sc->sc_has_rcba) { 510 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 511 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 512 sc->sc_hpet_reg); 513 } else if (sc->sc_has_ich5_hpet) { 514 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 515 } 516 517 return true; 518 } 519 520 /* 521 * Initialize the power management timer. 522 */ 523 static void 524 pmtimer_configure(device_t self) 525 { 526 struct lpcib_softc *sc = device_private(self); 527 pcireg_t control; 528 529 /* 530 * Check if power management I/O space is enabled and enable the ACPI_EN 531 * bit if it's disabled. 532 */ 533 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 534 LPCIB_PCI_ACPI_CNTL); 535 sc->sc_acpi_cntl = control; 536 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 537 control |= LPCIB_PCI_ACPI_CNTL_EN; 538 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 539 LPCIB_PCI_ACPI_CNTL, control); 540 } 541 542 /* Attach our PM timer with the generic acpipmtimer function */ 543 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 544 LPCIB_PM1_TMR, 0); 545 } 546 547 static int 548 pmtimer_unconfigure(device_t self, int flags) 549 { 550 struct lpcib_softc *sc = device_private(self); 551 int rc; 552 553 if (sc->sc_pmtimer != NULL && 554 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 555 return rc; 556 557 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 558 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 559 560 return 0; 561 } 562 563 /* 564 * Initialize the watchdog timer. 565 */ 566 static void 567 tcotimer_configure(device_t self) 568 { 569 struct lpcib_softc *sc = device_private(self); 570 uint32_t ioreg; 571 unsigned int period; 572 573 /* Explicitly stop the TCO timer. */ 574 tcotimer_stop(sc); 575 576 /* 577 * Enable TCO timeout SMI only if the hardware reset does not 578 * work. We don't know what the SMBIOS does. 579 */ 580 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 581 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 582 583 /* 584 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 585 * in the SMI_EN register is the last chance. 586 */ 587 if (tcotimer_disable_noreboot(self)) { 588 ioreg |= LPCIB_SMI_EN_TCO_EN; 589 } 590 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 591 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 592 } 593 594 /* Reset the watchdog status registers. */ 595 tcotimer_status_reset(sc); 596 597 /* 598 * Register the driver with the sysmon watchdog framework. 599 */ 600 sc->sc_smw.smw_name = device_xname(self); 601 sc->sc_smw.smw_cookie = sc; 602 sc->sc_smw.smw_setmode = tcotimer_setmode; 603 sc->sc_smw.smw_tickle = tcotimer_tickle; 604 if (sc->sc_has_rcba) 605 period = LPCIB_TCOTIMER2_MAX_TICK; 606 else 607 period = LPCIB_TCOTIMER_MAX_TICK; 608 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 609 610 if (sysmon_wdog_register(&sc->sc_smw)) { 611 aprint_error_dev(self, "unable to register TCO timer" 612 "as a sysmon watchdog device.\n"); 613 return; 614 } 615 616 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 617 } 618 619 static int 620 tcotimer_unconfigure(device_t self, int flags) 621 { 622 struct lpcib_softc *sc = device_private(self); 623 int rc; 624 625 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 626 if (rc == ERESTART) 627 rc = EINTR; 628 return rc; 629 } 630 631 /* Explicitly stop the TCO timer. */ 632 tcotimer_stop(sc); 633 634 /* XXX Set No Reboot? */ 635 636 return 0; 637 } 638 639 640 /* 641 * Sysmon watchdog callbacks. 642 */ 643 static int 644 tcotimer_setmode(struct sysmon_wdog *smw) 645 { 646 struct lpcib_softc *sc = smw->smw_cookie; 647 unsigned int period; 648 uint16_t ich6period = 0; 649 uint8_t ich5period = 0; 650 651 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 652 /* Stop the TCO timer. */ 653 tcotimer_stop(sc); 654 } else { 655 /* 656 * ICH6 or newer are limited to 2s min and 613s max. 657 * ICH5 or older are limited to 4s min and 39s max. 658 */ 659 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 660 if (sc->sc_has_rcba) { 661 if (period < LPCIB_TCOTIMER2_MIN_TICK || 662 period > LPCIB_TCOTIMER2_MAX_TICK) 663 return EINVAL; 664 } else { 665 if (period < LPCIB_TCOTIMER_MIN_TICK || 666 period > LPCIB_TCOTIMER_MAX_TICK) 667 return EINVAL; 668 } 669 670 /* Stop the TCO timer, */ 671 tcotimer_stop(sc); 672 673 /* set the timeout, */ 674 if (sc->sc_has_rcba) { 675 /* ICH6 or newer */ 676 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 677 LPCIB_TCO_TMR2); 678 ich6period &= 0xfc00; 679 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 680 LPCIB_TCO_TMR2, ich6period | period); 681 } else { 682 /* ICH5 or older */ 683 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 684 LPCIB_TCO_TMR); 685 ich5period &= 0xc0; 686 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 687 LPCIB_TCO_TMR, ich5period | period); 688 } 689 690 /* and start/reload the timer. */ 691 tcotimer_start(sc); 692 tcotimer_tickle(smw); 693 } 694 695 return 0; 696 } 697 698 static int 699 tcotimer_tickle(struct sysmon_wdog *smw) 700 { 701 struct lpcib_softc *sc = smw->smw_cookie; 702 703 /* any value is allowed */ 704 if (sc->sc_has_rcba) 705 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 706 else 707 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 708 709 return 0; 710 } 711 712 static void 713 tcotimer_stop(struct lpcib_softc *sc) 714 { 715 uint16_t ioreg; 716 717 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 718 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 719 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 720 } 721 722 static void 723 tcotimer_start(struct lpcib_softc *sc) 724 { 725 uint16_t ioreg; 726 727 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 728 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 729 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 730 } 731 732 static void 733 tcotimer_status_reset(struct lpcib_softc *sc) 734 { 735 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 736 LPCIB_TCO1_STS_TIMEOUT); 737 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 738 LPCIB_TCO2_STS_BOOT_STS); 739 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 740 LPCIB_TCO2_STS_SECONDS_TO_STS); 741 } 742 743 /* 744 * Clear the No Reboot (NR) bit, this enables reboots when the timer 745 * reaches the timeout for the second time. 746 */ 747 static int 748 tcotimer_disable_noreboot(device_t self) 749 { 750 struct lpcib_softc *sc = device_private(self); 751 752 if (sc->sc_has_rcba) { 753 uint32_t status; 754 755 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 756 LPCIB_GCS_OFFSET); 757 status &= ~LPCIB_GCS_NO_REBOOT; 758 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 759 LPCIB_GCS_OFFSET, status); 760 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 761 LPCIB_GCS_OFFSET); 762 if (status & LPCIB_GCS_NO_REBOOT) 763 goto error; 764 } else { 765 pcireg_t pcireg; 766 767 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 768 LPCIB_PCI_GEN_STA); 769 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 770 /* TCO timeout reset is disabled; try to enable it */ 771 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 772 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 773 LPCIB_PCI_GEN_STA, pcireg); 774 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 775 goto error; 776 } 777 } 778 779 return 0; 780 error: 781 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 782 "hope SMBIOS properly handles it.\n"); 783 return EINVAL; 784 } 785 786 787 /* 788 * Intel ICH SpeedStep support. 789 */ 790 #define SS_READ(sc, reg) \ 791 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 792 #define SS_WRITE(sc, reg, val) \ 793 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 794 795 /* 796 * Linux driver says that SpeedStep on older chipsets cause 797 * lockups on Dell Inspiron 8000 and 8100. 798 * It should also not be enabled on systems with the 82855GM 799 * Hub, which typically have an EST-enabled CPU. 800 */ 801 static int 802 speedstep_bad_hb_check(const struct pci_attach_args *pa) 803 { 804 805 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 806 PCI_REVISION(pa->pa_class) < 5) 807 return 1; 808 809 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 810 return 1; 811 812 return 0; 813 } 814 815 static void 816 speedstep_configure(device_t self) 817 { 818 struct lpcib_softc *sc = device_private(self); 819 const struct sysctlnode *node, *ssnode; 820 int rv; 821 822 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 823 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 824 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 825 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 826 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 827 pcireg_t pmcon; 828 829 /* Enable SpeedStep if it isn't already enabled. */ 830 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 831 LPCIB_PCI_GEN_PMCON_1); 832 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 833 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 834 LPCIB_PCI_GEN_PMCON_1, 835 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 836 837 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 838 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 839 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 840 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 841 goto err; 842 843 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 844 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 845 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 846 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 847 CTL_EOL)) != 0) 848 goto err; 849 850 /* XXX save the sc for IO tag/handle */ 851 speedstep_cookie = sc; 852 aprint_verbose_dev(self, "SpeedStep enabled\n"); 853 } 854 855 return; 856 857 err: 858 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 859 } 860 861 static void 862 speedstep_unconfigure(device_t self) 863 { 864 struct lpcib_softc *sc = device_private(self); 865 866 sysctl_teardown(&sc->sc_log); 867 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 868 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 869 870 speedstep_cookie = NULL; 871 } 872 873 /* 874 * get/set the SpeedStep state: 0 == low power, 1 == high power. 875 */ 876 static int 877 speedstep_sysctl_helper(SYSCTLFN_ARGS) 878 { 879 struct sysctlnode node; 880 struct lpcib_softc *sc = speedstep_cookie; 881 uint8_t state, state2; 882 int ostate, nstate, s, error = 0; 883 884 /* 885 * We do the dance with spl's to avoid being at high ipl during 886 * sysctl_lookup() which can both copyin and copyout. 887 */ 888 s = splserial(); 889 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 890 splx(s); 891 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 892 ostate = 1; 893 else 894 ostate = 0; 895 nstate = ostate; 896 897 node = *rnode; 898 node.sysctl_data = &nstate; 899 900 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 901 if (error || newp == NULL) 902 goto out; 903 904 /* Only two states are available */ 905 if (nstate != 0 && nstate != 1) { 906 error = EINVAL; 907 goto out; 908 } 909 910 s = splserial(); 911 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 912 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 913 ostate = 1; 914 else 915 ostate = 0; 916 917 if (ostate != nstate) { 918 uint8_t cntl; 919 920 if (nstate == 0) 921 state2 |= LPCIB_PM_SS_STATE_LOW; 922 else 923 state2 &= ~LPCIB_PM_SS_STATE_LOW; 924 925 /* 926 * Must disable bus master arbitration during the change. 927 */ 928 cntl = SS_READ(sc, LPCIB_PM_CTRL); 929 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 930 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 931 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 932 } 933 splx(s); 934 out: 935 return error; 936 } 937 938 static void 939 lpcib_hpet_configure(device_t self) 940 { 941 struct lpcib_softc *sc = device_private(self); 942 struct lpcib_hpet_attach_args arg; 943 uint32_t hpet_reg, val; 944 945 if (sc->sc_has_ich5_hpet) { 946 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 947 LPCIB_PCI_GEN_CNTL); 948 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 949 case LPCIB_ICH5_HPTC_0000: 950 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 951 break; 952 case LPCIB_ICH5_HPTC_1000: 953 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 954 break; 955 case LPCIB_ICH5_HPTC_2000: 956 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 957 break; 958 case LPCIB_ICH5_HPTC_3000: 959 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 960 break; 961 default: 962 return; 963 } 964 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 965 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 966 LPCIB_PCI_GEN_CNTL, val); 967 } else if (sc->sc_has_rcba) { 968 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 969 LPCIB_RCBA_HPTC); 970 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 971 case LPCIB_RCBA_HPTC_0000: 972 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 973 break; 974 case LPCIB_RCBA_HPTC_1000: 975 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 976 break; 977 case LPCIB_RCBA_HPTC_2000: 978 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 979 break; 980 case LPCIB_RCBA_HPTC_3000: 981 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 982 break; 983 default: 984 return; 985 } 986 val |= LPCIB_RCBA_HPTC_EN; 987 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 988 val); 989 } else { 990 /* No HPET here */ 991 return; 992 } 993 994 arg.hpet_mem_t = sc->sc_pa.pa_memt; 995 arg.hpet_reg = hpet_reg; 996 997 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 998 } 999 1000 static int 1001 lpcib_hpet_unconfigure(device_t self, int flags) 1002 { 1003 struct lpcib_softc *sc = device_private(self); 1004 int rc; 1005 1006 if (sc->sc_hpetbus != NULL && 1007 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1008 return rc; 1009 1010 return 0; 1011 } 1012 1013 #if NGPIO > 0 1014 static void 1015 lpcib_gpio_configure(device_t self) 1016 { 1017 struct lpcib_softc *sc = device_private(self); 1018 struct gpiobus_attach_args gba; 1019 pcireg_t gpio_cntl; 1020 uint32_t use, io, bit; 1021 int pin, shift, base_reg, cntl_reg, reg; 1022 int rv; 1023 1024 /* this implies ICH >= 6, and thus different mapreg */ 1025 if (sc->sc_has_rcba) { 1026 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1027 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1028 } else { 1029 base_reg = LPCIB_PCI_GPIO_BASE; 1030 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1031 } 1032 1033 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1034 cntl_reg); 1035 1036 /* Is GPIO enabled? */ 1037 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1038 return; 1039 /* 1040 * The GPIO_BASE register is alike PCI BAR but not completely 1041 * compatible with it. The PMBASE define the base address and the type 1042 * but not describe the size. 1043 */ 1044 rv = pci_mapreg_submap(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1045 LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1046 NULL, &sc->sc_gpio_ios); 1047 if (rv != 0) { 1048 aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv); 1049 return; 1050 } 1051 1052 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1053 1054 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1055 sc->sc_gpio_pins[pin].pin_num = pin; 1056 1057 /* Read initial state */ 1058 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1059 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1060 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1061 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1062 shift = pin % 32; 1063 bit = __BIT(shift); 1064 1065 if ((use & bit) != 0) { 1066 sc->sc_gpio_pins[pin].pin_caps = 1067 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1068 if (pin < 32) 1069 sc->sc_gpio_pins[pin].pin_caps |= 1070 GPIO_PIN_PULSATE; 1071 if ((io & bit) != 0) 1072 sc->sc_gpio_pins[pin].pin_flags = 1073 GPIO_PIN_INPUT; 1074 else 1075 sc->sc_gpio_pins[pin].pin_flags = 1076 GPIO_PIN_OUTPUT; 1077 } else 1078 sc->sc_gpio_pins[pin].pin_caps = 0; 1079 1080 if (lpcib_gpio_pin_read(sc, pin) == 0) 1081 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1082 else 1083 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1084 1085 } 1086 1087 /* Create controller tag */ 1088 sc->sc_gpio_gc.gp_cookie = sc; 1089 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1090 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1091 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1092 1093 memset(&gba, 0, sizeof(gba)); 1094 1095 gba.gba_gc = &sc->sc_gpio_gc; 1096 gba.gba_pins = sc->sc_gpio_pins; 1097 gba.gba_npins = LPCIB_GPIO_NPINS; 1098 1099 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1100 } 1101 1102 static int 1103 lpcib_gpio_unconfigure(device_t self, int flags) 1104 { 1105 struct lpcib_softc *sc = device_private(self); 1106 int rc; 1107 1108 if (sc->sc_gpiobus != NULL && 1109 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1110 return rc; 1111 1112 mutex_destroy(&sc->sc_gpio_mtx); 1113 1114 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1115 1116 return 0; 1117 } 1118 1119 static int 1120 lpcib_gpio_pin_read(void *arg, int pin) 1121 { 1122 struct lpcib_softc *sc = arg; 1123 uint32_t data; 1124 int reg, shift; 1125 1126 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1127 shift = pin % 32; 1128 1129 mutex_enter(&sc->sc_gpio_mtx); 1130 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1131 mutex_exit(&sc->sc_gpio_mtx); 1132 1133 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1134 } 1135 1136 static void 1137 lpcib_gpio_pin_write(void *arg, int pin, int value) 1138 { 1139 struct lpcib_softc *sc = arg; 1140 uint32_t data; 1141 int reg, shift; 1142 1143 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1144 shift = pin % 32; 1145 1146 mutex_enter(&sc->sc_gpio_mtx); 1147 1148 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1149 1150 if(value) 1151 data |= __BIT(shift); 1152 else 1153 data &= ~__BIT(shift); 1154 1155 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1156 1157 mutex_exit(&sc->sc_gpio_mtx); 1158 } 1159 1160 static void 1161 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1162 { 1163 struct lpcib_softc *sc = arg; 1164 uint32_t data; 1165 int reg, shift; 1166 1167 shift = pin % 32; 1168 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1169 1170 mutex_enter(&sc->sc_gpio_mtx); 1171 1172 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1173 1174 if (flags & GPIO_PIN_OUTPUT) 1175 data &= ~__BIT(shift); 1176 1177 if (flags & GPIO_PIN_INPUT) 1178 data |= __BIT(shift); 1179 1180 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1181 1182 1183 if (pin < 32) { 1184 reg = LPCIB_GPIO_GPO_BLINK; 1185 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1186 1187 if (flags & GPIO_PIN_PULSATE) 1188 data |= __BIT(shift); 1189 else 1190 data &= ~__BIT(shift); 1191 1192 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1193 } 1194 1195 mutex_exit(&sc->sc_gpio_mtx); 1196 } 1197 #endif 1198 1199 #if NFWHRNG > 0 1200 static void 1201 lpcib_fwh_configure(device_t self) 1202 { 1203 struct lpcib_softc *sc; 1204 pcireg_t pr; 1205 1206 sc = device_private(self); 1207 1208 if (sc->sc_has_rcba) { 1209 /* 1210 * Very unlikely to find a 82802 on a ICH6 or newer. 1211 * Also the write enable register moved at that point. 1212 */ 1213 return; 1214 } else { 1215 /* Enable FWH write to identify FWH. */ 1216 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1217 LPCIB_PCI_BIOS_CNTL); 1218 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1219 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1220 } 1221 1222 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1223 1224 /* restore previous write enable setting */ 1225 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1226 LPCIB_PCI_BIOS_CNTL, pr); 1227 } 1228 1229 static int 1230 lpcib_fwh_unconfigure(device_t self, int flags) 1231 { 1232 struct lpcib_softc *sc = device_private(self); 1233 int rc; 1234 1235 if (sc->sc_fwhbus != NULL && 1236 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1237 return rc; 1238 1239 return 0; 1240 } 1241 #endif 1242
Indexes created Wed Oct 01 18:09:54 GMT 2025