ichlpcib.c revision 1.34.6.2
1 /* $NetBSD: ichlpcib.c,v 1.34.6.2 2015/01/26 13:43:44 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.34.6.2 2015/01/26 13:43:44 martin Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 230 231 { 0, 0, 0, 0 }, 232 }; 233 234 /* 235 * Autoconf callbacks. 236 */ 237 static int 238 lpcibmatch(device_t parent, cfdata_t match, void *aux) 239 { 240 struct pci_attach_args *pa = aux; 241 struct lpcib_device *lpcib_dev; 242 243 /* We are ISA bridge, of course */ 244 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 245 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 246 return 0; 247 248 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 249 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 250 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 251 return 10; 252 } 253 254 return 0; 255 } 256 257 static void 258 lpcibattach(device_t parent, device_t self, void *aux) 259 { 260 struct pci_attach_args *pa = aux; 261 struct lpcib_softc *sc = device_private(self); 262 struct lpcib_device *lpcib_dev; 263 pcireg_t pmbase; 264 265 sc->sc_pa = *pa; 266 267 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 268 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 269 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 270 continue; 271 sc->sc_has_rcba = lpcib_dev->has_rcba; 272 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 273 break; 274 } 275 276 pcibattach(parent, self, aux); 277 278 /* 279 * Part of our I/O registers are used as ACPI PM regs. 280 * Since our ACPI subsystem accesses the I/O space directly so far, 281 * we do not have to bother bus_space I/O map confliction. 282 * 283 * The PMBASE register is alike PCI BAR but not completely compatible 284 * with it. The PMBASE define the base address and the type but 285 * not describe the size. The value of the register may be lower 286 * than LPCIB_PCI_PM_SIZE. It makes impossible to use 287 * pci_mapreg_submap() because the function does range check. 288 */ 289 sc->sc_iot = pa->pa_iot; 290 pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE); 291 if (bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(pmbase), 292 LPCIB_PCI_PM_SIZE, 0, &sc->sc_ioh) != 0) { 293 aprint_error_dev(self, 294 "can't map power management i/o space\n"); 295 return; 296 } 297 298 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 299 LPCIB_PCI_GEN_PMCON_1); 300 301 /* For ICH6 and later, always enable RCBA */ 302 if (sc->sc_has_rcba) { 303 pcireg_t rcba; 304 305 sc->sc_rcbat = sc->sc_pa.pa_memt; 306 307 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 308 LPCIB_RCBA); 309 if ((rcba & LPCIB_RCBA_EN) == 0) { 310 aprint_error_dev(self, "RCBA is not enabled\n"); 311 return; 312 } 313 rcba &= ~LPCIB_RCBA_EN; 314 315 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 316 &sc->sc_rcbah)) { 317 aprint_error_dev(self, "RCBA could not be mapped\n"); 318 return; 319 } 320 } 321 322 /* Set up the power management timer. */ 323 pmtimer_configure(self); 324 325 /* Set up the TCO (watchdog). */ 326 tcotimer_configure(self); 327 328 /* Set up SpeedStep. */ 329 speedstep_configure(self); 330 331 /* Set up HPET. */ 332 lpcib_hpet_configure(self); 333 334 #if NGPIO > 0 335 /* Set up GPIO */ 336 lpcib_gpio_configure(self); 337 #endif 338 339 #if NFWHRNG > 0 340 lpcib_fwh_configure(self); 341 #endif 342 343 /* Install power handler */ 344 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 345 lpcib_shutdown)) 346 aprint_error_dev(self, "couldn't establish power handler\n"); 347 } 348 349 static void 350 lpcibchilddet(device_t self, device_t child) 351 { 352 struct lpcib_softc *sc = device_private(self); 353 uint32_t val; 354 355 #if NFWHRNG > 0 356 if (sc->sc_fwhbus == child) { 357 sc->sc_fwhbus = NULL; 358 return; 359 } 360 #endif 361 #if NGPIO > 0 362 if (sc->sc_gpiobus == child) { 363 sc->sc_gpiobus = NULL; 364 return; 365 } 366 #endif 367 if (sc->sc_hpetbus != child) { 368 pcibchilddet(self, child); 369 return; 370 } 371 sc->sc_hpetbus = NULL; 372 if (sc->sc_has_ich5_hpet) { 373 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 374 LPCIB_PCI_GEN_CNTL); 375 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 376 case LPCIB_ICH5_HPTC_0000: 377 case LPCIB_ICH5_HPTC_1000: 378 case LPCIB_ICH5_HPTC_2000: 379 case LPCIB_ICH5_HPTC_3000: 380 break; 381 default: 382 return; 383 } 384 val &= ~LPCIB_ICH5_HPTC_EN; 385 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 386 LPCIB_PCI_GEN_CNTL, val); 387 } else if (sc->sc_has_rcba) { 388 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 389 LPCIB_RCBA_HPTC); 390 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 391 case LPCIB_RCBA_HPTC_0000: 392 case LPCIB_RCBA_HPTC_1000: 393 case LPCIB_RCBA_HPTC_2000: 394 case LPCIB_RCBA_HPTC_3000: 395 break; 396 default: 397 return; 398 } 399 val &= ~LPCIB_RCBA_HPTC_EN; 400 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 401 val); 402 } 403 } 404 405 static int 406 lpcibrescan(device_t self, const char *ifattr, const int *locators) 407 { 408 struct lpcib_softc *sc = device_private(self); 409 410 #if NFWHRNG > 0 411 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 412 lpcib_fwh_configure(self); 413 #endif 414 415 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 416 lpcib_hpet_configure(self); 417 418 #if NGPIO > 0 419 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 420 lpcib_gpio_configure(self); 421 #endif 422 423 return pcibrescan(self, ifattr, locators); 424 } 425 426 static int 427 lpcibdetach(device_t self, int flags) 428 { 429 struct lpcib_softc *sc = device_private(self); 430 int rc; 431 432 pmf_device_deregister(self); 433 434 #if NFWHRNG > 0 435 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 436 return rc; 437 #endif 438 439 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 440 return rc; 441 442 #if NGPIO > 0 443 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 444 return rc; 445 #endif 446 447 /* Set up SpeedStep. */ 448 speedstep_unconfigure(self); 449 450 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 451 return rc; 452 453 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 454 return rc; 455 456 if (sc->sc_has_rcba) 457 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 458 459 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 460 461 return pcibdetach(self, flags); 462 } 463 464 static bool 465 lpcib_shutdown(device_t dv, int howto) 466 { 467 struct lpcib_softc *sc = device_private(dv); 468 469 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 470 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 471 472 return true; 473 } 474 475 static bool 476 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 477 { 478 struct lpcib_softc *sc = device_private(dv); 479 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 480 pcitag_t tag = sc->sc_pcib.sc_tag; 481 482 /* capture PIRQ routing control registers */ 483 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 484 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 485 486 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 487 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 488 489 if (sc->sc_has_rcba) { 490 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 491 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 492 LPCIB_RCBA_HPTC); 493 } else if (sc->sc_has_ich5_hpet) { 494 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 495 } 496 497 return true; 498 } 499 500 static bool 501 lpcib_resume(device_t dv, const pmf_qual_t *qual) 502 { 503 struct lpcib_softc *sc = device_private(dv); 504 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 505 pcitag_t tag = sc->sc_pcib.sc_tag; 506 507 /* restore PIRQ routing control registers */ 508 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 509 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 510 511 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 512 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 513 514 if (sc->sc_has_rcba) { 515 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 516 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 517 sc->sc_hpet_reg); 518 } else if (sc->sc_has_ich5_hpet) { 519 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 520 } 521 522 return true; 523 } 524 525 /* 526 * Initialize the power management timer. 527 */ 528 static void 529 pmtimer_configure(device_t self) 530 { 531 struct lpcib_softc *sc = device_private(self); 532 pcireg_t control; 533 534 /* 535 * Check if power management I/O space is enabled and enable the ACPI_EN 536 * bit if it's disabled. 537 */ 538 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 539 LPCIB_PCI_ACPI_CNTL); 540 sc->sc_acpi_cntl = control; 541 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 542 control |= LPCIB_PCI_ACPI_CNTL_EN; 543 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 544 LPCIB_PCI_ACPI_CNTL, control); 545 } 546 547 /* Attach our PM timer with the generic acpipmtimer function */ 548 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 549 LPCIB_PM1_TMR, 0); 550 } 551 552 static int 553 pmtimer_unconfigure(device_t self, int flags) 554 { 555 struct lpcib_softc *sc = device_private(self); 556 int rc; 557 558 if (sc->sc_pmtimer != NULL && 559 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 560 return rc; 561 562 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 563 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 564 565 return 0; 566 } 567 568 /* 569 * Initialize the watchdog timer. 570 */ 571 static void 572 tcotimer_configure(device_t self) 573 { 574 struct lpcib_softc *sc = device_private(self); 575 uint32_t ioreg; 576 unsigned int period; 577 578 /* Explicitly stop the TCO timer. */ 579 tcotimer_stop(sc); 580 581 /* 582 * Enable TCO timeout SMI only if the hardware reset does not 583 * work. We don't know what the SMBIOS does. 584 */ 585 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 586 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 587 588 /* 589 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 590 * in the SMI_EN register is the last chance. 591 */ 592 if (tcotimer_disable_noreboot(self)) { 593 ioreg |= LPCIB_SMI_EN_TCO_EN; 594 } 595 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 596 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 597 } 598 599 /* Reset the watchdog status registers. */ 600 tcotimer_status_reset(sc); 601 602 /* 603 * Register the driver with the sysmon watchdog framework. 604 */ 605 sc->sc_smw.smw_name = device_xname(self); 606 sc->sc_smw.smw_cookie = sc; 607 sc->sc_smw.smw_setmode = tcotimer_setmode; 608 sc->sc_smw.smw_tickle = tcotimer_tickle; 609 if (sc->sc_has_rcba) 610 period = LPCIB_TCOTIMER2_MAX_TICK; 611 else 612 period = LPCIB_TCOTIMER_MAX_TICK; 613 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 614 615 if (sysmon_wdog_register(&sc->sc_smw)) { 616 aprint_error_dev(self, "unable to register TCO timer" 617 "as a sysmon watchdog device.\n"); 618 return; 619 } 620 621 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 622 } 623 624 static int 625 tcotimer_unconfigure(device_t self, int flags) 626 { 627 struct lpcib_softc *sc = device_private(self); 628 int rc; 629 630 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 631 if (rc == ERESTART) 632 rc = EINTR; 633 return rc; 634 } 635 636 /* Explicitly stop the TCO timer. */ 637 tcotimer_stop(sc); 638 639 /* XXX Set No Reboot? */ 640 641 return 0; 642 } 643 644 645 /* 646 * Sysmon watchdog callbacks. 647 */ 648 static int 649 tcotimer_setmode(struct sysmon_wdog *smw) 650 { 651 struct lpcib_softc *sc = smw->smw_cookie; 652 unsigned int period; 653 uint16_t ich6period = 0; 654 uint8_t ich5period = 0; 655 656 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 657 /* Stop the TCO timer. */ 658 tcotimer_stop(sc); 659 } else { 660 /* 661 * ICH6 or newer are limited to 2s min and 613s max. 662 * ICH5 or older are limited to 4s min and 39s max. 663 */ 664 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 665 if (sc->sc_has_rcba) { 666 if (period < LPCIB_TCOTIMER2_MIN_TICK || 667 period > LPCIB_TCOTIMER2_MAX_TICK) 668 return EINVAL; 669 } else { 670 if (period < LPCIB_TCOTIMER_MIN_TICK || 671 period > LPCIB_TCOTIMER_MAX_TICK) 672 return EINVAL; 673 } 674 675 /* Stop the TCO timer, */ 676 tcotimer_stop(sc); 677 678 /* set the timeout, */ 679 if (sc->sc_has_rcba) { 680 /* ICH6 or newer */ 681 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 682 LPCIB_TCO_TMR2); 683 ich6period &= 0xfc00; 684 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 685 LPCIB_TCO_TMR2, ich6period | period); 686 } else { 687 /* ICH5 or older */ 688 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 689 LPCIB_TCO_TMR); 690 ich5period &= 0xc0; 691 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 692 LPCIB_TCO_TMR, ich5period | period); 693 } 694 695 /* and start/reload the timer. */ 696 tcotimer_start(sc); 697 tcotimer_tickle(smw); 698 } 699 700 return 0; 701 } 702 703 static int 704 tcotimer_tickle(struct sysmon_wdog *smw) 705 { 706 struct lpcib_softc *sc = smw->smw_cookie; 707 708 /* any value is allowed */ 709 if (sc->sc_has_rcba) 710 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 711 else 712 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 713 714 return 0; 715 } 716 717 static void 718 tcotimer_stop(struct lpcib_softc *sc) 719 { 720 uint16_t ioreg; 721 722 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 723 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 724 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 725 } 726 727 static void 728 tcotimer_start(struct lpcib_softc *sc) 729 { 730 uint16_t ioreg; 731 732 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 733 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 734 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 735 } 736 737 static void 738 tcotimer_status_reset(struct lpcib_softc *sc) 739 { 740 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 741 LPCIB_TCO1_STS_TIMEOUT); 742 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 743 LPCIB_TCO2_STS_BOOT_STS); 744 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 745 LPCIB_TCO2_STS_SECONDS_TO_STS); 746 } 747 748 /* 749 * Clear the No Reboot (NR) bit, this enables reboots when the timer 750 * reaches the timeout for the second time. 751 */ 752 static int 753 tcotimer_disable_noreboot(device_t self) 754 { 755 struct lpcib_softc *sc = device_private(self); 756 757 if (sc->sc_has_rcba) { 758 uint32_t status; 759 760 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 761 LPCIB_GCS_OFFSET); 762 status &= ~LPCIB_GCS_NO_REBOOT; 763 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 764 LPCIB_GCS_OFFSET, status); 765 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 766 LPCIB_GCS_OFFSET); 767 if (status & LPCIB_GCS_NO_REBOOT) 768 goto error; 769 } else { 770 pcireg_t pcireg; 771 772 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 773 LPCIB_PCI_GEN_STA); 774 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 775 /* TCO timeout reset is disabled; try to enable it */ 776 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 777 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 778 LPCIB_PCI_GEN_STA, pcireg); 779 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 780 goto error; 781 } 782 } 783 784 return 0; 785 error: 786 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 787 "hope SMBIOS properly handles it.\n"); 788 return EINVAL; 789 } 790 791 792 /* 793 * Intel ICH SpeedStep support. 794 */ 795 #define SS_READ(sc, reg) \ 796 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 797 #define SS_WRITE(sc, reg, val) \ 798 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 799 800 /* 801 * Linux driver says that SpeedStep on older chipsets cause 802 * lockups on Dell Inspiron 8000 and 8100. 803 * It should also not be enabled on systems with the 82855GM 804 * Hub, which typically have an EST-enabled CPU. 805 */ 806 static int 807 speedstep_bad_hb_check(const struct pci_attach_args *pa) 808 { 809 810 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 811 PCI_REVISION(pa->pa_class) < 5) 812 return 1; 813 814 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 815 return 1; 816 817 return 0; 818 } 819 820 static void 821 speedstep_configure(device_t self) 822 { 823 struct lpcib_softc *sc = device_private(self); 824 const struct sysctlnode *node, *ssnode; 825 int rv; 826 827 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 828 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 829 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 830 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 831 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 832 pcireg_t pmcon; 833 834 /* Enable SpeedStep if it isn't already enabled. */ 835 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 836 LPCIB_PCI_GEN_PMCON_1); 837 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 838 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 839 LPCIB_PCI_GEN_PMCON_1, 840 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 841 842 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 843 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 844 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 845 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 846 goto err; 847 848 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 849 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 850 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 851 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 852 CTL_EOL)) != 0) 853 goto err; 854 855 /* XXX save the sc for IO tag/handle */ 856 speedstep_cookie = sc; 857 aprint_verbose_dev(self, "SpeedStep enabled\n"); 858 } 859 860 return; 861 862 err: 863 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 864 } 865 866 static void 867 speedstep_unconfigure(device_t self) 868 { 869 struct lpcib_softc *sc = device_private(self); 870 871 sysctl_teardown(&sc->sc_log); 872 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 873 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 874 875 speedstep_cookie = NULL; 876 } 877 878 /* 879 * get/set the SpeedStep state: 0 == low power, 1 == high power. 880 */ 881 static int 882 speedstep_sysctl_helper(SYSCTLFN_ARGS) 883 { 884 struct sysctlnode node; 885 struct lpcib_softc *sc = speedstep_cookie; 886 uint8_t state, state2; 887 int ostate, nstate, s, error = 0; 888 889 /* 890 * We do the dance with spl's to avoid being at high ipl during 891 * sysctl_lookup() which can both copyin and copyout. 892 */ 893 s = splserial(); 894 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 895 splx(s); 896 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 897 ostate = 1; 898 else 899 ostate = 0; 900 nstate = ostate; 901 902 node = *rnode; 903 node.sysctl_data = &nstate; 904 905 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 906 if (error || newp == NULL) 907 goto out; 908 909 /* Only two states are available */ 910 if (nstate != 0 && nstate != 1) { 911 error = EINVAL; 912 goto out; 913 } 914 915 s = splserial(); 916 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 917 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 918 ostate = 1; 919 else 920 ostate = 0; 921 922 if (ostate != nstate) { 923 uint8_t cntl; 924 925 if (nstate == 0) 926 state2 |= LPCIB_PM_SS_STATE_LOW; 927 else 928 state2 &= ~LPCIB_PM_SS_STATE_LOW; 929 930 /* 931 * Must disable bus master arbitration during the change. 932 */ 933 cntl = SS_READ(sc, LPCIB_PM_CTRL); 934 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 935 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 936 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 937 } 938 splx(s); 939 out: 940 return error; 941 } 942 943 static void 944 lpcib_hpet_configure(device_t self) 945 { 946 struct lpcib_softc *sc = device_private(self); 947 struct lpcib_hpet_attach_args arg; 948 uint32_t hpet_reg, val; 949 950 if (sc->sc_has_ich5_hpet) { 951 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 952 LPCIB_PCI_GEN_CNTL); 953 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 954 case LPCIB_ICH5_HPTC_0000: 955 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 956 break; 957 case LPCIB_ICH5_HPTC_1000: 958 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 959 break; 960 case LPCIB_ICH5_HPTC_2000: 961 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 962 break; 963 case LPCIB_ICH5_HPTC_3000: 964 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 965 break; 966 default: 967 return; 968 } 969 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 970 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 971 LPCIB_PCI_GEN_CNTL, val); 972 } else if (sc->sc_has_rcba) { 973 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 974 LPCIB_RCBA_HPTC); 975 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 976 case LPCIB_RCBA_HPTC_0000: 977 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 978 break; 979 case LPCIB_RCBA_HPTC_1000: 980 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 981 break; 982 case LPCIB_RCBA_HPTC_2000: 983 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 984 break; 985 case LPCIB_RCBA_HPTC_3000: 986 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 987 break; 988 default: 989 return; 990 } 991 val |= LPCIB_RCBA_HPTC_EN; 992 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 993 val); 994 } else { 995 /* No HPET here */ 996 return; 997 } 998 999 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1000 arg.hpet_reg = hpet_reg; 1001 1002 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1003 } 1004 1005 static int 1006 lpcib_hpet_unconfigure(device_t self, int flags) 1007 { 1008 struct lpcib_softc *sc = device_private(self); 1009 int rc; 1010 1011 if (sc->sc_hpetbus != NULL && 1012 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1013 return rc; 1014 1015 return 0; 1016 } 1017 1018 #if NGPIO > 0 1019 static void 1020 lpcib_gpio_configure(device_t self) 1021 { 1022 struct lpcib_softc *sc = device_private(self); 1023 struct gpiobus_attach_args gba; 1024 pcireg_t gpio_cntl; 1025 uint32_t use, io, bit; 1026 int pin, shift, base_reg, cntl_reg, reg; 1027 int rv; 1028 1029 /* this implies ICH >= 6, and thus different mapreg */ 1030 if (sc->sc_has_rcba) { 1031 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1032 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1033 } else { 1034 base_reg = LPCIB_PCI_GPIO_BASE; 1035 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1036 } 1037 1038 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1039 cntl_reg); 1040 1041 /* Is GPIO enabled? */ 1042 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1043 return; 1044 /* 1045 * The GPIO_BASE register is alike PCI BAR but not completely 1046 * compatible with it. The PMBASE define the base address and the type 1047 * but not describe the size. The value of the register may be lower 1048 * than LPCIB_PCI_GPIO_SIZE. It makes impossible to use 1049 * pci_mapreg_submap() because the function does range check. 1050 */ 1051 sc->sc_gpio_iot = sc->sc_pa.pa_iot; 1052 reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg); 1053 rv = bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(reg), 1054 LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_ioh); 1055 if (rv != 0) { 1056 aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv); 1057 return; 1058 } 1059 1060 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1061 1062 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1063 sc->sc_gpio_pins[pin].pin_num = pin; 1064 1065 /* Read initial state */ 1066 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1067 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1068 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1069 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1070 shift = pin % 32; 1071 bit = __BIT(shift); 1072 1073 if ((use & bit) != 0) { 1074 sc->sc_gpio_pins[pin].pin_caps = 1075 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1076 if (pin < 32) 1077 sc->sc_gpio_pins[pin].pin_caps |= 1078 GPIO_PIN_PULSATE; 1079 if ((io & bit) != 0) 1080 sc->sc_gpio_pins[pin].pin_flags = 1081 GPIO_PIN_INPUT; 1082 else 1083 sc->sc_gpio_pins[pin].pin_flags = 1084 GPIO_PIN_OUTPUT; 1085 } else 1086 sc->sc_gpio_pins[pin].pin_caps = 0; 1087 1088 if (lpcib_gpio_pin_read(sc, pin) == 0) 1089 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1090 else 1091 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1092 1093 } 1094 1095 /* Create controller tag */ 1096 sc->sc_gpio_gc.gp_cookie = sc; 1097 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1098 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1099 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1100 1101 memset(&gba, 0, sizeof(gba)); 1102 1103 gba.gba_gc = &sc->sc_gpio_gc; 1104 gba.gba_pins = sc->sc_gpio_pins; 1105 gba.gba_npins = LPCIB_GPIO_NPINS; 1106 1107 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1108 } 1109 1110 static int 1111 lpcib_gpio_unconfigure(device_t self, int flags) 1112 { 1113 struct lpcib_softc *sc = device_private(self); 1114 int rc; 1115 1116 if (sc->sc_gpiobus != NULL && 1117 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1118 return rc; 1119 1120 mutex_destroy(&sc->sc_gpio_mtx); 1121 1122 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1123 1124 return 0; 1125 } 1126 1127 static int 1128 lpcib_gpio_pin_read(void *arg, int pin) 1129 { 1130 struct lpcib_softc *sc = arg; 1131 uint32_t data; 1132 int reg, shift; 1133 1134 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1135 shift = pin % 32; 1136 1137 mutex_enter(&sc->sc_gpio_mtx); 1138 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1139 mutex_exit(&sc->sc_gpio_mtx); 1140 1141 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1142 } 1143 1144 static void 1145 lpcib_gpio_pin_write(void *arg, int pin, int value) 1146 { 1147 struct lpcib_softc *sc = arg; 1148 uint32_t data; 1149 int reg, shift; 1150 1151 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1152 shift = pin % 32; 1153 1154 mutex_enter(&sc->sc_gpio_mtx); 1155 1156 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1157 1158 if(value) 1159 data |= __BIT(shift); 1160 else 1161 data &= ~__BIT(shift); 1162 1163 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1164 1165 mutex_exit(&sc->sc_gpio_mtx); 1166 } 1167 1168 static void 1169 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1170 { 1171 struct lpcib_softc *sc = arg; 1172 uint32_t data; 1173 int reg, shift; 1174 1175 shift = pin % 32; 1176 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1177 1178 mutex_enter(&sc->sc_gpio_mtx); 1179 1180 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1181 1182 if (flags & GPIO_PIN_OUTPUT) 1183 data &= ~__BIT(shift); 1184 1185 if (flags & GPIO_PIN_INPUT) 1186 data |= __BIT(shift); 1187 1188 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1189 1190 1191 if (pin < 32) { 1192 reg = LPCIB_GPIO_GPO_BLINK; 1193 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1194 1195 if (flags & GPIO_PIN_PULSATE) 1196 data |= __BIT(shift); 1197 else 1198 data &= ~__BIT(shift); 1199 1200 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1201 } 1202 1203 mutex_exit(&sc->sc_gpio_mtx); 1204 } 1205 #endif 1206 1207 #if NFWHRNG > 0 1208 static void 1209 lpcib_fwh_configure(device_t self) 1210 { 1211 struct lpcib_softc *sc; 1212 pcireg_t pr; 1213 1214 sc = device_private(self); 1215 1216 if (sc->sc_has_rcba) { 1217 /* 1218 * Very unlikely to find a 82802 on a ICH6 or newer. 1219 * Also the write enable register moved at that point. 1220 */ 1221 return; 1222 } else { 1223 /* Enable FWH write to identify FWH. */ 1224 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1225 LPCIB_PCI_BIOS_CNTL); 1226 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1227 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1228 } 1229 1230 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1231 1232 /* restore previous write enable setting */ 1233 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1234 LPCIB_PCI_BIOS_CNTL, pr); 1235 } 1236 1237 static int 1238 lpcib_fwh_unconfigure(device_t self, int flags) 1239 { 1240 struct lpcib_softc *sc = device_private(self); 1241 int rc; 1242 1243 if (sc->sc_fwhbus != NULL && 1244 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1245 return rc; 1246 1247 return 0; 1248 } 1249 #endif 1250
Indexes created Wed Oct 01 15:09:59 GMT 2025