ichlpcib.c revision 1.35
1 /* $NetBSD: ichlpcib.c,v 1.35 2012/12/06 10:32:44 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.35 2012/12/06 10:32:44 msaitoh Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 220 221 { 0, 0, 0, 0 }, 222 }; 223 224 /* 225 * Autoconf callbacks. 226 */ 227 static int 228 lpcibmatch(device_t parent, cfdata_t match, void *aux) 229 { 230 struct pci_attach_args *pa = aux; 231 struct lpcib_device *lpcib_dev; 232 233 /* We are ISA bridge, of course */ 234 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 235 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 236 return 0; 237 238 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 239 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 240 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 241 return 10; 242 } 243 244 return 0; 245 } 246 247 static void 248 lpcibattach(device_t parent, device_t self, void *aux) 249 { 250 struct pci_attach_args *pa = aux; 251 struct lpcib_softc *sc = device_private(self); 252 struct lpcib_device *lpcib_dev; 253 254 sc->sc_pa = *pa; 255 256 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 257 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 258 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 259 continue; 260 sc->sc_has_rcba = lpcib_dev->has_rcba; 261 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 262 break; 263 } 264 265 pcibattach(parent, self, aux); 266 267 /* 268 * Part of our I/O registers are used as ACPI PM regs. 269 * Since our ACPI subsystem accesses the I/O space directly so far, 270 * we do not have to bother bus_space I/O map confliction. 271 */ 272 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 273 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 274 aprint_error_dev(self, "can't map power management i/o space"); 275 return; 276 } 277 278 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 279 LPCIB_PCI_GEN_PMCON_1); 280 281 /* For ICH6 and later, always enable RCBA */ 282 if (sc->sc_has_rcba) { 283 pcireg_t rcba; 284 285 sc->sc_rcbat = sc->sc_pa.pa_memt; 286 287 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 288 LPCIB_RCBA); 289 if ((rcba & LPCIB_RCBA_EN) == 0) { 290 aprint_error_dev(self, "RCBA is not enabled"); 291 return; 292 } 293 rcba &= ~LPCIB_RCBA_EN; 294 295 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 296 &sc->sc_rcbah)) { 297 aprint_error_dev(self, "RCBA could not be mapped"); 298 return; 299 } 300 } 301 302 /* Set up the power management timer. */ 303 pmtimer_configure(self); 304 305 /* Set up the TCO (watchdog). */ 306 tcotimer_configure(self); 307 308 /* Set up SpeedStep. */ 309 speedstep_configure(self); 310 311 /* Set up HPET. */ 312 lpcib_hpet_configure(self); 313 314 #if NGPIO > 0 315 /* Set up GPIO */ 316 lpcib_gpio_configure(self); 317 #endif 318 319 #if NFWHRNG > 0 320 lpcib_fwh_configure(self); 321 #endif 322 323 /* Install power handler */ 324 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 325 lpcib_shutdown)) 326 aprint_error_dev(self, "couldn't establish power handler\n"); 327 } 328 329 static void 330 lpcibchilddet(device_t self, device_t child) 331 { 332 struct lpcib_softc *sc = device_private(self); 333 uint32_t val; 334 335 #if NFWHRNG > 0 336 if (sc->sc_fwhbus == child) { 337 sc->sc_fwhbus = NULL; 338 return; 339 } 340 #endif 341 #if NGPIO > 0 342 if (sc->sc_gpiobus == child) { 343 sc->sc_gpiobus = NULL; 344 return; 345 } 346 #endif 347 if (sc->sc_hpetbus != child) { 348 pcibchilddet(self, child); 349 return; 350 } 351 sc->sc_hpetbus = NULL; 352 if (sc->sc_has_ich5_hpet) { 353 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 354 LPCIB_PCI_GEN_CNTL); 355 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 356 case LPCIB_ICH5_HPTC_0000: 357 case LPCIB_ICH5_HPTC_1000: 358 case LPCIB_ICH5_HPTC_2000: 359 case LPCIB_ICH5_HPTC_3000: 360 break; 361 default: 362 return; 363 } 364 val &= ~LPCIB_ICH5_HPTC_EN; 365 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 366 LPCIB_PCI_GEN_CNTL, val); 367 } else if (sc->sc_has_rcba) { 368 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 369 LPCIB_RCBA_HPTC); 370 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 371 case LPCIB_RCBA_HPTC_0000: 372 case LPCIB_RCBA_HPTC_1000: 373 case LPCIB_RCBA_HPTC_2000: 374 case LPCIB_RCBA_HPTC_3000: 375 break; 376 default: 377 return; 378 } 379 val &= ~LPCIB_RCBA_HPTC_EN; 380 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 381 val); 382 } 383 } 384 385 static int 386 lpcibrescan(device_t self, const char *ifattr, const int *locators) 387 { 388 struct lpcib_softc *sc = device_private(self); 389 390 #if NFWHRNG > 0 391 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 392 lpcib_fwh_configure(self); 393 #endif 394 395 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 396 lpcib_hpet_configure(self); 397 398 #if NGPIO > 0 399 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 400 lpcib_gpio_configure(self); 401 #endif 402 403 return pcibrescan(self, ifattr, locators); 404 } 405 406 static int 407 lpcibdetach(device_t self, int flags) 408 { 409 struct lpcib_softc *sc = device_private(self); 410 int rc; 411 412 pmf_device_deregister(self); 413 414 #if NFWHRNG > 0 415 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 416 return rc; 417 #endif 418 419 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 420 return rc; 421 422 #if NGPIO > 0 423 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 424 return rc; 425 #endif 426 427 /* Set up SpeedStep. */ 428 speedstep_unconfigure(self); 429 430 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 431 return rc; 432 433 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 434 return rc; 435 436 if (sc->sc_has_rcba) 437 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 438 439 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 440 441 return pcibdetach(self, flags); 442 } 443 444 static bool 445 lpcib_shutdown(device_t dv, int howto) 446 { 447 struct lpcib_softc *sc = device_private(dv); 448 449 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 450 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 451 452 return true; 453 } 454 455 static bool 456 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 457 { 458 struct lpcib_softc *sc = device_private(dv); 459 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 460 pcitag_t tag = sc->sc_pcib.sc_tag; 461 462 /* capture PIRQ routing control registers */ 463 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 464 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 465 466 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 467 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 468 469 if (sc->sc_has_rcba) { 470 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 471 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 472 LPCIB_RCBA_HPTC); 473 } else if (sc->sc_has_ich5_hpet) { 474 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 475 } 476 477 return true; 478 } 479 480 static bool 481 lpcib_resume(device_t dv, const pmf_qual_t *qual) 482 { 483 struct lpcib_softc *sc = device_private(dv); 484 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 485 pcitag_t tag = sc->sc_pcib.sc_tag; 486 487 /* restore PIRQ routing control registers */ 488 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 489 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 490 491 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 492 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 493 494 if (sc->sc_has_rcba) { 495 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 496 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 497 sc->sc_hpet_reg); 498 } else if (sc->sc_has_ich5_hpet) { 499 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 500 } 501 502 return true; 503 } 504 505 /* 506 * Initialize the power management timer. 507 */ 508 static void 509 pmtimer_configure(device_t self) 510 { 511 struct lpcib_softc *sc = device_private(self); 512 pcireg_t control; 513 514 /* 515 * Check if power management I/O space is enabled and enable the ACPI_EN 516 * bit if it's disabled. 517 */ 518 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 519 LPCIB_PCI_ACPI_CNTL); 520 sc->sc_acpi_cntl = control; 521 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 522 control |= LPCIB_PCI_ACPI_CNTL_EN; 523 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 524 LPCIB_PCI_ACPI_CNTL, control); 525 } 526 527 /* Attach our PM timer with the generic acpipmtimer function */ 528 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 529 LPCIB_PM1_TMR, 0); 530 } 531 532 static int 533 pmtimer_unconfigure(device_t self, int flags) 534 { 535 struct lpcib_softc *sc = device_private(self); 536 int rc; 537 538 if (sc->sc_pmtimer != NULL && 539 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 540 return rc; 541 542 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 543 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 544 545 return 0; 546 } 547 548 /* 549 * Initialize the watchdog timer. 550 */ 551 static void 552 tcotimer_configure(device_t self) 553 { 554 struct lpcib_softc *sc = device_private(self); 555 uint32_t ioreg; 556 unsigned int period; 557 558 /* Explicitly stop the TCO timer. */ 559 tcotimer_stop(sc); 560 561 /* 562 * Enable TCO timeout SMI only if the hardware reset does not 563 * work. We don't know what the SMBIOS does. 564 */ 565 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 566 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 567 568 /* 569 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 570 * in the SMI_EN register is the last chance. 571 */ 572 if (tcotimer_disable_noreboot(self)) { 573 ioreg |= LPCIB_SMI_EN_TCO_EN; 574 } 575 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 576 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 577 } 578 579 /* Reset the watchdog status registers. */ 580 tcotimer_status_reset(sc); 581 582 /* 583 * Register the driver with the sysmon watchdog framework. 584 */ 585 sc->sc_smw.smw_name = device_xname(self); 586 sc->sc_smw.smw_cookie = sc; 587 sc->sc_smw.smw_setmode = tcotimer_setmode; 588 sc->sc_smw.smw_tickle = tcotimer_tickle; 589 if (sc->sc_has_rcba) 590 period = LPCIB_TCOTIMER2_MAX_TICK; 591 else 592 period = LPCIB_TCOTIMER_MAX_TICK; 593 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 594 595 if (sysmon_wdog_register(&sc->sc_smw)) { 596 aprint_error_dev(self, "unable to register TCO timer" 597 "as a sysmon watchdog device.\n"); 598 return; 599 } 600 601 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 602 } 603 604 static int 605 tcotimer_unconfigure(device_t self, int flags) 606 { 607 struct lpcib_softc *sc = device_private(self); 608 int rc; 609 610 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 611 if (rc == ERESTART) 612 rc = EINTR; 613 return rc; 614 } 615 616 /* Explicitly stop the TCO timer. */ 617 tcotimer_stop(sc); 618 619 /* XXX Set No Reboot? */ 620 621 return 0; 622 } 623 624 625 /* 626 * Sysmon watchdog callbacks. 627 */ 628 static int 629 tcotimer_setmode(struct sysmon_wdog *smw) 630 { 631 struct lpcib_softc *sc = smw->smw_cookie; 632 unsigned int period; 633 uint16_t ich6period = 0; 634 uint8_t ich5period = 0; 635 636 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 637 /* Stop the TCO timer. */ 638 tcotimer_stop(sc); 639 } else { 640 /* 641 * ICH6 or newer are limited to 2s min and 613s max. 642 * ICH5 or older are limited to 4s min and 39s max. 643 */ 644 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 645 if (sc->sc_has_rcba) { 646 if (period < LPCIB_TCOTIMER2_MIN_TICK || 647 period > LPCIB_TCOTIMER2_MAX_TICK) 648 return EINVAL; 649 } else { 650 if (period < LPCIB_TCOTIMER_MIN_TICK || 651 period > LPCIB_TCOTIMER_MAX_TICK) 652 return EINVAL; 653 } 654 655 /* Stop the TCO timer, */ 656 tcotimer_stop(sc); 657 658 /* set the timeout, */ 659 if (sc->sc_has_rcba) { 660 /* ICH6 or newer */ 661 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 662 LPCIB_TCO_TMR2); 663 ich6period &= 0xfc00; 664 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 665 LPCIB_TCO_TMR2, ich6period | period); 666 } else { 667 /* ICH5 or older */ 668 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 669 LPCIB_TCO_TMR); 670 ich5period &= 0xc0; 671 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 672 LPCIB_TCO_TMR, ich5period | period); 673 } 674 675 /* and start/reload the timer. */ 676 tcotimer_start(sc); 677 tcotimer_tickle(smw); 678 } 679 680 return 0; 681 } 682 683 static int 684 tcotimer_tickle(struct sysmon_wdog *smw) 685 { 686 struct lpcib_softc *sc = smw->smw_cookie; 687 688 /* any value is allowed */ 689 if (sc->sc_has_rcba) 690 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 691 else 692 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 693 694 return 0; 695 } 696 697 static void 698 tcotimer_stop(struct lpcib_softc *sc) 699 { 700 uint16_t ioreg; 701 702 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 703 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 704 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 705 } 706 707 static void 708 tcotimer_start(struct lpcib_softc *sc) 709 { 710 uint16_t ioreg; 711 712 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 713 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 714 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 715 } 716 717 static void 718 tcotimer_status_reset(struct lpcib_softc *sc) 719 { 720 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 721 LPCIB_TCO1_STS_TIMEOUT); 722 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 723 LPCIB_TCO2_STS_BOOT_STS); 724 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 725 LPCIB_TCO2_STS_SECONDS_TO_STS); 726 } 727 728 /* 729 * Clear the No Reboot (NR) bit, this enables reboots when the timer 730 * reaches the timeout for the second time. 731 */ 732 static int 733 tcotimer_disable_noreboot(device_t self) 734 { 735 struct lpcib_softc *sc = device_private(self); 736 737 if (sc->sc_has_rcba) { 738 uint32_t status; 739 740 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 741 LPCIB_GCS_OFFSET); 742 status &= ~LPCIB_GCS_NO_REBOOT; 743 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 744 LPCIB_GCS_OFFSET, status); 745 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 746 LPCIB_GCS_OFFSET); 747 if (status & LPCIB_GCS_NO_REBOOT) 748 goto error; 749 } else { 750 pcireg_t pcireg; 751 752 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 753 LPCIB_PCI_GEN_STA); 754 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 755 /* TCO timeout reset is disabled; try to enable it */ 756 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 757 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 758 LPCIB_PCI_GEN_STA, pcireg); 759 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 760 goto error; 761 } 762 } 763 764 return 0; 765 error: 766 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 767 "hope SMBIOS properly handles it.\n"); 768 return EINVAL; 769 } 770 771 772 /* 773 * Intel ICH SpeedStep support. 774 */ 775 #define SS_READ(sc, reg) \ 776 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 777 #define SS_WRITE(sc, reg, val) \ 778 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 779 780 /* 781 * Linux driver says that SpeedStep on older chipsets cause 782 * lockups on Dell Inspiron 8000 and 8100. 783 * It should also not be enabled on systems with the 82855GM 784 * Hub, which typically have an EST-enabled CPU. 785 */ 786 static int 787 speedstep_bad_hb_check(const struct pci_attach_args *pa) 788 { 789 790 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 791 PCI_REVISION(pa->pa_class) < 5) 792 return 1; 793 794 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 795 return 1; 796 797 return 0; 798 } 799 800 static void 801 speedstep_configure(device_t self) 802 { 803 struct lpcib_softc *sc = device_private(self); 804 const struct sysctlnode *node, *ssnode; 805 int rv; 806 807 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 808 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 809 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 810 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 811 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 812 pcireg_t pmcon; 813 814 /* Enable SpeedStep if it isn't already enabled. */ 815 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 816 LPCIB_PCI_GEN_PMCON_1); 817 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 818 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 819 LPCIB_PCI_GEN_PMCON_1, 820 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 821 822 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 823 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 824 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 825 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 826 goto err; 827 828 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 829 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 830 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 831 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 832 CTL_EOL)) != 0) 833 goto err; 834 835 /* XXX save the sc for IO tag/handle */ 836 speedstep_cookie = sc; 837 aprint_verbose_dev(self, "SpeedStep enabled\n"); 838 } 839 840 return; 841 842 err: 843 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 844 } 845 846 static void 847 speedstep_unconfigure(device_t self) 848 { 849 struct lpcib_softc *sc = device_private(self); 850 851 sysctl_teardown(&sc->sc_log); 852 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 853 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 854 855 speedstep_cookie = NULL; 856 } 857 858 /* 859 * get/set the SpeedStep state: 0 == low power, 1 == high power. 860 */ 861 static int 862 speedstep_sysctl_helper(SYSCTLFN_ARGS) 863 { 864 struct sysctlnode node; 865 struct lpcib_softc *sc = speedstep_cookie; 866 uint8_t state, state2; 867 int ostate, nstate, s, error = 0; 868 869 /* 870 * We do the dance with spl's to avoid being at high ipl during 871 * sysctl_lookup() which can both copyin and copyout. 872 */ 873 s = splserial(); 874 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 875 splx(s); 876 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 877 ostate = 1; 878 else 879 ostate = 0; 880 nstate = ostate; 881 882 node = *rnode; 883 node.sysctl_data = &nstate; 884 885 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 886 if (error || newp == NULL) 887 goto out; 888 889 /* Only two states are available */ 890 if (nstate != 0 && nstate != 1) { 891 error = EINVAL; 892 goto out; 893 } 894 895 s = splserial(); 896 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 897 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 898 ostate = 1; 899 else 900 ostate = 0; 901 902 if (ostate != nstate) { 903 uint8_t cntl; 904 905 if (nstate == 0) 906 state2 |= LPCIB_PM_SS_STATE_LOW; 907 else 908 state2 &= ~LPCIB_PM_SS_STATE_LOW; 909 910 /* 911 * Must disable bus master arbitration during the change. 912 */ 913 cntl = SS_READ(sc, LPCIB_PM_CTRL); 914 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 915 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 916 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 917 } 918 splx(s); 919 out: 920 return error; 921 } 922 923 static void 924 lpcib_hpet_configure(device_t self) 925 { 926 struct lpcib_softc *sc = device_private(self); 927 struct lpcib_hpet_attach_args arg; 928 uint32_t hpet_reg, val; 929 930 if (sc->sc_has_ich5_hpet) { 931 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 932 LPCIB_PCI_GEN_CNTL); 933 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 934 case LPCIB_ICH5_HPTC_0000: 935 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 936 break; 937 case LPCIB_ICH5_HPTC_1000: 938 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 939 break; 940 case LPCIB_ICH5_HPTC_2000: 941 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 942 break; 943 case LPCIB_ICH5_HPTC_3000: 944 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 945 break; 946 default: 947 return; 948 } 949 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 950 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 951 LPCIB_PCI_GEN_CNTL, val); 952 } else if (sc->sc_has_rcba) { 953 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 954 LPCIB_RCBA_HPTC); 955 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 956 case LPCIB_RCBA_HPTC_0000: 957 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 958 break; 959 case LPCIB_RCBA_HPTC_1000: 960 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 961 break; 962 case LPCIB_RCBA_HPTC_2000: 963 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 964 break; 965 case LPCIB_RCBA_HPTC_3000: 966 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 967 break; 968 default: 969 return; 970 } 971 val |= LPCIB_RCBA_HPTC_EN; 972 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 973 val); 974 } else { 975 /* No HPET here */ 976 return; 977 } 978 979 arg.hpet_mem_t = sc->sc_pa.pa_memt; 980 arg.hpet_reg = hpet_reg; 981 982 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 983 } 984 985 static int 986 lpcib_hpet_unconfigure(device_t self, int flags) 987 { 988 struct lpcib_softc *sc = device_private(self); 989 int rc; 990 991 if (sc->sc_hpetbus != NULL && 992 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 993 return rc; 994 995 return 0; 996 } 997 998 #if NGPIO > 0 999 static void 1000 lpcib_gpio_configure(device_t self) 1001 { 1002 struct lpcib_softc *sc = device_private(self); 1003 struct gpiobus_attach_args gba; 1004 pcireg_t gpio_cntl; 1005 uint32_t use, io, bit; 1006 int pin, shift, base_reg, cntl_reg, reg; 1007 1008 /* this implies ICH >= 6, and thus different mapreg */ 1009 if (sc->sc_has_rcba) { 1010 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1011 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1012 } else { 1013 base_reg = LPCIB_PCI_GPIO_BASE; 1014 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1015 } 1016 1017 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1018 cntl_reg); 1019 1020 /* Is GPIO enabled? */ 1021 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1022 return; 1023 1024 if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1025 &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1026 NULL, &sc->sc_gpio_ios)) { 1027 aprint_error_dev(self, "can't map general purpose i/o space\n"); 1028 return; 1029 } 1030 1031 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1032 1033 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1034 sc->sc_gpio_pins[pin].pin_num = pin; 1035 1036 /* Read initial state */ 1037 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1038 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1039 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1040 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1041 shift = pin % 32; 1042 bit = __BIT(shift); 1043 1044 if ((use & bit) != 0) { 1045 sc->sc_gpio_pins[pin].pin_caps = 1046 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1047 if (pin < 32) 1048 sc->sc_gpio_pins[pin].pin_caps |= 1049 GPIO_PIN_PULSATE; 1050 if ((io & bit) != 0) 1051 sc->sc_gpio_pins[pin].pin_flags = 1052 GPIO_PIN_INPUT; 1053 else 1054 sc->sc_gpio_pins[pin].pin_flags = 1055 GPIO_PIN_OUTPUT; 1056 } else 1057 sc->sc_gpio_pins[pin].pin_caps = 0; 1058 1059 if (lpcib_gpio_pin_read(sc, pin) == 0) 1060 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1061 else 1062 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1063 1064 } 1065 1066 /* Create controller tag */ 1067 sc->sc_gpio_gc.gp_cookie = sc; 1068 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1069 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1070 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1071 1072 memset(&gba, 0, sizeof(gba)); 1073 1074 gba.gba_gc = &sc->sc_gpio_gc; 1075 gba.gba_pins = sc->sc_gpio_pins; 1076 gba.gba_npins = LPCIB_GPIO_NPINS; 1077 1078 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1079 } 1080 1081 static int 1082 lpcib_gpio_unconfigure(device_t self, int flags) 1083 { 1084 struct lpcib_softc *sc = device_private(self); 1085 int rc; 1086 1087 if (sc->sc_gpiobus != NULL && 1088 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1089 return rc; 1090 1091 mutex_destroy(&sc->sc_gpio_mtx); 1092 1093 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1094 1095 return 0; 1096 } 1097 1098 static int 1099 lpcib_gpio_pin_read(void *arg, int pin) 1100 { 1101 struct lpcib_softc *sc = arg; 1102 uint32_t data; 1103 int reg, shift; 1104 1105 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1106 shift = pin % 32; 1107 1108 mutex_enter(&sc->sc_gpio_mtx); 1109 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1110 mutex_exit(&sc->sc_gpio_mtx); 1111 1112 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1113 } 1114 1115 static void 1116 lpcib_gpio_pin_write(void *arg, int pin, int value) 1117 { 1118 struct lpcib_softc *sc = arg; 1119 uint32_t data; 1120 int reg, shift; 1121 1122 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1123 shift = pin % 32; 1124 1125 mutex_enter(&sc->sc_gpio_mtx); 1126 1127 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1128 1129 if(value) 1130 data |= __BIT(shift); 1131 else 1132 data &= ~__BIT(shift); 1133 1134 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1135 1136 mutex_exit(&sc->sc_gpio_mtx); 1137 } 1138 1139 static void 1140 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1141 { 1142 struct lpcib_softc *sc = arg; 1143 uint32_t data; 1144 int reg, shift; 1145 1146 shift = pin % 32; 1147 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1148 1149 mutex_enter(&sc->sc_gpio_mtx); 1150 1151 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1152 1153 if (flags & GPIO_PIN_OUTPUT) 1154 data &= ~__BIT(shift); 1155 1156 if (flags & GPIO_PIN_INPUT) 1157 data |= __BIT(shift); 1158 1159 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1160 1161 1162 if (pin < 32) { 1163 reg = LPCIB_GPIO_GPO_BLINK; 1164 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1165 1166 if (flags & GPIO_PIN_PULSATE) 1167 data |= __BIT(shift); 1168 else 1169 data &= ~__BIT(shift); 1170 1171 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1172 } 1173 1174 mutex_exit(&sc->sc_gpio_mtx); 1175 } 1176 #endif 1177 1178 #if NFWHRNG > 0 1179 static void 1180 lpcib_fwh_configure(device_t self) 1181 { 1182 struct lpcib_softc *sc; 1183 pcireg_t pr; 1184 1185 sc = device_private(self); 1186 1187 if (sc->sc_has_rcba) { 1188 /* 1189 * Very unlikely to find a 82802 on a ICH6 or newer. 1190 * Also the write enable register moved at that point. 1191 */ 1192 return; 1193 } else { 1194 /* Enable FWH write to identify FWH. */ 1195 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1196 LPCIB_PCI_BIOS_CNTL); 1197 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1198 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1199 } 1200 1201 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1202 1203 /* restore previous write enable setting */ 1204 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1205 LPCIB_PCI_BIOS_CNTL, pr); 1206 } 1207 1208 static int 1209 lpcib_fwh_unconfigure(device_t self, int flags) 1210 { 1211 struct lpcib_softc *sc = device_private(self); 1212 int rc; 1213 1214 if (sc->sc_fwhbus != NULL && 1215 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1216 return rc; 1217 1218 return 0; 1219 } 1220 #endif 1221
Indexes created Tue Sep 30 17:09:57 GMT 2025