ichlpcib.c revision 1.36
1 /* $NetBSD: ichlpcib.c,v 1.36 2012/12/06 12:50:09 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.36 2012/12/06 12:50:09 msaitoh Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 237 { 0, 0, 0, 0 }, 238 }; 239 240 /* 241 * Autoconf callbacks. 242 */ 243 static int 244 lpcibmatch(device_t parent, cfdata_t match, void *aux) 245 { 246 struct pci_attach_args *pa = aux; 247 struct lpcib_device *lpcib_dev; 248 249 /* We are ISA bridge, of course */ 250 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 251 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 252 return 0; 253 254 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 255 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 256 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 257 return 10; 258 } 259 260 return 0; 261 } 262 263 static void 264 lpcibattach(device_t parent, device_t self, void *aux) 265 { 266 struct pci_attach_args *pa = aux; 267 struct lpcib_softc *sc = device_private(self); 268 struct lpcib_device *lpcib_dev; 269 270 sc->sc_pa = *pa; 271 272 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 273 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 274 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 275 continue; 276 sc->sc_has_rcba = lpcib_dev->has_rcba; 277 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 278 break; 279 } 280 281 pcibattach(parent, self, aux); 282 283 /* 284 * Part of our I/O registers are used as ACPI PM regs. 285 * Since our ACPI subsystem accesses the I/O space directly so far, 286 * we do not have to bother bus_space I/O map confliction. 287 */ 288 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 289 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 290 aprint_error_dev(self, "can't map power management i/o space"); 291 return; 292 } 293 294 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 295 LPCIB_PCI_GEN_PMCON_1); 296 297 /* For ICH6 and later, always enable RCBA */ 298 if (sc->sc_has_rcba) { 299 pcireg_t rcba; 300 301 sc->sc_rcbat = sc->sc_pa.pa_memt; 302 303 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 304 LPCIB_RCBA); 305 if ((rcba & LPCIB_RCBA_EN) == 0) { 306 aprint_error_dev(self, "RCBA is not enabled"); 307 return; 308 } 309 rcba &= ~LPCIB_RCBA_EN; 310 311 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 312 &sc->sc_rcbah)) { 313 aprint_error_dev(self, "RCBA could not be mapped"); 314 return; 315 } 316 } 317 318 /* Set up the power management timer. */ 319 pmtimer_configure(self); 320 321 /* Set up the TCO (watchdog). */ 322 tcotimer_configure(self); 323 324 /* Set up SpeedStep. */ 325 speedstep_configure(self); 326 327 /* Set up HPET. */ 328 lpcib_hpet_configure(self); 329 330 #if NGPIO > 0 331 /* Set up GPIO */ 332 lpcib_gpio_configure(self); 333 #endif 334 335 #if NFWHRNG > 0 336 lpcib_fwh_configure(self); 337 #endif 338 339 /* Install power handler */ 340 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 341 lpcib_shutdown)) 342 aprint_error_dev(self, "couldn't establish power handler\n"); 343 } 344 345 static void 346 lpcibchilddet(device_t self, device_t child) 347 { 348 struct lpcib_softc *sc = device_private(self); 349 uint32_t val; 350 351 #if NFWHRNG > 0 352 if (sc->sc_fwhbus == child) { 353 sc->sc_fwhbus = NULL; 354 return; 355 } 356 #endif 357 #if NGPIO > 0 358 if (sc->sc_gpiobus == child) { 359 sc->sc_gpiobus = NULL; 360 return; 361 } 362 #endif 363 if (sc->sc_hpetbus != child) { 364 pcibchilddet(self, child); 365 return; 366 } 367 sc->sc_hpetbus = NULL; 368 if (sc->sc_has_ich5_hpet) { 369 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 370 LPCIB_PCI_GEN_CNTL); 371 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 372 case LPCIB_ICH5_HPTC_0000: 373 case LPCIB_ICH5_HPTC_1000: 374 case LPCIB_ICH5_HPTC_2000: 375 case LPCIB_ICH5_HPTC_3000: 376 break; 377 default: 378 return; 379 } 380 val &= ~LPCIB_ICH5_HPTC_EN; 381 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 382 LPCIB_PCI_GEN_CNTL, val); 383 } else if (sc->sc_has_rcba) { 384 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 385 LPCIB_RCBA_HPTC); 386 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 387 case LPCIB_RCBA_HPTC_0000: 388 case LPCIB_RCBA_HPTC_1000: 389 case LPCIB_RCBA_HPTC_2000: 390 case LPCIB_RCBA_HPTC_3000: 391 break; 392 default: 393 return; 394 } 395 val &= ~LPCIB_RCBA_HPTC_EN; 396 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 397 val); 398 } 399 } 400 401 static int 402 lpcibrescan(device_t self, const char *ifattr, const int *locators) 403 { 404 struct lpcib_softc *sc = device_private(self); 405 406 #if NFWHRNG > 0 407 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 408 lpcib_fwh_configure(self); 409 #endif 410 411 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 412 lpcib_hpet_configure(self); 413 414 #if NGPIO > 0 415 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 416 lpcib_gpio_configure(self); 417 #endif 418 419 return pcibrescan(self, ifattr, locators); 420 } 421 422 static int 423 lpcibdetach(device_t self, int flags) 424 { 425 struct lpcib_softc *sc = device_private(self); 426 int rc; 427 428 pmf_device_deregister(self); 429 430 #if NFWHRNG > 0 431 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 432 return rc; 433 #endif 434 435 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 436 return rc; 437 438 #if NGPIO > 0 439 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 440 return rc; 441 #endif 442 443 /* Set up SpeedStep. */ 444 speedstep_unconfigure(self); 445 446 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 447 return rc; 448 449 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 450 return rc; 451 452 if (sc->sc_has_rcba) 453 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 454 455 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 456 457 return pcibdetach(self, flags); 458 } 459 460 static bool 461 lpcib_shutdown(device_t dv, int howto) 462 { 463 struct lpcib_softc *sc = device_private(dv); 464 465 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 466 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 467 468 return true; 469 } 470 471 static bool 472 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 473 { 474 struct lpcib_softc *sc = device_private(dv); 475 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 476 pcitag_t tag = sc->sc_pcib.sc_tag; 477 478 /* capture PIRQ routing control registers */ 479 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 480 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 481 482 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 483 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 484 485 if (sc->sc_has_rcba) { 486 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 487 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 488 LPCIB_RCBA_HPTC); 489 } else if (sc->sc_has_ich5_hpet) { 490 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 491 } 492 493 return true; 494 } 495 496 static bool 497 lpcib_resume(device_t dv, const pmf_qual_t *qual) 498 { 499 struct lpcib_softc *sc = device_private(dv); 500 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 501 pcitag_t tag = sc->sc_pcib.sc_tag; 502 503 /* restore PIRQ routing control registers */ 504 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 505 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 506 507 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 508 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 509 510 if (sc->sc_has_rcba) { 511 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 512 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 513 sc->sc_hpet_reg); 514 } else if (sc->sc_has_ich5_hpet) { 515 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 516 } 517 518 return true; 519 } 520 521 /* 522 * Initialize the power management timer. 523 */ 524 static void 525 pmtimer_configure(device_t self) 526 { 527 struct lpcib_softc *sc = device_private(self); 528 pcireg_t control; 529 530 /* 531 * Check if power management I/O space is enabled and enable the ACPI_EN 532 * bit if it's disabled. 533 */ 534 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 535 LPCIB_PCI_ACPI_CNTL); 536 sc->sc_acpi_cntl = control; 537 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 538 control |= LPCIB_PCI_ACPI_CNTL_EN; 539 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 540 LPCIB_PCI_ACPI_CNTL, control); 541 } 542 543 /* Attach our PM timer with the generic acpipmtimer function */ 544 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 545 LPCIB_PM1_TMR, 0); 546 } 547 548 static int 549 pmtimer_unconfigure(device_t self, int flags) 550 { 551 struct lpcib_softc *sc = device_private(self); 552 int rc; 553 554 if (sc->sc_pmtimer != NULL && 555 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 556 return rc; 557 558 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 559 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 560 561 return 0; 562 } 563 564 /* 565 * Initialize the watchdog timer. 566 */ 567 static void 568 tcotimer_configure(device_t self) 569 { 570 struct lpcib_softc *sc = device_private(self); 571 uint32_t ioreg; 572 unsigned int period; 573 574 /* Explicitly stop the TCO timer. */ 575 tcotimer_stop(sc); 576 577 /* 578 * Enable TCO timeout SMI only if the hardware reset does not 579 * work. We don't know what the SMBIOS does. 580 */ 581 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 582 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 583 584 /* 585 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 586 * in the SMI_EN register is the last chance. 587 */ 588 if (tcotimer_disable_noreboot(self)) { 589 ioreg |= LPCIB_SMI_EN_TCO_EN; 590 } 591 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 592 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 593 } 594 595 /* Reset the watchdog status registers. */ 596 tcotimer_status_reset(sc); 597 598 /* 599 * Register the driver with the sysmon watchdog framework. 600 */ 601 sc->sc_smw.smw_name = device_xname(self); 602 sc->sc_smw.smw_cookie = sc; 603 sc->sc_smw.smw_setmode = tcotimer_setmode; 604 sc->sc_smw.smw_tickle = tcotimer_tickle; 605 if (sc->sc_has_rcba) 606 period = LPCIB_TCOTIMER2_MAX_TICK; 607 else 608 period = LPCIB_TCOTIMER_MAX_TICK; 609 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 610 611 if (sysmon_wdog_register(&sc->sc_smw)) { 612 aprint_error_dev(self, "unable to register TCO timer" 613 "as a sysmon watchdog device.\n"); 614 return; 615 } 616 617 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 618 } 619 620 static int 621 tcotimer_unconfigure(device_t self, int flags) 622 { 623 struct lpcib_softc *sc = device_private(self); 624 int rc; 625 626 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 627 if (rc == ERESTART) 628 rc = EINTR; 629 return rc; 630 } 631 632 /* Explicitly stop the TCO timer. */ 633 tcotimer_stop(sc); 634 635 /* XXX Set No Reboot? */ 636 637 return 0; 638 } 639 640 641 /* 642 * Sysmon watchdog callbacks. 643 */ 644 static int 645 tcotimer_setmode(struct sysmon_wdog *smw) 646 { 647 struct lpcib_softc *sc = smw->smw_cookie; 648 unsigned int period; 649 uint16_t ich6period = 0; 650 uint8_t ich5period = 0; 651 652 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 653 /* Stop the TCO timer. */ 654 tcotimer_stop(sc); 655 } else { 656 /* 657 * ICH6 or newer are limited to 2s min and 613s max. 658 * ICH5 or older are limited to 4s min and 39s max. 659 */ 660 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 661 if (sc->sc_has_rcba) { 662 if (period < LPCIB_TCOTIMER2_MIN_TICK || 663 period > LPCIB_TCOTIMER2_MAX_TICK) 664 return EINVAL; 665 } else { 666 if (period < LPCIB_TCOTIMER_MIN_TICK || 667 period > LPCIB_TCOTIMER_MAX_TICK) 668 return EINVAL; 669 } 670 671 /* Stop the TCO timer, */ 672 tcotimer_stop(sc); 673 674 /* set the timeout, */ 675 if (sc->sc_has_rcba) { 676 /* ICH6 or newer */ 677 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 678 LPCIB_TCO_TMR2); 679 ich6period &= 0xfc00; 680 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 681 LPCIB_TCO_TMR2, ich6period | period); 682 } else { 683 /* ICH5 or older */ 684 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 685 LPCIB_TCO_TMR); 686 ich5period &= 0xc0; 687 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 688 LPCIB_TCO_TMR, ich5period | period); 689 } 690 691 /* and start/reload the timer. */ 692 tcotimer_start(sc); 693 tcotimer_tickle(smw); 694 } 695 696 return 0; 697 } 698 699 static int 700 tcotimer_tickle(struct sysmon_wdog *smw) 701 { 702 struct lpcib_softc *sc = smw->smw_cookie; 703 704 /* any value is allowed */ 705 if (sc->sc_has_rcba) 706 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 707 else 708 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 709 710 return 0; 711 } 712 713 static void 714 tcotimer_stop(struct lpcib_softc *sc) 715 { 716 uint16_t ioreg; 717 718 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 719 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 720 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 721 } 722 723 static void 724 tcotimer_start(struct lpcib_softc *sc) 725 { 726 uint16_t ioreg; 727 728 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 729 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 730 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 731 } 732 733 static void 734 tcotimer_status_reset(struct lpcib_softc *sc) 735 { 736 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 737 LPCIB_TCO1_STS_TIMEOUT); 738 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 739 LPCIB_TCO2_STS_BOOT_STS); 740 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 741 LPCIB_TCO2_STS_SECONDS_TO_STS); 742 } 743 744 /* 745 * Clear the No Reboot (NR) bit, this enables reboots when the timer 746 * reaches the timeout for the second time. 747 */ 748 static int 749 tcotimer_disable_noreboot(device_t self) 750 { 751 struct lpcib_softc *sc = device_private(self); 752 753 if (sc->sc_has_rcba) { 754 uint32_t status; 755 756 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 757 LPCIB_GCS_OFFSET); 758 status &= ~LPCIB_GCS_NO_REBOOT; 759 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 760 LPCIB_GCS_OFFSET, status); 761 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 762 LPCIB_GCS_OFFSET); 763 if (status & LPCIB_GCS_NO_REBOOT) 764 goto error; 765 } else { 766 pcireg_t pcireg; 767 768 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 769 LPCIB_PCI_GEN_STA); 770 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 771 /* TCO timeout reset is disabled; try to enable it */ 772 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 773 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 774 LPCIB_PCI_GEN_STA, pcireg); 775 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 776 goto error; 777 } 778 } 779 780 return 0; 781 error: 782 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 783 "hope SMBIOS properly handles it.\n"); 784 return EINVAL; 785 } 786 787 788 /* 789 * Intel ICH SpeedStep support. 790 */ 791 #define SS_READ(sc, reg) \ 792 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 793 #define SS_WRITE(sc, reg, val) \ 794 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 795 796 /* 797 * Linux driver says that SpeedStep on older chipsets cause 798 * lockups on Dell Inspiron 8000 and 8100. 799 * It should also not be enabled on systems with the 82855GM 800 * Hub, which typically have an EST-enabled CPU. 801 */ 802 static int 803 speedstep_bad_hb_check(const struct pci_attach_args *pa) 804 { 805 806 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 807 PCI_REVISION(pa->pa_class) < 5) 808 return 1; 809 810 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 811 return 1; 812 813 return 0; 814 } 815 816 static void 817 speedstep_configure(device_t self) 818 { 819 struct lpcib_softc *sc = device_private(self); 820 const struct sysctlnode *node, *ssnode; 821 int rv; 822 823 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 824 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 825 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 826 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 827 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 828 pcireg_t pmcon; 829 830 /* Enable SpeedStep if it isn't already enabled. */ 831 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 832 LPCIB_PCI_GEN_PMCON_1); 833 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 834 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 835 LPCIB_PCI_GEN_PMCON_1, 836 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 837 838 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 839 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 840 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 841 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 842 goto err; 843 844 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 845 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 846 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 847 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 848 CTL_EOL)) != 0) 849 goto err; 850 851 /* XXX save the sc for IO tag/handle */ 852 speedstep_cookie = sc; 853 aprint_verbose_dev(self, "SpeedStep enabled\n"); 854 } 855 856 return; 857 858 err: 859 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 860 } 861 862 static void 863 speedstep_unconfigure(device_t self) 864 { 865 struct lpcib_softc *sc = device_private(self); 866 867 sysctl_teardown(&sc->sc_log); 868 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 869 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 870 871 speedstep_cookie = NULL; 872 } 873 874 /* 875 * get/set the SpeedStep state: 0 == low power, 1 == high power. 876 */ 877 static int 878 speedstep_sysctl_helper(SYSCTLFN_ARGS) 879 { 880 struct sysctlnode node; 881 struct lpcib_softc *sc = speedstep_cookie; 882 uint8_t state, state2; 883 int ostate, nstate, s, error = 0; 884 885 /* 886 * We do the dance with spl's to avoid being at high ipl during 887 * sysctl_lookup() which can both copyin and copyout. 888 */ 889 s = splserial(); 890 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 891 splx(s); 892 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 893 ostate = 1; 894 else 895 ostate = 0; 896 nstate = ostate; 897 898 node = *rnode; 899 node.sysctl_data = &nstate; 900 901 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 902 if (error || newp == NULL) 903 goto out; 904 905 /* Only two states are available */ 906 if (nstate != 0 && nstate != 1) { 907 error = EINVAL; 908 goto out; 909 } 910 911 s = splserial(); 912 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 913 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 914 ostate = 1; 915 else 916 ostate = 0; 917 918 if (ostate != nstate) { 919 uint8_t cntl; 920 921 if (nstate == 0) 922 state2 |= LPCIB_PM_SS_STATE_LOW; 923 else 924 state2 &= ~LPCIB_PM_SS_STATE_LOW; 925 926 /* 927 * Must disable bus master arbitration during the change. 928 */ 929 cntl = SS_READ(sc, LPCIB_PM_CTRL); 930 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 931 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 932 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 933 } 934 splx(s); 935 out: 936 return error; 937 } 938 939 static void 940 lpcib_hpet_configure(device_t self) 941 { 942 struct lpcib_softc *sc = device_private(self); 943 struct lpcib_hpet_attach_args arg; 944 uint32_t hpet_reg, val; 945 946 if (sc->sc_has_ich5_hpet) { 947 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 948 LPCIB_PCI_GEN_CNTL); 949 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 950 case LPCIB_ICH5_HPTC_0000: 951 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 952 break; 953 case LPCIB_ICH5_HPTC_1000: 954 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 955 break; 956 case LPCIB_ICH5_HPTC_2000: 957 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 958 break; 959 case LPCIB_ICH5_HPTC_3000: 960 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 961 break; 962 default: 963 return; 964 } 965 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 966 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 967 LPCIB_PCI_GEN_CNTL, val); 968 } else if (sc->sc_has_rcba) { 969 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 970 LPCIB_RCBA_HPTC); 971 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 972 case LPCIB_RCBA_HPTC_0000: 973 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 974 break; 975 case LPCIB_RCBA_HPTC_1000: 976 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 977 break; 978 case LPCIB_RCBA_HPTC_2000: 979 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 980 break; 981 case LPCIB_RCBA_HPTC_3000: 982 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 983 break; 984 default: 985 return; 986 } 987 val |= LPCIB_RCBA_HPTC_EN; 988 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 989 val); 990 } else { 991 /* No HPET here */ 992 return; 993 } 994 995 arg.hpet_mem_t = sc->sc_pa.pa_memt; 996 arg.hpet_reg = hpet_reg; 997 998 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 999 } 1000 1001 static int 1002 lpcib_hpet_unconfigure(device_t self, int flags) 1003 { 1004 struct lpcib_softc *sc = device_private(self); 1005 int rc; 1006 1007 if (sc->sc_hpetbus != NULL && 1008 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1009 return rc; 1010 1011 return 0; 1012 } 1013 1014 #if NGPIO > 0 1015 static void 1016 lpcib_gpio_configure(device_t self) 1017 { 1018 struct lpcib_softc *sc = device_private(self); 1019 struct gpiobus_attach_args gba; 1020 pcireg_t gpio_cntl; 1021 uint32_t use, io, bit; 1022 int pin, shift, base_reg, cntl_reg, reg; 1023 1024 /* this implies ICH >= 6, and thus different mapreg */ 1025 if (sc->sc_has_rcba) { 1026 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1027 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1028 } else { 1029 base_reg = LPCIB_PCI_GPIO_BASE; 1030 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1031 } 1032 1033 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1034 cntl_reg); 1035 1036 /* Is GPIO enabled? */ 1037 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1038 return; 1039 1040 if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1041 &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1042 NULL, &sc->sc_gpio_ios)) { 1043 aprint_error_dev(self, "can't map general purpose i/o space\n"); 1044 return; 1045 } 1046 1047 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1048 1049 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1050 sc->sc_gpio_pins[pin].pin_num = pin; 1051 1052 /* Read initial state */ 1053 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1054 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1055 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1056 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1057 shift = pin % 32; 1058 bit = __BIT(shift); 1059 1060 if ((use & bit) != 0) { 1061 sc->sc_gpio_pins[pin].pin_caps = 1062 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1063 if (pin < 32) 1064 sc->sc_gpio_pins[pin].pin_caps |= 1065 GPIO_PIN_PULSATE; 1066 if ((io & bit) != 0) 1067 sc->sc_gpio_pins[pin].pin_flags = 1068 GPIO_PIN_INPUT; 1069 else 1070 sc->sc_gpio_pins[pin].pin_flags = 1071 GPIO_PIN_OUTPUT; 1072 } else 1073 sc->sc_gpio_pins[pin].pin_caps = 0; 1074 1075 if (lpcib_gpio_pin_read(sc, pin) == 0) 1076 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1077 else 1078 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1079 1080 } 1081 1082 /* Create controller tag */ 1083 sc->sc_gpio_gc.gp_cookie = sc; 1084 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1085 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1086 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1087 1088 memset(&gba, 0, sizeof(gba)); 1089 1090 gba.gba_gc = &sc->sc_gpio_gc; 1091 gba.gba_pins = sc->sc_gpio_pins; 1092 gba.gba_npins = LPCIB_GPIO_NPINS; 1093 1094 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1095 } 1096 1097 static int 1098 lpcib_gpio_unconfigure(device_t self, int flags) 1099 { 1100 struct lpcib_softc *sc = device_private(self); 1101 int rc; 1102 1103 if (sc->sc_gpiobus != NULL && 1104 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1105 return rc; 1106 1107 mutex_destroy(&sc->sc_gpio_mtx); 1108 1109 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1110 1111 return 0; 1112 } 1113 1114 static int 1115 lpcib_gpio_pin_read(void *arg, int pin) 1116 { 1117 struct lpcib_softc *sc = arg; 1118 uint32_t data; 1119 int reg, shift; 1120 1121 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1122 shift = pin % 32; 1123 1124 mutex_enter(&sc->sc_gpio_mtx); 1125 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1126 mutex_exit(&sc->sc_gpio_mtx); 1127 1128 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1129 } 1130 1131 static void 1132 lpcib_gpio_pin_write(void *arg, int pin, int value) 1133 { 1134 struct lpcib_softc *sc = arg; 1135 uint32_t data; 1136 int reg, shift; 1137 1138 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1139 shift = pin % 32; 1140 1141 mutex_enter(&sc->sc_gpio_mtx); 1142 1143 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1144 1145 if(value) 1146 data |= __BIT(shift); 1147 else 1148 data &= ~__BIT(shift); 1149 1150 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1151 1152 mutex_exit(&sc->sc_gpio_mtx); 1153 } 1154 1155 static void 1156 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1157 { 1158 struct lpcib_softc *sc = arg; 1159 uint32_t data; 1160 int reg, shift; 1161 1162 shift = pin % 32; 1163 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1164 1165 mutex_enter(&sc->sc_gpio_mtx); 1166 1167 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1168 1169 if (flags & GPIO_PIN_OUTPUT) 1170 data &= ~__BIT(shift); 1171 1172 if (flags & GPIO_PIN_INPUT) 1173 data |= __BIT(shift); 1174 1175 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1176 1177 1178 if (pin < 32) { 1179 reg = LPCIB_GPIO_GPO_BLINK; 1180 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1181 1182 if (flags & GPIO_PIN_PULSATE) 1183 data |= __BIT(shift); 1184 else 1185 data &= ~__BIT(shift); 1186 1187 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1188 } 1189 1190 mutex_exit(&sc->sc_gpio_mtx); 1191 } 1192 #endif 1193 1194 #if NFWHRNG > 0 1195 static void 1196 lpcib_fwh_configure(device_t self) 1197 { 1198 struct lpcib_softc *sc; 1199 pcireg_t pr; 1200 1201 sc = device_private(self); 1202 1203 if (sc->sc_has_rcba) { 1204 /* 1205 * Very unlikely to find a 82802 on a ICH6 or newer. 1206 * Also the write enable register moved at that point. 1207 */ 1208 return; 1209 } else { 1210 /* Enable FWH write to identify FWH. */ 1211 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1212 LPCIB_PCI_BIOS_CNTL); 1213 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1214 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1215 } 1216 1217 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1218 1219 /* restore previous write enable setting */ 1220 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1221 LPCIB_PCI_BIOS_CNTL, pr); 1222 } 1223 1224 static int 1225 lpcib_fwh_unconfigure(device_t self, int flags) 1226 { 1227 struct lpcib_softc *sc = device_private(self); 1228 int rc; 1229 1230 if (sc->sc_fwhbus != NULL && 1231 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1232 return rc; 1233 1234 return 0; 1235 } 1236 #endif 1237
Indexes created Tue Sep 30 11:09:46 GMT 2025