ichlpcib.c revision 1.38
1 /* $NetBSD: ichlpcib.c,v 1.38 2013/01/12 20:33:59 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.38 2013/01/12 20:33:59 riastradh Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 251 252 { 0, 0, 0, 0 }, 253 }; 254 255 /* 256 * Autoconf callbacks. 257 */ 258 static int 259 lpcibmatch(device_t parent, cfdata_t match, void *aux) 260 { 261 struct pci_attach_args *pa = aux; 262 struct lpcib_device *lpcib_dev; 263 264 /* We are ISA bridge, of course */ 265 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 266 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 267 return 0; 268 269 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 270 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 271 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 272 return 10; 273 } 274 275 return 0; 276 } 277 278 static void 279 lpcibattach(device_t parent, device_t self, void *aux) 280 { 281 struct pci_attach_args *pa = aux; 282 struct lpcib_softc *sc = device_private(self); 283 struct lpcib_device *lpcib_dev; 284 285 sc->sc_pa = *pa; 286 287 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 288 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 289 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 290 continue; 291 sc->sc_has_rcba = lpcib_dev->has_rcba; 292 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 293 break; 294 } 295 296 pcibattach(parent, self, aux); 297 298 /* 299 * Part of our I/O registers are used as ACPI PM regs. 300 * Since our ACPI subsystem accesses the I/O space directly so far, 301 * we do not have to bother bus_space I/O map confliction. 302 */ 303 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 304 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 305 aprint_error_dev(self, "can't map power management i/o space"); 306 return; 307 } 308 309 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 310 LPCIB_PCI_GEN_PMCON_1); 311 312 /* For ICH6 and later, always enable RCBA */ 313 if (sc->sc_has_rcba) { 314 pcireg_t rcba; 315 316 sc->sc_rcbat = sc->sc_pa.pa_memt; 317 318 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 319 LPCIB_RCBA); 320 if ((rcba & LPCIB_RCBA_EN) == 0) { 321 aprint_error_dev(self, "RCBA is not enabled"); 322 return; 323 } 324 rcba &= ~LPCIB_RCBA_EN; 325 326 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 327 &sc->sc_rcbah)) { 328 aprint_error_dev(self, "RCBA could not be mapped"); 329 return; 330 } 331 } 332 333 /* Set up the power management timer. */ 334 pmtimer_configure(self); 335 336 /* Set up the TCO (watchdog). */ 337 tcotimer_configure(self); 338 339 /* Set up SpeedStep. */ 340 speedstep_configure(self); 341 342 /* Set up HPET. */ 343 lpcib_hpet_configure(self); 344 345 #if NGPIO > 0 346 /* Set up GPIO */ 347 lpcib_gpio_configure(self); 348 #endif 349 350 #if NFWHRNG > 0 351 lpcib_fwh_configure(self); 352 #endif 353 354 /* Install power handler */ 355 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 356 lpcib_shutdown)) 357 aprint_error_dev(self, "couldn't establish power handler\n"); 358 } 359 360 static void 361 lpcibchilddet(device_t self, device_t child) 362 { 363 struct lpcib_softc *sc = device_private(self); 364 uint32_t val; 365 366 #if NFWHRNG > 0 367 if (sc->sc_fwhbus == child) { 368 sc->sc_fwhbus = NULL; 369 return; 370 } 371 #endif 372 #if NGPIO > 0 373 if (sc->sc_gpiobus == child) { 374 sc->sc_gpiobus = NULL; 375 return; 376 } 377 #endif 378 if (sc->sc_hpetbus != child) { 379 pcibchilddet(self, child); 380 return; 381 } 382 sc->sc_hpetbus = NULL; 383 if (sc->sc_has_ich5_hpet) { 384 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 385 LPCIB_PCI_GEN_CNTL); 386 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 387 case LPCIB_ICH5_HPTC_0000: 388 case LPCIB_ICH5_HPTC_1000: 389 case LPCIB_ICH5_HPTC_2000: 390 case LPCIB_ICH5_HPTC_3000: 391 break; 392 default: 393 return; 394 } 395 val &= ~LPCIB_ICH5_HPTC_EN; 396 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 397 LPCIB_PCI_GEN_CNTL, val); 398 } else if (sc->sc_has_rcba) { 399 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 400 LPCIB_RCBA_HPTC); 401 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 402 case LPCIB_RCBA_HPTC_0000: 403 case LPCIB_RCBA_HPTC_1000: 404 case LPCIB_RCBA_HPTC_2000: 405 case LPCIB_RCBA_HPTC_3000: 406 break; 407 default: 408 return; 409 } 410 val &= ~LPCIB_RCBA_HPTC_EN; 411 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 412 val); 413 } 414 } 415 416 static int 417 lpcibrescan(device_t self, const char *ifattr, const int *locators) 418 { 419 struct lpcib_softc *sc = device_private(self); 420 421 #if NFWHRNG > 0 422 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 423 lpcib_fwh_configure(self); 424 #endif 425 426 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 427 lpcib_hpet_configure(self); 428 429 #if NGPIO > 0 430 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 431 lpcib_gpio_configure(self); 432 #endif 433 434 return pcibrescan(self, ifattr, locators); 435 } 436 437 static int 438 lpcibdetach(device_t self, int flags) 439 { 440 struct lpcib_softc *sc = device_private(self); 441 int rc; 442 443 pmf_device_deregister(self); 444 445 #if NFWHRNG > 0 446 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 447 return rc; 448 #endif 449 450 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 451 return rc; 452 453 #if NGPIO > 0 454 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 455 return rc; 456 #endif 457 458 /* Set up SpeedStep. */ 459 speedstep_unconfigure(self); 460 461 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 462 return rc; 463 464 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 465 return rc; 466 467 if (sc->sc_has_rcba) 468 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 469 470 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 471 472 return pcibdetach(self, flags); 473 } 474 475 static bool 476 lpcib_shutdown(device_t dv, int howto) 477 { 478 struct lpcib_softc *sc = device_private(dv); 479 480 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 481 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 482 483 return true; 484 } 485 486 static bool 487 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 488 { 489 struct lpcib_softc *sc = device_private(dv); 490 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 491 pcitag_t tag = sc->sc_pcib.sc_tag; 492 493 /* capture PIRQ routing control registers */ 494 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 495 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 496 497 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 498 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 499 500 if (sc->sc_has_rcba) { 501 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 502 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 503 LPCIB_RCBA_HPTC); 504 } else if (sc->sc_has_ich5_hpet) { 505 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 506 } 507 508 return true; 509 } 510 511 static bool 512 lpcib_resume(device_t dv, const pmf_qual_t *qual) 513 { 514 struct lpcib_softc *sc = device_private(dv); 515 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 516 pcitag_t tag = sc->sc_pcib.sc_tag; 517 518 /* restore PIRQ routing control registers */ 519 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 520 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 521 522 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 523 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 524 525 if (sc->sc_has_rcba) { 526 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 527 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 528 sc->sc_hpet_reg); 529 } else if (sc->sc_has_ich5_hpet) { 530 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 531 } 532 533 return true; 534 } 535 536 /* 537 * Initialize the power management timer. 538 */ 539 static void 540 pmtimer_configure(device_t self) 541 { 542 struct lpcib_softc *sc = device_private(self); 543 pcireg_t control; 544 545 /* 546 * Check if power management I/O space is enabled and enable the ACPI_EN 547 * bit if it's disabled. 548 */ 549 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 550 LPCIB_PCI_ACPI_CNTL); 551 sc->sc_acpi_cntl = control; 552 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 553 control |= LPCIB_PCI_ACPI_CNTL_EN; 554 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 555 LPCIB_PCI_ACPI_CNTL, control); 556 } 557 558 /* Attach our PM timer with the generic acpipmtimer function */ 559 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 560 LPCIB_PM1_TMR, 0); 561 } 562 563 static int 564 pmtimer_unconfigure(device_t self, int flags) 565 { 566 struct lpcib_softc *sc = device_private(self); 567 int rc; 568 569 if (sc->sc_pmtimer != NULL && 570 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 571 return rc; 572 573 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 574 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 575 576 return 0; 577 } 578 579 /* 580 * Initialize the watchdog timer. 581 */ 582 static void 583 tcotimer_configure(device_t self) 584 { 585 struct lpcib_softc *sc = device_private(self); 586 uint32_t ioreg; 587 unsigned int period; 588 589 /* Explicitly stop the TCO timer. */ 590 tcotimer_stop(sc); 591 592 /* 593 * Enable TCO timeout SMI only if the hardware reset does not 594 * work. We don't know what the SMBIOS does. 595 */ 596 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 597 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 598 599 /* 600 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 601 * in the SMI_EN register is the last chance. 602 */ 603 if (tcotimer_disable_noreboot(self)) { 604 ioreg |= LPCIB_SMI_EN_TCO_EN; 605 } 606 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 607 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 608 } 609 610 /* Reset the watchdog status registers. */ 611 tcotimer_status_reset(sc); 612 613 /* 614 * Register the driver with the sysmon watchdog framework. 615 */ 616 sc->sc_smw.smw_name = device_xname(self); 617 sc->sc_smw.smw_cookie = sc; 618 sc->sc_smw.smw_setmode = tcotimer_setmode; 619 sc->sc_smw.smw_tickle = tcotimer_tickle; 620 if (sc->sc_has_rcba) 621 period = LPCIB_TCOTIMER2_MAX_TICK; 622 else 623 period = LPCIB_TCOTIMER_MAX_TICK; 624 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 625 626 if (sysmon_wdog_register(&sc->sc_smw)) { 627 aprint_error_dev(self, "unable to register TCO timer" 628 "as a sysmon watchdog device.\n"); 629 return; 630 } 631 632 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 633 } 634 635 static int 636 tcotimer_unconfigure(device_t self, int flags) 637 { 638 struct lpcib_softc *sc = device_private(self); 639 int rc; 640 641 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 642 if (rc == ERESTART) 643 rc = EINTR; 644 return rc; 645 } 646 647 /* Explicitly stop the TCO timer. */ 648 tcotimer_stop(sc); 649 650 /* XXX Set No Reboot? */ 651 652 return 0; 653 } 654 655 656 /* 657 * Sysmon watchdog callbacks. 658 */ 659 static int 660 tcotimer_setmode(struct sysmon_wdog *smw) 661 { 662 struct lpcib_softc *sc = smw->smw_cookie; 663 unsigned int period; 664 uint16_t ich6period = 0; 665 uint8_t ich5period = 0; 666 667 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 668 /* Stop the TCO timer. */ 669 tcotimer_stop(sc); 670 } else { 671 /* 672 * ICH6 or newer are limited to 2s min and 613s max. 673 * ICH5 or older are limited to 4s min and 39s max. 674 */ 675 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 676 if (sc->sc_has_rcba) { 677 if (period < LPCIB_TCOTIMER2_MIN_TICK || 678 period > LPCIB_TCOTIMER2_MAX_TICK) 679 return EINVAL; 680 } else { 681 if (period < LPCIB_TCOTIMER_MIN_TICK || 682 period > LPCIB_TCOTIMER_MAX_TICK) 683 return EINVAL; 684 } 685 686 /* Stop the TCO timer, */ 687 tcotimer_stop(sc); 688 689 /* set the timeout, */ 690 if (sc->sc_has_rcba) { 691 /* ICH6 or newer */ 692 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 693 LPCIB_TCO_TMR2); 694 ich6period &= 0xfc00; 695 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 696 LPCIB_TCO_TMR2, ich6period | period); 697 } else { 698 /* ICH5 or older */ 699 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 700 LPCIB_TCO_TMR); 701 ich5period &= 0xc0; 702 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 703 LPCIB_TCO_TMR, ich5period | period); 704 } 705 706 /* and start/reload the timer. */ 707 tcotimer_start(sc); 708 tcotimer_tickle(smw); 709 } 710 711 return 0; 712 } 713 714 static int 715 tcotimer_tickle(struct sysmon_wdog *smw) 716 { 717 struct lpcib_softc *sc = smw->smw_cookie; 718 719 /* any value is allowed */ 720 if (sc->sc_has_rcba) 721 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 722 else 723 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 724 725 return 0; 726 } 727 728 static void 729 tcotimer_stop(struct lpcib_softc *sc) 730 { 731 uint16_t ioreg; 732 733 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 734 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 735 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 736 } 737 738 static void 739 tcotimer_start(struct lpcib_softc *sc) 740 { 741 uint16_t ioreg; 742 743 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 744 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 745 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 746 } 747 748 static void 749 tcotimer_status_reset(struct lpcib_softc *sc) 750 { 751 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 752 LPCIB_TCO1_STS_TIMEOUT); 753 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 754 LPCIB_TCO2_STS_BOOT_STS); 755 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 756 LPCIB_TCO2_STS_SECONDS_TO_STS); 757 } 758 759 /* 760 * Clear the No Reboot (NR) bit, this enables reboots when the timer 761 * reaches the timeout for the second time. 762 */ 763 static int 764 tcotimer_disable_noreboot(device_t self) 765 { 766 struct lpcib_softc *sc = device_private(self); 767 768 if (sc->sc_has_rcba) { 769 uint32_t status; 770 771 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 772 LPCIB_GCS_OFFSET); 773 status &= ~LPCIB_GCS_NO_REBOOT; 774 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 775 LPCIB_GCS_OFFSET, status); 776 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 777 LPCIB_GCS_OFFSET); 778 if (status & LPCIB_GCS_NO_REBOOT) 779 goto error; 780 } else { 781 pcireg_t pcireg; 782 783 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 784 LPCIB_PCI_GEN_STA); 785 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 786 /* TCO timeout reset is disabled; try to enable it */ 787 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 788 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 789 LPCIB_PCI_GEN_STA, pcireg); 790 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 791 goto error; 792 } 793 } 794 795 return 0; 796 error: 797 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 798 "hope SMBIOS properly handles it.\n"); 799 return EINVAL; 800 } 801 802 803 /* 804 * Intel ICH SpeedStep support. 805 */ 806 #define SS_READ(sc, reg) \ 807 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 808 #define SS_WRITE(sc, reg, val) \ 809 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 810 811 /* 812 * Linux driver says that SpeedStep on older chipsets cause 813 * lockups on Dell Inspiron 8000 and 8100. 814 * It should also not be enabled on systems with the 82855GM 815 * Hub, which typically have an EST-enabled CPU. 816 */ 817 static int 818 speedstep_bad_hb_check(const struct pci_attach_args *pa) 819 { 820 821 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 822 PCI_REVISION(pa->pa_class) < 5) 823 return 1; 824 825 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 826 return 1; 827 828 return 0; 829 } 830 831 static void 832 speedstep_configure(device_t self) 833 { 834 struct lpcib_softc *sc = device_private(self); 835 const struct sysctlnode *node, *ssnode; 836 int rv; 837 838 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 839 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 840 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 841 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 842 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 843 pcireg_t pmcon; 844 845 /* Enable SpeedStep if it isn't already enabled. */ 846 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 847 LPCIB_PCI_GEN_PMCON_1); 848 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 849 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 850 LPCIB_PCI_GEN_PMCON_1, 851 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 852 853 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 854 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 855 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 856 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 857 goto err; 858 859 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 860 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 861 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 862 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 863 CTL_EOL)) != 0) 864 goto err; 865 866 /* XXX save the sc for IO tag/handle */ 867 speedstep_cookie = sc; 868 aprint_verbose_dev(self, "SpeedStep enabled\n"); 869 } 870 871 return; 872 873 err: 874 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 875 } 876 877 static void 878 speedstep_unconfigure(device_t self) 879 { 880 struct lpcib_softc *sc = device_private(self); 881 882 sysctl_teardown(&sc->sc_log); 883 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 884 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 885 886 speedstep_cookie = NULL; 887 } 888 889 /* 890 * get/set the SpeedStep state: 0 == low power, 1 == high power. 891 */ 892 static int 893 speedstep_sysctl_helper(SYSCTLFN_ARGS) 894 { 895 struct sysctlnode node; 896 struct lpcib_softc *sc = speedstep_cookie; 897 uint8_t state, state2; 898 int ostate, nstate, s, error = 0; 899 900 /* 901 * We do the dance with spl's to avoid being at high ipl during 902 * sysctl_lookup() which can both copyin and copyout. 903 */ 904 s = splserial(); 905 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 906 splx(s); 907 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 908 ostate = 1; 909 else 910 ostate = 0; 911 nstate = ostate; 912 913 node = *rnode; 914 node.sysctl_data = &nstate; 915 916 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 917 if (error || newp == NULL) 918 goto out; 919 920 /* Only two states are available */ 921 if (nstate != 0 && nstate != 1) { 922 error = EINVAL; 923 goto out; 924 } 925 926 s = splserial(); 927 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 928 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 929 ostate = 1; 930 else 931 ostate = 0; 932 933 if (ostate != nstate) { 934 uint8_t cntl; 935 936 if (nstate == 0) 937 state2 |= LPCIB_PM_SS_STATE_LOW; 938 else 939 state2 &= ~LPCIB_PM_SS_STATE_LOW; 940 941 /* 942 * Must disable bus master arbitration during the change. 943 */ 944 cntl = SS_READ(sc, LPCIB_PM_CTRL); 945 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 946 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 947 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 948 } 949 splx(s); 950 out: 951 return error; 952 } 953 954 static void 955 lpcib_hpet_configure(device_t self) 956 { 957 struct lpcib_softc *sc = device_private(self); 958 struct lpcib_hpet_attach_args arg; 959 uint32_t hpet_reg, val; 960 961 if (sc->sc_has_ich5_hpet) { 962 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 963 LPCIB_PCI_GEN_CNTL); 964 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 965 case LPCIB_ICH5_HPTC_0000: 966 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 967 break; 968 case LPCIB_ICH5_HPTC_1000: 969 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 970 break; 971 case LPCIB_ICH5_HPTC_2000: 972 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 973 break; 974 case LPCIB_ICH5_HPTC_3000: 975 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 976 break; 977 default: 978 return; 979 } 980 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 981 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 982 LPCIB_PCI_GEN_CNTL, val); 983 } else if (sc->sc_has_rcba) { 984 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 985 LPCIB_RCBA_HPTC); 986 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 987 case LPCIB_RCBA_HPTC_0000: 988 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 989 break; 990 case LPCIB_RCBA_HPTC_1000: 991 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 992 break; 993 case LPCIB_RCBA_HPTC_2000: 994 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 995 break; 996 case LPCIB_RCBA_HPTC_3000: 997 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 998 break; 999 default: 1000 return; 1001 } 1002 val |= LPCIB_RCBA_HPTC_EN; 1003 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1004 val); 1005 } else { 1006 /* No HPET here */ 1007 return; 1008 } 1009 1010 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1011 arg.hpet_reg = hpet_reg; 1012 1013 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1014 } 1015 1016 static int 1017 lpcib_hpet_unconfigure(device_t self, int flags) 1018 { 1019 struct lpcib_softc *sc = device_private(self); 1020 int rc; 1021 1022 if (sc->sc_hpetbus != NULL && 1023 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1024 return rc; 1025 1026 return 0; 1027 } 1028 1029 #if NGPIO > 0 1030 static void 1031 lpcib_gpio_configure(device_t self) 1032 { 1033 struct lpcib_softc *sc = device_private(self); 1034 struct gpiobus_attach_args gba; 1035 pcireg_t gpio_cntl; 1036 uint32_t use, io, bit; 1037 int pin, shift, base_reg, cntl_reg, reg; 1038 1039 /* this implies ICH >= 6, and thus different mapreg */ 1040 if (sc->sc_has_rcba) { 1041 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1042 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1043 } else { 1044 base_reg = LPCIB_PCI_GPIO_BASE; 1045 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1046 } 1047 1048 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1049 cntl_reg); 1050 1051 /* Is GPIO enabled? */ 1052 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1053 return; 1054 1055 if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1056 &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1057 NULL, &sc->sc_gpio_ios)) { 1058 aprint_error_dev(self, "can't map general purpose i/o space\n"); 1059 return; 1060 } 1061 1062 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1063 1064 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1065 sc->sc_gpio_pins[pin].pin_num = pin; 1066 1067 /* Read initial state */ 1068 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1069 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1070 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1071 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1072 shift = pin % 32; 1073 bit = __BIT(shift); 1074 1075 if ((use & bit) != 0) { 1076 sc->sc_gpio_pins[pin].pin_caps = 1077 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1078 if (pin < 32) 1079 sc->sc_gpio_pins[pin].pin_caps |= 1080 GPIO_PIN_PULSATE; 1081 if ((io & bit) != 0) 1082 sc->sc_gpio_pins[pin].pin_flags = 1083 GPIO_PIN_INPUT; 1084 else 1085 sc->sc_gpio_pins[pin].pin_flags = 1086 GPIO_PIN_OUTPUT; 1087 } else 1088 sc->sc_gpio_pins[pin].pin_caps = 0; 1089 1090 if (lpcib_gpio_pin_read(sc, pin) == 0) 1091 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1092 else 1093 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1094 1095 } 1096 1097 /* Create controller tag */ 1098 sc->sc_gpio_gc.gp_cookie = sc; 1099 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1100 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1101 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1102 1103 memset(&gba, 0, sizeof(gba)); 1104 1105 gba.gba_gc = &sc->sc_gpio_gc; 1106 gba.gba_pins = sc->sc_gpio_pins; 1107 gba.gba_npins = LPCIB_GPIO_NPINS; 1108 1109 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1110 } 1111 1112 static int 1113 lpcib_gpio_unconfigure(device_t self, int flags) 1114 { 1115 struct lpcib_softc *sc = device_private(self); 1116 int rc; 1117 1118 if (sc->sc_gpiobus != NULL && 1119 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1120 return rc; 1121 1122 mutex_destroy(&sc->sc_gpio_mtx); 1123 1124 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1125 1126 return 0; 1127 } 1128 1129 static int 1130 lpcib_gpio_pin_read(void *arg, int pin) 1131 { 1132 struct lpcib_softc *sc = arg; 1133 uint32_t data; 1134 int reg, shift; 1135 1136 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1137 shift = pin % 32; 1138 1139 mutex_enter(&sc->sc_gpio_mtx); 1140 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1141 mutex_exit(&sc->sc_gpio_mtx); 1142 1143 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1144 } 1145 1146 static void 1147 lpcib_gpio_pin_write(void *arg, int pin, int value) 1148 { 1149 struct lpcib_softc *sc = arg; 1150 uint32_t data; 1151 int reg, shift; 1152 1153 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1154 shift = pin % 32; 1155 1156 mutex_enter(&sc->sc_gpio_mtx); 1157 1158 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1159 1160 if(value) 1161 data |= __BIT(shift); 1162 else 1163 data &= ~__BIT(shift); 1164 1165 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1166 1167 mutex_exit(&sc->sc_gpio_mtx); 1168 } 1169 1170 static void 1171 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1172 { 1173 struct lpcib_softc *sc = arg; 1174 uint32_t data; 1175 int reg, shift; 1176 1177 shift = pin % 32; 1178 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1179 1180 mutex_enter(&sc->sc_gpio_mtx); 1181 1182 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1183 1184 if (flags & GPIO_PIN_OUTPUT) 1185 data &= ~__BIT(shift); 1186 1187 if (flags & GPIO_PIN_INPUT) 1188 data |= __BIT(shift); 1189 1190 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1191 1192 1193 if (pin < 32) { 1194 reg = LPCIB_GPIO_GPO_BLINK; 1195 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1196 1197 if (flags & GPIO_PIN_PULSATE) 1198 data |= __BIT(shift); 1199 else 1200 data &= ~__BIT(shift); 1201 1202 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1203 } 1204 1205 mutex_exit(&sc->sc_gpio_mtx); 1206 } 1207 #endif 1208 1209 #if NFWHRNG > 0 1210 static void 1211 lpcib_fwh_configure(device_t self) 1212 { 1213 struct lpcib_softc *sc; 1214 pcireg_t pr; 1215 1216 sc = device_private(self); 1217 1218 if (sc->sc_has_rcba) { 1219 /* 1220 * Very unlikely to find a 82802 on a ICH6 or newer. 1221 * Also the write enable register moved at that point. 1222 */ 1223 return; 1224 } else { 1225 /* Enable FWH write to identify FWH. */ 1226 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1227 LPCIB_PCI_BIOS_CNTL); 1228 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1229 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1230 } 1231 1232 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1233 1234 /* restore previous write enable setting */ 1235 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1236 LPCIB_PCI_BIOS_CNTL, pr); 1237 } 1238 1239 static int 1240 lpcib_fwh_unconfigure(device_t self, int flags) 1241 { 1242 struct lpcib_softc *sc = device_private(self); 1243 int rc; 1244 1245 if (sc->sc_fwhbus != NULL && 1246 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1247 return rc; 1248 1249 return 0; 1250 } 1251 #endif 1252
Indexes created Tue Sep 30 11:09:46 GMT 2025