ichlpcib.c revision 1.4.6.10
1 /* $NetBSD: ichlpcib.c,v 1.4.6.10 2007/09/05 21:04:54 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 41 * 42 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 43 * some power management and monitoring functions. 44 * Currently we support the watchdog timer, SpeedStep (on some systems) 45 * and the power management timer. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.4.6.10 2007/09/05 21:04:54 joerg Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/sysctl.h> 56 #include <sys/timetc.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/sysmon/sysmonvar.h> 64 65 #include <dev/ic/acpipmtimer.h> 66 #include <dev/ic/i82801lpcreg.h> 67 #include <dev/ic/hpetreg.h> 68 #include <dev/ic/hpetvar.h> 69 70 #include "hpet.h" 71 72 struct lpcib_softc { 73 /* Device object. */ 74 struct device sc_dev; 75 76 pci_chipset_tag_t sc_pc; 77 pcitag_t sc_pcitag; 78 struct pci_conf_state sc_pciconf; 79 80 struct pci_attach_args sc_pa; 81 int sc_has_rcba; 82 int sc_has_ich5_hpet; 83 84 /* RCBA */ 85 bus_space_tag_t sc_rcbat; 86 bus_space_handle_t sc_rcbah; 87 pcireg_t sc_rcba_reg; 88 89 /* Watchdog variables. */ 90 struct sysmon_wdog sc_smw; 91 bus_space_tag_t sc_iot; 92 bus_space_handle_t sc_ioh; 93 94 #if NHPET > 0 95 /* HPET variables. */ 96 uint32_t sc_hpet_reg; 97 #endif 98 99 /* Power management */ 100 pcireg_t sc_pirq[8]; 101 pcireg_t sc_pmcon; 102 pcireg_t sc_fwhsel2; 103 }; 104 105 static int lpcibmatch(struct device *, struct cfdata *, void *); 106 static void lpcibattach(struct device *, struct device *, void *); 107 static pnp_status_t lpcib_power(device_t, pnp_request_t, void *); 108 109 static void pmtimer_configure(struct lpcib_softc *); 110 111 static void tcotimer_configure(struct lpcib_softc *); 112 static int tcotimer_setmode(struct sysmon_wdog *); 113 static int tcotimer_tickle(struct sysmon_wdog *); 114 static void tcotimer_stop(struct lpcib_softc *); 115 static void tcotimer_start(struct lpcib_softc *); 116 static void tcotimer_status_reset(struct lpcib_softc *); 117 static int tcotimer_disable_noreboot(struct lpcib_softc *); 118 119 static void speedstep_configure(struct lpcib_softc *); 120 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 121 122 #if NHPET > 0 123 static void lpcib_hpet_configure(struct lpcib_softc *); 124 #endif 125 126 struct lpcib_softc *speedstep_cookie; /* XXX */ 127 128 /* Defined in arch/.../pci/pcib.c. */ 129 extern void pcibattach(struct device *, struct device *, void *); 130 131 CFATTACH_DECL(ichlpcib, sizeof(struct lpcib_softc), 132 lpcibmatch, lpcibattach, NULL, NULL); 133 134 static struct lpcib_device { 135 pcireg_t vendor, product; 136 int has_rcba; 137 int has_ich5_hpet; 138 } lpcib_devices[] = { 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 161 { 0, 0, 0, 0 }, 162 }; 163 164 /* 165 * Autoconf callbacks. 166 */ 167 static int 168 lpcibmatch(struct device *parent, struct cfdata *match, void *aux) 169 { 170 struct pci_attach_args *pa = aux; 171 struct lpcib_device *lpcib_dev; 172 173 /* We are ISA bridge, of course */ 174 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 175 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 176 return 0; 177 178 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 179 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 180 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 181 return 10; 182 } 183 184 return 0; 185 } 186 187 static void 188 lpcibattach(struct device *parent, struct device *self, void *aux) 189 { 190 struct pci_attach_args *pa = aux; 191 struct lpcib_softc *sc = device_private(self); 192 struct lpcib_device *lpcib_dev; 193 pnp_status_t status; 194 195 sc->sc_pc = pa->pa_pc; 196 sc->sc_pcitag = pa->pa_tag; 197 sc->sc_pa = *pa; 198 199 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 200 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 201 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 202 continue; 203 sc->sc_has_rcba = lpcib_dev->has_rcba; 204 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 205 break; 206 } 207 208 pcibattach(parent, self, aux); 209 210 /* 211 * Part of our I/O registers are used as ACPI PM regs. 212 * Since our ACPI subsystem accesses the I/O space directly so far, 213 * we do not have to bother bus_space I/O map confliction. 214 */ 215 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 216 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 217 aprint_error("%s: can't map power management i/o space", 218 sc->sc_dev.dv_xname); 219 return; 220 } 221 222 /* For ICH6 and later, always enable RCBA */ 223 if (sc->sc_has_rcba) { 224 pcireg_t rcba; 225 226 sc->sc_rcbat = sc->sc_pa.pa_memt; 227 228 rcba = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_RCBA); 229 if ((rcba & LPCIB_RCBA_EN) == 0) { 230 aprint_error("%s: RCBA is not enabled", 231 sc->sc_dev.dv_xname); 232 return; 233 } 234 rcba &= ~LPCIB_RCBA_EN; 235 236 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 237 &sc->sc_rcbah)) { 238 aprint_error("%s: RCBA could not be mapped", 239 sc->sc_dev.dv_xname); 240 return; 241 } 242 } 243 244 /* Set up the power management timer. */ 245 pmtimer_configure(sc); 246 247 /* Set up the TCO (watchdog). */ 248 tcotimer_configure(sc); 249 250 /* Set up SpeedStep. */ 251 speedstep_configure(sc); 252 253 #if NHPET > 0 254 /* Set up HPET. */ 255 lpcib_hpet_configure(sc); 256 #endif 257 258 /* Install power handler */ 259 status = pnp_register(self, lpcib_power); 260 if (status != PNP_STATUS_SUCCESS) 261 aprint_error("%s: couldn't establish power handler\n", 262 device_xname(self)); 263 } 264 265 static pnp_status_t 266 lpcib_power(device_t dv, pnp_request_t req, void *opaque) 267 { 268 struct lpcib_softc *sc; 269 pnp_state_t *state; 270 pnp_capabilities_t *caps; 271 pci_chipset_tag_t pc; 272 pcitag_t tag; 273 pcireg_t val; 274 int off; 275 276 sc = device_private(dv); 277 pc = sc->sc_pc; 278 tag = sc->sc_pcitag; 279 280 switch (req) { 281 case PNP_REQUEST_GET_CAPABILITIES: 282 caps = (pnp_capabilities_t *)opaque; 283 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &off, &val)) 284 caps->state = PNP_STATE_D0 | PNP_STATE_D3; 285 else 286 caps->state = pci_pnp_capabilities(val); 287 break; 288 case PNP_REQUEST_GET_STATE: 289 state = (pnp_state_t *)opaque; 290 if (pci_get_powerstate(pc, tag, &val) != 0) 291 *state = PNP_STATE_D0; 292 else 293 *state = pci_pnp_powerstate(val); 294 break; 295 case PNP_REQUEST_SET_STATE: 296 state = (pnp_state_t *)opaque; 297 298 switch (*state) { 299 case PNP_STATE_D3: 300 val = PCI_PMCSR_STATE_D3; 301 pci_conf_capture(pc, tag, &sc->sc_pciconf); 302 303 /* capture PIRQ routing control registers */ 304 sc->sc_pirq[0] = pci_conf_read(pc, tag, 305 LPCIB_PCI_PIRQA_ROUT); 306 sc->sc_pirq[1] = pci_conf_read(pc, tag, 307 LPCIB_PCI_PIRQB_ROUT); 308 sc->sc_pirq[2] = pci_conf_read(pc, tag, 309 LPCIB_PCI_PIRQC_ROUT); 310 sc->sc_pirq[3] = pci_conf_read(pc, tag, 311 LPCIB_PCI_PIRQD_ROUT); 312 sc->sc_pirq[4] = pci_conf_read(pc, tag, 313 LPCIB_PCI_PIRQE_ROUT); 314 sc->sc_pirq[5] = pci_conf_read(pc, tag, 315 LPCIB_PCI_PIRQF_ROUT); 316 sc->sc_pirq[6] = pci_conf_read(pc, tag, 317 LPCIB_PCI_PIRQG_ROUT); 318 sc->sc_pirq[7] = pci_conf_read(pc, tag, 319 LPCIB_PCI_PIRQH_ROUT); 320 321 sc->sc_pmcon = pci_conf_read(pc, tag, 322 LPCIB_PCI_GEN_PMCON_1); 323 sc->sc_fwhsel2 = pci_conf_read(pc, tag, 324 LPCIB_PCI_GEN_STA); 325 if (sc->sc_has_rcba) { 326 sc->sc_rcba_reg = pci_conf_read(pc, tag, 327 LPCIB_RCBA); 328 #if NHPET > 0 329 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, 330 sc->sc_rcbah, LPCIB_RCBA_HPTC); 331 #endif 332 } else if (sc->sc_has_ich5_hpet) { 333 #if NHPET > 0 334 sc->sc_hpet_reg = pci_conf_read(pc, tag, 335 LPCIB_PCI_GEN_CNTL); 336 #endif 337 } 338 339 break; 340 case PNP_STATE_D0: 341 val = PCI_PMCSR_STATE_D0; 342 343 break; 344 default: 345 return PNP_STATUS_UNSUPPORTED; 346 } 347 348 (void)pci_set_powerstate(pc, tag, val); 349 350 if (*state != PNP_STATE_D0) 351 break; 352 353 pci_conf_restore(pc, tag, &sc->sc_pciconf); 354 355 /* restore PIRQ routing control registers */ 356 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, 357 sc->sc_pirq[0]); 358 pci_conf_write(pc, tag, LPCIB_PCI_PIRQB_ROUT, 359 sc->sc_pirq[1]); 360 pci_conf_write(pc, tag, LPCIB_PCI_PIRQC_ROUT, 361 sc->sc_pirq[2]); 362 pci_conf_write(pc, tag, LPCIB_PCI_PIRQD_ROUT, 363 sc->sc_pirq[3]); 364 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, 365 sc->sc_pirq[4]); 366 pci_conf_write(pc, tag, LPCIB_PCI_PIRQF_ROUT, 367 sc->sc_pirq[5]); 368 pci_conf_write(pc, tag, LPCIB_PCI_PIRQG_ROUT, 369 sc->sc_pirq[6]); 370 pci_conf_write(pc, tag, LPCIB_PCI_PIRQH_ROUT, 371 sc->sc_pirq[7]); 372 373 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 374 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 375 if (sc->sc_has_rcba) { 376 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 377 #if NHPET > 0 378 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 379 LPCIB_RCBA_HPTC, sc->sc_hpet_reg); 380 #endif 381 } else if (sc->sc_has_ich5_hpet) { 382 #if NHPET > 0 383 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 384 #endif 385 } 386 387 388 break; 389 default: 390 return PNP_STATUS_UNSUPPORTED; 391 } 392 393 return PNP_STATUS_SUCCESS; 394 } 395 396 /* 397 * Initialize the power management timer. 398 */ 399 static void 400 pmtimer_configure(struct lpcib_softc *sc) 401 { 402 pcireg_t control; 403 404 /* 405 * Check if power management I/O space is enabled and enable the ACPI_EN 406 * bit if it's disabled. 407 */ 408 control = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL); 409 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 410 control |= LPCIB_PCI_ACPI_CNTL_EN; 411 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL, 412 control); 413 } 414 415 /* Attach our PM timer with the generic acpipmtimer function */ 416 acpipmtimer_attach(&sc->sc_dev, sc->sc_iot, sc->sc_ioh, 417 LPCIB_PM1_TMR, 0); 418 } 419 420 /* 421 * Initialize the watchdog timer. 422 */ 423 static void 424 tcotimer_configure(struct lpcib_softc *sc) 425 { 426 uint32_t ioreg; 427 unsigned int period; 428 429 /* 430 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 431 * in the SMI_EN register is the last chance. 432 */ 433 if (tcotimer_disable_noreboot(sc)) { 434 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 435 ioreg |= LPCIB_SMI_EN_TCO_EN; 436 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 437 } 438 439 /* Reset the watchdog status registers. */ 440 tcotimer_status_reset(sc); 441 442 /* Explicitly stop the TCO timer. */ 443 tcotimer_stop(sc); 444 445 /* 446 * Register the driver with the sysmon watchdog framework. 447 */ 448 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 449 sc->sc_smw.smw_cookie = sc; 450 sc->sc_smw.smw_setmode = tcotimer_setmode; 451 sc->sc_smw.smw_tickle = tcotimer_tickle; 452 if (sc->sc_has_rcba) 453 period = LPCIB_TCOTIMER2_MAX_TICK; 454 else 455 period = LPCIB_TCOTIMER_MAX_TICK; 456 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 457 458 if (sysmon_wdog_register(&sc->sc_smw)) { 459 aprint_error("%s: unable to register TCO timer" 460 "as a sysmon watchdog device.\n", 461 sc->sc_dev.dv_xname); 462 return; 463 } 464 465 aprint_verbose("%s: TCO (watchdog) timer configured.\n", 466 sc->sc_dev.dv_xname); 467 } 468 469 /* 470 * Sysmon watchdog callbacks. 471 */ 472 static int 473 tcotimer_setmode(struct sysmon_wdog *smw) 474 { 475 struct lpcib_softc *sc = smw->smw_cookie; 476 unsigned int period; 477 uint16_t ich6period = 0; 478 479 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 480 /* Stop the TCO timer. */ 481 tcotimer_stop(sc); 482 } else { 483 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 484 /* 485 * ICH6 or newer are limited to 2s min and 613s max. 486 * ICH5 or older are limited to 4s min and 39s max. 487 */ 488 if (sc->sc_has_rcba) { 489 if (period < LPCIB_TCOTIMER2_MIN_TICK || 490 period > LPCIB_TCOTIMER2_MAX_TICK) 491 return EINVAL; 492 } else { 493 if (period < LPCIB_TCOTIMER_MIN_TICK || 494 period > LPCIB_TCOTIMER_MAX_TICK) 495 return EINVAL; 496 } 497 498 /* Stop the TCO timer, */ 499 tcotimer_stop(sc); 500 501 /* set the timeout, */ 502 if (sc->sc_has_rcba) { 503 /* ICH6 or newer */ 504 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 505 LPCIB_TCO_TMR2); 506 ich6period &= 0xfc00; 507 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 508 LPCIB_TCO_TMR2, ich6period | period); 509 } else { 510 /* ICH5 or older */ 511 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 512 LPCIB_TCO_TMR); 513 period &= 0xc0; 514 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 515 LPCIB_TCO_TMR, period); 516 } 517 518 /* and start/reload the timer. */ 519 tcotimer_start(sc); 520 tcotimer_tickle(smw); 521 } 522 523 return 0; 524 } 525 526 static int 527 tcotimer_tickle(struct sysmon_wdog *smw) 528 { 529 struct lpcib_softc *sc = smw->smw_cookie; 530 531 /* any value is allowed */ 532 if (sc->sc_has_rcba) 533 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 534 else 535 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 536 537 return 0; 538 } 539 540 static void 541 tcotimer_stop(struct lpcib_softc *sc) 542 { 543 uint16_t ioreg; 544 545 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 546 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 547 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 548 } 549 550 static void 551 tcotimer_start(struct lpcib_softc *sc) 552 { 553 uint16_t ioreg; 554 555 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 556 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 557 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 558 } 559 560 static void 561 tcotimer_status_reset(struct lpcib_softc *sc) 562 { 563 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 564 LPCIB_TCO1_STS_TIMEOUT); 565 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 566 LPCIB_TCO2_STS_BOOT_STS); 567 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 568 LPCIB_TCO2_STS_SECONDS_TO_STS); 569 } 570 571 /* 572 * Clear the No Reboot (NR) bit, this enables reboots when the timer 573 * reaches the timeout for the second time. 574 */ 575 static int 576 tcotimer_disable_noreboot(struct lpcib_softc *sc) 577 { 578 579 if (sc->sc_has_rcba) { 580 uint32_t status; 581 582 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET); 583 status &= ~LPCIB_GCS_NO_REBOOT; 584 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET, status); 585 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET); 586 if (status & LPCIB_GCS_NO_REBOOT) 587 goto error; 588 } else { 589 pcireg_t pcireg; 590 591 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 592 LPCIB_PCI_GEN_STA); 593 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 594 /* TCO timeout reset is disabled; try to enable it */ 595 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 596 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 597 LPCIB_PCI_GEN_STA, pcireg); 598 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 599 goto error; 600 } 601 } 602 603 return 0; 604 error: 605 aprint_error("%s: TCO timer reboot disabled by hardware; " 606 "hope SMBIOS properly handles it.\n", sc->sc_dev.dv_xname); 607 return EINVAL; 608 } 609 610 611 /* 612 * Intel ICH SpeedStep support. 613 */ 614 #define SS_READ(sc, reg) \ 615 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 616 #define SS_WRITE(sc, reg, val) \ 617 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 618 619 /* 620 * Linux driver says that SpeedStep on older chipsets cause 621 * lockups on Dell Inspiron 8000 and 8100. 622 */ 623 static int 624 speedstep_bad_hb_check(struct pci_attach_args *pa) 625 { 626 627 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 628 PCI_REVISION(pa->pa_class) < 5) 629 return 1; 630 631 return 0; 632 } 633 634 static void 635 speedstep_configure(struct lpcib_softc *sc) 636 { 637 const struct sysctlnode *node, *ssnode; 638 int rv; 639 640 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 641 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 642 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 643 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 644 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 645 uint8_t pmcon; 646 647 /* Enable SpeedStep if it isn't already enabled. */ 648 pmcon = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 649 LPCIB_PCI_GEN_PMCON_1); 650 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 651 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 652 LPCIB_PCI_GEN_PMCON_1, 653 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 654 655 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 656 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 657 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 658 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 659 goto err; 660 661 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 662 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 663 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 664 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 665 CTL_EOL)) != 0) 666 goto err; 667 668 /* XXX save the sc for IO tag/handle */ 669 speedstep_cookie = sc; 670 aprint_verbose("%s: SpeedStep enabled\n", sc->sc_dev.dv_xname); 671 } 672 673 return; 674 675 err: 676 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 677 } 678 679 /* 680 * get/set the SpeedStep state: 0 == low power, 1 == high power. 681 */ 682 static int 683 speedstep_sysctl_helper(SYSCTLFN_ARGS) 684 { 685 struct sysctlnode node; 686 struct lpcib_softc *sc = speedstep_cookie; 687 uint8_t state, state2; 688 int ostate, nstate, s, error = 0; 689 690 /* 691 * We do the dance with spl's to avoid being at high ipl during 692 * sysctl_lookup() which can both copyin and copyout. 693 */ 694 s = splserial(); 695 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 696 splx(s); 697 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 698 ostate = 1; 699 else 700 ostate = 0; 701 nstate = ostate; 702 703 node = *rnode; 704 node.sysctl_data = &nstate; 705 706 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 707 if (error || newp == NULL) 708 goto out; 709 710 /* Only two states are available */ 711 if (nstate != 0 && nstate != 1) { 712 error = EINVAL; 713 goto out; 714 } 715 716 s = splserial(); 717 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 718 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 719 ostate = 1; 720 else 721 ostate = 0; 722 723 if (ostate != nstate) { 724 uint8_t cntl; 725 726 if (nstate == 0) 727 state2 |= LPCIB_PM_SS_STATE_LOW; 728 else 729 state2 &= ~LPCIB_PM_SS_STATE_LOW; 730 731 /* 732 * Must disable bus master arbitration during the change. 733 */ 734 cntl = SS_READ(sc, LPCIB_PM_CTRL); 735 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 736 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 737 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 738 } 739 splx(s); 740 out: 741 return error; 742 } 743 744 #if NHPET > 0 745 struct lpcib_hpet_attach_arg { 746 bus_space_tag_t hpet_mem_t; 747 uint32_t hpet_reg; 748 }; 749 750 static int 751 lpcib_hpet_match(struct device *self, struct cfdata *match, void *aux) 752 { 753 struct lpcib_hpet_attach_arg *arg = aux; 754 bus_space_tag_t tag; 755 bus_space_handle_t handle; 756 757 tag = arg->hpet_mem_t; 758 759 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 760 aprint_verbose("%s: HPET window not mapped, skipping\n", 761 self->dv_xname); 762 return 0; 763 } 764 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 765 766 return 1; 767 } 768 769 static void 770 lpcib_hpet_attach(struct device *parent, struct device *self, void *aux) 771 { 772 struct hpet_softc *sc = device_private(self); 773 struct lpcib_hpet_attach_arg *arg = aux; 774 775 aprint_naive("\n"); 776 aprint_normal("\n"); 777 778 sc->sc_memt = arg->hpet_mem_t; 779 780 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 781 &sc->sc_memh)) { 782 aprint_error("%s: HPET memory window could not be mapped", 783 sc->sc_dev.dv_xname); 784 return; 785 } 786 787 hpet_attach_subr(sc); 788 } 789 790 CFATTACH_DECL(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 791 lpcib_hpet_attach, NULL, NULL); 792 793 static void 794 lpcib_hpet_configure(struct lpcib_softc *sc) 795 { 796 struct lpcib_hpet_attach_arg arg; 797 uint32_t hpet_reg, val; 798 799 if (sc->sc_has_ich5_hpet) { 800 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_GEN_CNTL); 801 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 802 case LPCIB_ICH5_HPTC_0000: 803 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 804 break; 805 case LPCIB_ICH5_HPTC_1000: 806 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 807 break; 808 case LPCIB_ICH5_HPTC_2000: 809 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 810 break; 811 case LPCIB_ICH5_HPTC_3000: 812 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 813 break; 814 default: 815 return; 816 } 817 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 818 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_GEN_CNTL, val); 819 } else if (sc->sc_has_rcba) { 820 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 821 LPCIB_RCBA_HPTC); 822 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 823 case LPCIB_RCBA_HPTC_0000: 824 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 825 break; 826 case LPCIB_RCBA_HPTC_1000: 827 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 828 break; 829 case LPCIB_RCBA_HPTC_2000: 830 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 831 break; 832 case LPCIB_RCBA_HPTC_3000: 833 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 834 break; 835 default: 836 return; 837 } 838 val |= LPCIB_RCBA_HPTC_EN; 839 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 840 val); 841 } else { 842 /* No HPET here */ 843 return; 844 } 845 846 arg.hpet_mem_t = sc->sc_pa.pa_memt; 847 arg.hpet_reg = hpet_reg; 848 849 config_found_ia((struct device *)sc, "hpetichbus", &arg, NULL); 850 } 851 #endif 852
Indexes created Wed Oct 01 18:09:54 GMT 2025