ichlpcib.c revision 1.4.6.13
1 /* $NetBSD: ichlpcib.c,v 1.4.6.13 2007/10/01 05:37:23 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 41 * 42 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 43 * some power management and monitoring functions. 44 * Currently we support the watchdog timer, SpeedStep (on some systems) 45 * and the power management timer. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.4.6.13 2007/10/01 05:37:23 joerg Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/sysctl.h> 56 #include <sys/timetc.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/sysmon/sysmonvar.h> 64 65 #include <dev/ic/acpipmtimer.h> 66 #include <dev/ic/i82801lpcreg.h> 67 #include <dev/ic/hpetreg.h> 68 #include <dev/ic/hpetvar.h> 69 70 #include "hpet.h" 71 72 struct lpcib_softc { 73 /* Device object. */ 74 struct device sc_dev; 75 76 pci_chipset_tag_t sc_pc; 77 pcitag_t sc_pcitag; 78 struct pci_conf_state sc_pciconf; 79 80 struct pci_attach_args sc_pa; 81 int sc_has_rcba; 82 int sc_has_ich5_hpet; 83 84 /* RCBA */ 85 bus_space_tag_t sc_rcbat; 86 bus_space_handle_t sc_rcbah; 87 pcireg_t sc_rcba_reg; 88 89 /* Watchdog variables. */ 90 struct sysmon_wdog sc_smw; 91 bus_space_tag_t sc_iot; 92 bus_space_handle_t sc_ioh; 93 94 #if NHPET > 0 95 /* HPET variables. */ 96 uint32_t sc_hpet_reg; 97 #endif 98 99 /* Power management */ 100 pcireg_t sc_pirq[8]; 101 pcireg_t sc_pmcon; 102 pcireg_t sc_fwhsel2; 103 }; 104 105 static int lpcibmatch(struct device *, struct cfdata *, void *); 106 static void lpcibattach(struct device *, struct device *, void *); 107 static void lpcib_suspend(device_t); 108 static void lpcib_resume(device_t); 109 110 static void pmtimer_configure(struct lpcib_softc *); 111 112 static void tcotimer_configure(struct lpcib_softc *); 113 static int tcotimer_setmode(struct sysmon_wdog *); 114 static int tcotimer_tickle(struct sysmon_wdog *); 115 static void tcotimer_stop(struct lpcib_softc *); 116 static void tcotimer_start(struct lpcib_softc *); 117 static void tcotimer_status_reset(struct lpcib_softc *); 118 static int tcotimer_disable_noreboot(struct lpcib_softc *); 119 120 static void speedstep_configure(struct lpcib_softc *); 121 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 122 123 #if NHPET > 0 124 static void lpcib_hpet_configure(struct lpcib_softc *); 125 #endif 126 127 struct lpcib_softc *speedstep_cookie; /* XXX */ 128 129 /* Defined in arch/.../pci/pcib.c. */ 130 extern void pcibattach(struct device *, struct device *, void *); 131 132 CFATTACH_DECL(ichlpcib, sizeof(struct lpcib_softc), 133 lpcibmatch, lpcibattach, NULL, NULL); 134 135 static struct lpcib_device { 136 pcireg_t vendor, product; 137 int has_rcba; 138 int has_ich5_hpet; 139 } lpcib_devices[] = { 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 162 { 0, 0, 0, 0 }, 163 }; 164 165 /* 166 * Autoconf callbacks. 167 */ 168 static int 169 lpcibmatch(struct device *parent, struct cfdata *match, void *aux) 170 { 171 struct pci_attach_args *pa = aux; 172 struct lpcib_device *lpcib_dev; 173 174 /* We are ISA bridge, of course */ 175 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 176 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 177 return 0; 178 179 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 180 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 181 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 182 return 10; 183 } 184 185 return 0; 186 } 187 188 static void 189 lpcibattach(struct device *parent, struct device *self, void *aux) 190 { 191 struct pci_attach_args *pa = aux; 192 struct lpcib_softc *sc = device_private(self); 193 struct lpcib_device *lpcib_dev; 194 pnp_status_t pnp_status; 195 196 sc->sc_pc = pa->pa_pc; 197 sc->sc_pcitag = pa->pa_tag; 198 sc->sc_pa = *pa; 199 200 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 201 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 202 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 203 continue; 204 sc->sc_has_rcba = lpcib_dev->has_rcba; 205 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 206 break; 207 } 208 209 pcibattach(parent, self, aux); 210 211 /* 212 * Part of our I/O registers are used as ACPI PM regs. 213 * Since our ACPI subsystem accesses the I/O space directly so far, 214 * we do not have to bother bus_space I/O map confliction. 215 */ 216 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 217 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 218 aprint_error("%s: can't map power management i/o space", 219 sc->sc_dev.dv_xname); 220 return; 221 } 222 223 /* For ICH6 and later, always enable RCBA */ 224 if (sc->sc_has_rcba) { 225 pcireg_t rcba; 226 227 sc->sc_rcbat = sc->sc_pa.pa_memt; 228 229 rcba = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_RCBA); 230 if ((rcba & LPCIB_RCBA_EN) == 0) { 231 aprint_error("%s: RCBA is not enabled", 232 sc->sc_dev.dv_xname); 233 return; 234 } 235 rcba &= ~LPCIB_RCBA_EN; 236 237 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 238 &sc->sc_rcbah)) { 239 aprint_error("%s: RCBA could not be mapped", 240 sc->sc_dev.dv_xname); 241 return; 242 } 243 } 244 245 /* Set up the power management timer. */ 246 pmtimer_configure(sc); 247 248 /* Set up the TCO (watchdog). */ 249 tcotimer_configure(sc); 250 251 /* Set up SpeedStep. */ 252 speedstep_configure(sc); 253 254 #if NHPET > 0 255 /* Set up HPET. */ 256 lpcib_hpet_configure(sc); 257 #endif 258 259 /* Install power handler */ 260 pnp_status = pci_generic_power_register(self, pa->pa_pc, pa->pa_tag, 261 lpcib_suspend, lpcib_resume); 262 if (pnp_status != PNP_STATUS_SUCCESS) { 263 aprint_error("%s: couldn't establish power handler\n", 264 device_xname(self)); 265 } 266 } 267 268 static void 269 lpcib_suspend(device_t dv) 270 { 271 struct lpcib_softc *sc = device_private(dv); 272 pci_chipset_tag_t pc = sc->sc_pc; 273 pcitag_t tag = sc->sc_pcitag; 274 275 /* capture PIRQ routing control registers */ 276 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 277 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQB_ROUT); 278 sc->sc_pirq[2] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQC_ROUT); 279 sc->sc_pirq[3] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQD_ROUT); 280 sc->sc_pirq[4] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 281 sc->sc_pirq[5] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQF_ROUT); 282 sc->sc_pirq[6] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQG_ROUT); 283 sc->sc_pirq[7] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQH_ROUT); 284 285 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 286 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 287 288 if (sc->sc_has_rcba) { 289 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 290 #if NHPET > 0 291 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 292 LPCIB_RCBA_HPTC); 293 #endif 294 } else if (sc->sc_has_ich5_hpet) { 295 #if NHPET > 0 296 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 297 #endif 298 } 299 } 300 301 static void 302 lpcib_resume(device_t dv) 303 { 304 struct lpcib_softc *sc = device_private(dv); 305 pci_chipset_tag_t pc = sc->sc_pc; 306 pcitag_t tag = sc->sc_pcitag; 307 308 /* restore PIRQ routing control registers */ 309 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 310 pci_conf_write(pc, tag, LPCIB_PCI_PIRQB_ROUT, sc->sc_pirq[1]); 311 pci_conf_write(pc, tag, LPCIB_PCI_PIRQC_ROUT, sc->sc_pirq[2]); 312 pci_conf_write(pc, tag, LPCIB_PCI_PIRQD_ROUT, sc->sc_pirq[3]); 313 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[4]); 314 pci_conf_write(pc, tag, LPCIB_PCI_PIRQF_ROUT, sc->sc_pirq[5]); 315 pci_conf_write(pc, tag, LPCIB_PCI_PIRQG_ROUT, sc->sc_pirq[6]); 316 pci_conf_write(pc, tag, LPCIB_PCI_PIRQH_ROUT, sc->sc_pirq[7]); 317 318 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 319 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 320 321 if (sc->sc_has_rcba) { 322 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 323 #if NHPET > 0 324 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 325 sc->sc_hpet_reg); 326 #endif 327 } else if (sc->sc_has_ich5_hpet) { 328 #if NHPET > 0 329 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 330 #endif 331 } 332 } 333 334 /* 335 * Initialize the power management timer. 336 */ 337 static void 338 pmtimer_configure(struct lpcib_softc *sc) 339 { 340 pcireg_t control; 341 342 /* 343 * Check if power management I/O space is enabled and enable the ACPI_EN 344 * bit if it's disabled. 345 */ 346 control = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL); 347 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 348 control |= LPCIB_PCI_ACPI_CNTL_EN; 349 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL, 350 control); 351 } 352 353 /* Attach our PM timer with the generic acpipmtimer function */ 354 acpipmtimer_attach(&sc->sc_dev, sc->sc_iot, sc->sc_ioh, 355 LPCIB_PM1_TMR, 0); 356 } 357 358 /* 359 * Initialize the watchdog timer. 360 */ 361 static void 362 tcotimer_configure(struct lpcib_softc *sc) 363 { 364 uint32_t ioreg; 365 unsigned int period; 366 367 /* 368 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 369 * in the SMI_EN register is the last chance. 370 */ 371 if (tcotimer_disable_noreboot(sc)) { 372 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 373 ioreg |= LPCIB_SMI_EN_TCO_EN; 374 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 375 } 376 377 /* Reset the watchdog status registers. */ 378 tcotimer_status_reset(sc); 379 380 /* Explicitly stop the TCO timer. */ 381 tcotimer_stop(sc); 382 383 /* 384 * Register the driver with the sysmon watchdog framework. 385 */ 386 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 387 sc->sc_smw.smw_cookie = sc; 388 sc->sc_smw.smw_setmode = tcotimer_setmode; 389 sc->sc_smw.smw_tickle = tcotimer_tickle; 390 if (sc->sc_has_rcba) 391 period = LPCIB_TCOTIMER2_MAX_TICK; 392 else 393 period = LPCIB_TCOTIMER_MAX_TICK; 394 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 395 396 if (sysmon_wdog_register(&sc->sc_smw)) { 397 aprint_error("%s: unable to register TCO timer" 398 "as a sysmon watchdog device.\n", 399 sc->sc_dev.dv_xname); 400 return; 401 } 402 403 aprint_verbose("%s: TCO (watchdog) timer configured.\n", 404 sc->sc_dev.dv_xname); 405 } 406 407 /* 408 * Sysmon watchdog callbacks. 409 */ 410 static int 411 tcotimer_setmode(struct sysmon_wdog *smw) 412 { 413 struct lpcib_softc *sc = smw->smw_cookie; 414 unsigned int period; 415 uint16_t ich6period = 0; 416 417 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 418 /* Stop the TCO timer. */ 419 tcotimer_stop(sc); 420 } else { 421 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 422 /* 423 * ICH6 or newer are limited to 2s min and 613s max. 424 * ICH5 or older are limited to 4s min and 39s max. 425 */ 426 if (sc->sc_has_rcba) { 427 if (period < LPCIB_TCOTIMER2_MIN_TICK || 428 period > LPCIB_TCOTIMER2_MAX_TICK) 429 return EINVAL; 430 } else { 431 if (period < LPCIB_TCOTIMER_MIN_TICK || 432 period > LPCIB_TCOTIMER_MAX_TICK) 433 return EINVAL; 434 } 435 436 /* Stop the TCO timer, */ 437 tcotimer_stop(sc); 438 439 /* set the timeout, */ 440 if (sc->sc_has_rcba) { 441 /* ICH6 or newer */ 442 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 443 LPCIB_TCO_TMR2); 444 ich6period &= 0xfc00; 445 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 446 LPCIB_TCO_TMR2, ich6period | period); 447 } else { 448 /* ICH5 or older */ 449 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 450 LPCIB_TCO_TMR); 451 period &= 0xc0; 452 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 453 LPCIB_TCO_TMR, period); 454 } 455 456 /* and start/reload the timer. */ 457 tcotimer_start(sc); 458 tcotimer_tickle(smw); 459 } 460 461 return 0; 462 } 463 464 static int 465 tcotimer_tickle(struct sysmon_wdog *smw) 466 { 467 struct lpcib_softc *sc = smw->smw_cookie; 468 469 /* any value is allowed */ 470 if (sc->sc_has_rcba) 471 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 472 else 473 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 474 475 return 0; 476 } 477 478 static void 479 tcotimer_stop(struct lpcib_softc *sc) 480 { 481 uint16_t ioreg; 482 483 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 484 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 485 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 486 } 487 488 static void 489 tcotimer_start(struct lpcib_softc *sc) 490 { 491 uint16_t ioreg; 492 493 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 494 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 495 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 496 } 497 498 static void 499 tcotimer_status_reset(struct lpcib_softc *sc) 500 { 501 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 502 LPCIB_TCO1_STS_TIMEOUT); 503 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 504 LPCIB_TCO2_STS_BOOT_STS); 505 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 506 LPCIB_TCO2_STS_SECONDS_TO_STS); 507 } 508 509 /* 510 * Clear the No Reboot (NR) bit, this enables reboots when the timer 511 * reaches the timeout for the second time. 512 */ 513 static int 514 tcotimer_disable_noreboot(struct lpcib_softc *sc) 515 { 516 517 if (sc->sc_has_rcba) { 518 uint32_t status; 519 520 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET); 521 status &= ~LPCIB_GCS_NO_REBOOT; 522 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET, status); 523 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET); 524 if (status & LPCIB_GCS_NO_REBOOT) 525 goto error; 526 } else { 527 pcireg_t pcireg; 528 529 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 530 LPCIB_PCI_GEN_STA); 531 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 532 /* TCO timeout reset is disabled; try to enable it */ 533 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 534 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 535 LPCIB_PCI_GEN_STA, pcireg); 536 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 537 goto error; 538 } 539 } 540 541 return 0; 542 error: 543 aprint_error("%s: TCO timer reboot disabled by hardware; " 544 "hope SMBIOS properly handles it.\n", sc->sc_dev.dv_xname); 545 return EINVAL; 546 } 547 548 549 /* 550 * Intel ICH SpeedStep support. 551 */ 552 #define SS_READ(sc, reg) \ 553 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 554 #define SS_WRITE(sc, reg, val) \ 555 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 556 557 /* 558 * Linux driver says that SpeedStep on older chipsets cause 559 * lockups on Dell Inspiron 8000 and 8100. 560 */ 561 static int 562 speedstep_bad_hb_check(struct pci_attach_args *pa) 563 { 564 565 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 566 PCI_REVISION(pa->pa_class) < 5) 567 return 1; 568 569 return 0; 570 } 571 572 static void 573 speedstep_configure(struct lpcib_softc *sc) 574 { 575 const struct sysctlnode *node, *ssnode; 576 int rv; 577 578 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 579 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 580 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 581 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 582 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 583 uint8_t pmcon; 584 585 /* Enable SpeedStep if it isn't already enabled. */ 586 pmcon = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 587 LPCIB_PCI_GEN_PMCON_1); 588 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 589 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 590 LPCIB_PCI_GEN_PMCON_1, 591 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 592 593 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 594 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 595 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 596 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 597 goto err; 598 599 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 600 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 601 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 602 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 603 CTL_EOL)) != 0) 604 goto err; 605 606 /* XXX save the sc for IO tag/handle */ 607 speedstep_cookie = sc; 608 aprint_verbose("%s: SpeedStep enabled\n", sc->sc_dev.dv_xname); 609 } 610 611 return; 612 613 err: 614 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 615 } 616 617 /* 618 * get/set the SpeedStep state: 0 == low power, 1 == high power. 619 */ 620 static int 621 speedstep_sysctl_helper(SYSCTLFN_ARGS) 622 { 623 struct sysctlnode node; 624 struct lpcib_softc *sc = speedstep_cookie; 625 uint8_t state, state2; 626 int ostate, nstate, s, error = 0; 627 628 /* 629 * We do the dance with spl's to avoid being at high ipl during 630 * sysctl_lookup() which can both copyin and copyout. 631 */ 632 s = splserial(); 633 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 634 splx(s); 635 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 636 ostate = 1; 637 else 638 ostate = 0; 639 nstate = ostate; 640 641 node = *rnode; 642 node.sysctl_data = &nstate; 643 644 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 645 if (error || newp == NULL) 646 goto out; 647 648 /* Only two states are available */ 649 if (nstate != 0 && nstate != 1) { 650 error = EINVAL; 651 goto out; 652 } 653 654 s = splserial(); 655 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 656 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 657 ostate = 1; 658 else 659 ostate = 0; 660 661 if (ostate != nstate) { 662 uint8_t cntl; 663 664 if (nstate == 0) 665 state2 |= LPCIB_PM_SS_STATE_LOW; 666 else 667 state2 &= ~LPCIB_PM_SS_STATE_LOW; 668 669 /* 670 * Must disable bus master arbitration during the change. 671 */ 672 cntl = SS_READ(sc, LPCIB_PM_CTRL); 673 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 674 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 675 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 676 } 677 splx(s); 678 out: 679 return error; 680 } 681 682 #if NHPET > 0 683 struct lpcib_hpet_attach_arg { 684 bus_space_tag_t hpet_mem_t; 685 uint32_t hpet_reg; 686 }; 687 688 static int 689 lpcib_hpet_match(device_t parent, struct cfdata *match, void *aux) 690 { 691 struct lpcib_hpet_attach_arg *arg = aux; 692 bus_space_tag_t tag; 693 bus_space_handle_t handle; 694 695 tag = arg->hpet_mem_t; 696 697 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 698 aprint_verbose("%s: HPET window not mapped, skipping\n", 699 parent->dv_xname); 700 return 0; 701 } 702 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 703 704 return 1; 705 } 706 707 static void 708 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 709 { 710 struct hpet_softc *sc = device_private(self); 711 struct lpcib_hpet_attach_arg *arg = aux; 712 713 aprint_naive("\n"); 714 aprint_normal("\n"); 715 716 sc->sc_memt = arg->hpet_mem_t; 717 718 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 719 &sc->sc_memh)) { 720 aprint_error("%s: HPET memory window could not be mapped", 721 sc->sc_dev.dv_xname); 722 return; 723 } 724 725 hpet_attach_subr(sc); 726 } 727 728 CFATTACH_DECL(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 729 lpcib_hpet_attach, NULL, NULL); 730 731 static void 732 lpcib_hpet_configure(struct lpcib_softc *sc) 733 { 734 struct lpcib_hpet_attach_arg arg; 735 uint32_t hpet_reg, val; 736 737 if (sc->sc_has_ich5_hpet) { 738 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_GEN_CNTL); 739 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 740 case LPCIB_ICH5_HPTC_0000: 741 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 742 break; 743 case LPCIB_ICH5_HPTC_1000: 744 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 745 break; 746 case LPCIB_ICH5_HPTC_2000: 747 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 748 break; 749 case LPCIB_ICH5_HPTC_3000: 750 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 751 break; 752 default: 753 return; 754 } 755 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 756 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_GEN_CNTL, val); 757 } else if (sc->sc_has_rcba) { 758 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 759 LPCIB_RCBA_HPTC); 760 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 761 case LPCIB_RCBA_HPTC_0000: 762 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 763 break; 764 case LPCIB_RCBA_HPTC_1000: 765 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 766 break; 767 case LPCIB_RCBA_HPTC_2000: 768 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 769 break; 770 case LPCIB_RCBA_HPTC_3000: 771 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 772 break; 773 default: 774 return; 775 } 776 val |= LPCIB_RCBA_HPTC_EN; 777 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 778 val); 779 } else { 780 /* No HPET here */ 781 return; 782 } 783 784 arg.hpet_mem_t = sc->sc_pa.pa_memt; 785 arg.hpet_reg = hpet_reg; 786 787 config_found_ia((struct device *)sc, "hpetichbus", &arg, NULL); 788 } 789 #endif 790
Indexes created Wed Oct 01 18:09:54 GMT 2025