ichlpcib.c revision 1.4.6.14
1 /* $NetBSD: ichlpcib.c,v 1.4.6.14 2007/11/06 14:27:10 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 41 * 42 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 43 * some power management and monitoring functions. 44 * Currently we support the watchdog timer, SpeedStep (on some systems) 45 * and the power management timer. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.4.6.14 2007/11/06 14:27:10 joerg Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/sysctl.h> 56 #include <sys/timetc.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/sysmon/sysmonvar.h> 64 65 #include <dev/ic/acpipmtimer.h> 66 #include <dev/ic/i82801lpcreg.h> 67 #include <dev/ic/hpetreg.h> 68 #include <dev/ic/hpetvar.h> 69 70 #include "hpet.h" 71 72 struct lpcib_softc { 73 /* Device object. */ 74 struct device sc_dev; 75 76 pci_chipset_tag_t sc_pc; 77 pcitag_t sc_pcitag; 78 struct pci_conf_state sc_pciconf; 79 80 struct pci_attach_args sc_pa; 81 int sc_has_rcba; 82 int sc_has_ich5_hpet; 83 84 /* RCBA */ 85 bus_space_tag_t sc_rcbat; 86 bus_space_handle_t sc_rcbah; 87 pcireg_t sc_rcba_reg; 88 89 /* Watchdog variables. */ 90 struct sysmon_wdog sc_smw; 91 bus_space_tag_t sc_iot; 92 bus_space_handle_t sc_ioh; 93 94 #if NHPET > 0 95 /* HPET variables. */ 96 uint32_t sc_hpet_reg; 97 #endif 98 99 /* Power management */ 100 pcireg_t sc_pirq[8]; 101 pcireg_t sc_pmcon; 102 pcireg_t sc_fwhsel2; 103 }; 104 105 static int lpcibmatch(struct device *, struct cfdata *, void *); 106 static void lpcibattach(struct device *, struct device *, void *); 107 static bool lpcib_suspend(device_t); 108 static bool lpcib_resume(device_t); 109 110 static void pmtimer_configure(struct lpcib_softc *); 111 112 static void tcotimer_configure(struct lpcib_softc *); 113 static int tcotimer_setmode(struct sysmon_wdog *); 114 static int tcotimer_tickle(struct sysmon_wdog *); 115 static void tcotimer_stop(struct lpcib_softc *); 116 static void tcotimer_start(struct lpcib_softc *); 117 static void tcotimer_status_reset(struct lpcib_softc *); 118 static int tcotimer_disable_noreboot(struct lpcib_softc *); 119 120 static void speedstep_configure(struct lpcib_softc *); 121 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 122 123 #if NHPET > 0 124 static void lpcib_hpet_configure(struct lpcib_softc *); 125 #endif 126 127 struct lpcib_softc *speedstep_cookie; /* XXX */ 128 129 /* Defined in arch/.../pci/pcib.c. */ 130 extern void pcibattach(struct device *, struct device *, void *); 131 132 CFATTACH_DECL(ichlpcib, sizeof(struct lpcib_softc), 133 lpcibmatch, lpcibattach, NULL, NULL); 134 135 static struct lpcib_device { 136 pcireg_t vendor, product; 137 int has_rcba; 138 int has_ich5_hpet; 139 } lpcib_devices[] = { 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 162 { 0, 0, 0, 0 }, 163 }; 164 165 /* 166 * Autoconf callbacks. 167 */ 168 static int 169 lpcibmatch(struct device *parent, struct cfdata *match, void *aux) 170 { 171 struct pci_attach_args *pa = aux; 172 struct lpcib_device *lpcib_dev; 173 174 /* We are ISA bridge, of course */ 175 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 176 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 177 return 0; 178 179 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 180 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 181 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 182 return 10; 183 } 184 185 return 0; 186 } 187 188 static void 189 lpcibattach(struct device *parent, struct device *self, void *aux) 190 { 191 struct pci_attach_args *pa = aux; 192 struct lpcib_softc *sc = device_private(self); 193 struct lpcib_device *lpcib_dev; 194 195 sc->sc_pc = pa->pa_pc; 196 sc->sc_pcitag = pa->pa_tag; 197 sc->sc_pa = *pa; 198 199 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 200 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 201 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 202 continue; 203 sc->sc_has_rcba = lpcib_dev->has_rcba; 204 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 205 break; 206 } 207 208 pcibattach(parent, self, aux); 209 210 /* 211 * Part of our I/O registers are used as ACPI PM regs. 212 * Since our ACPI subsystem accesses the I/O space directly so far, 213 * we do not have to bother bus_space I/O map confliction. 214 */ 215 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 216 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 217 aprint_error("%s: can't map power management i/o space", 218 sc->sc_dev.dv_xname); 219 return; 220 } 221 222 /* For ICH6 and later, always enable RCBA */ 223 if (sc->sc_has_rcba) { 224 pcireg_t rcba; 225 226 sc->sc_rcbat = sc->sc_pa.pa_memt; 227 228 rcba = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_RCBA); 229 if ((rcba & LPCIB_RCBA_EN) == 0) { 230 aprint_error("%s: RCBA is not enabled", 231 sc->sc_dev.dv_xname); 232 return; 233 } 234 rcba &= ~LPCIB_RCBA_EN; 235 236 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 237 &sc->sc_rcbah)) { 238 aprint_error("%s: RCBA could not be mapped", 239 sc->sc_dev.dv_xname); 240 return; 241 } 242 } 243 244 /* Set up the power management timer. */ 245 pmtimer_configure(sc); 246 247 /* Set up the TCO (watchdog). */ 248 tcotimer_configure(sc); 249 250 /* Set up SpeedStep. */ 251 speedstep_configure(sc); 252 253 #if NHPET > 0 254 /* Set up HPET. */ 255 lpcib_hpet_configure(sc); 256 #endif 257 258 /* Install power handler */ 259 if (!pnp_device_register(self, lpcib_suspend, lpcib_resume)) 260 aprint_error_dev(self, "couldn't establish power handler\n"); 261 } 262 263 static bool 264 lpcib_suspend(device_t dv) 265 { 266 struct lpcib_softc *sc = device_private(dv); 267 pci_chipset_tag_t pc = sc->sc_pc; 268 pcitag_t tag = sc->sc_pcitag; 269 270 /* capture PIRQ routing control registers */ 271 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 272 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQB_ROUT); 273 sc->sc_pirq[2] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQC_ROUT); 274 sc->sc_pirq[3] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQD_ROUT); 275 sc->sc_pirq[4] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 276 sc->sc_pirq[5] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQF_ROUT); 277 sc->sc_pirq[6] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQG_ROUT); 278 sc->sc_pirq[7] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQH_ROUT); 279 280 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 281 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 282 283 if (sc->sc_has_rcba) { 284 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 285 #if NHPET > 0 286 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 287 LPCIB_RCBA_HPTC); 288 #endif 289 } else if (sc->sc_has_ich5_hpet) { 290 #if NHPET > 0 291 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 292 #endif 293 } 294 295 return true; 296 } 297 298 static bool 299 lpcib_resume(device_t dv) 300 { 301 struct lpcib_softc *sc = device_private(dv); 302 pci_chipset_tag_t pc = sc->sc_pc; 303 pcitag_t tag = sc->sc_pcitag; 304 305 /* restore PIRQ routing control registers */ 306 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 307 pci_conf_write(pc, tag, LPCIB_PCI_PIRQB_ROUT, sc->sc_pirq[1]); 308 pci_conf_write(pc, tag, LPCIB_PCI_PIRQC_ROUT, sc->sc_pirq[2]); 309 pci_conf_write(pc, tag, LPCIB_PCI_PIRQD_ROUT, sc->sc_pirq[3]); 310 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[4]); 311 pci_conf_write(pc, tag, LPCIB_PCI_PIRQF_ROUT, sc->sc_pirq[5]); 312 pci_conf_write(pc, tag, LPCIB_PCI_PIRQG_ROUT, sc->sc_pirq[6]); 313 pci_conf_write(pc, tag, LPCIB_PCI_PIRQH_ROUT, sc->sc_pirq[7]); 314 315 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 316 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 317 318 if (sc->sc_has_rcba) { 319 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 320 #if NHPET > 0 321 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 322 sc->sc_hpet_reg); 323 #endif 324 } else if (sc->sc_has_ich5_hpet) { 325 #if NHPET > 0 326 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 327 #endif 328 } 329 330 return true; 331 } 332 333 /* 334 * Initialize the power management timer. 335 */ 336 static void 337 pmtimer_configure(struct lpcib_softc *sc) 338 { 339 pcireg_t control; 340 341 /* 342 * Check if power management I/O space is enabled and enable the ACPI_EN 343 * bit if it's disabled. 344 */ 345 control = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL); 346 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 347 control |= LPCIB_PCI_ACPI_CNTL_EN; 348 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL, 349 control); 350 } 351 352 /* Attach our PM timer with the generic acpipmtimer function */ 353 acpipmtimer_attach(&sc->sc_dev, sc->sc_iot, sc->sc_ioh, 354 LPCIB_PM1_TMR, 0); 355 } 356 357 /* 358 * Initialize the watchdog timer. 359 */ 360 static void 361 tcotimer_configure(struct lpcib_softc *sc) 362 { 363 uint32_t ioreg; 364 unsigned int period; 365 366 /* 367 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 368 * in the SMI_EN register is the last chance. 369 */ 370 if (tcotimer_disable_noreboot(sc)) { 371 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 372 ioreg |= LPCIB_SMI_EN_TCO_EN; 373 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 374 } 375 376 /* Reset the watchdog status registers. */ 377 tcotimer_status_reset(sc); 378 379 /* Explicitly stop the TCO timer. */ 380 tcotimer_stop(sc); 381 382 /* 383 * Register the driver with the sysmon watchdog framework. 384 */ 385 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 386 sc->sc_smw.smw_cookie = sc; 387 sc->sc_smw.smw_setmode = tcotimer_setmode; 388 sc->sc_smw.smw_tickle = tcotimer_tickle; 389 if (sc->sc_has_rcba) 390 period = LPCIB_TCOTIMER2_MAX_TICK; 391 else 392 period = LPCIB_TCOTIMER_MAX_TICK; 393 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 394 395 if (sysmon_wdog_register(&sc->sc_smw)) { 396 aprint_error("%s: unable to register TCO timer" 397 "as a sysmon watchdog device.\n", 398 sc->sc_dev.dv_xname); 399 return; 400 } 401 402 aprint_verbose("%s: TCO (watchdog) timer configured.\n", 403 sc->sc_dev.dv_xname); 404 } 405 406 /* 407 * Sysmon watchdog callbacks. 408 */ 409 static int 410 tcotimer_setmode(struct sysmon_wdog *smw) 411 { 412 struct lpcib_softc *sc = smw->smw_cookie; 413 unsigned int period; 414 uint16_t ich6period = 0; 415 416 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 417 /* Stop the TCO timer. */ 418 tcotimer_stop(sc); 419 } else { 420 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 421 /* 422 * ICH6 or newer are limited to 2s min and 613s max. 423 * ICH5 or older are limited to 4s min and 39s max. 424 */ 425 if (sc->sc_has_rcba) { 426 if (period < LPCIB_TCOTIMER2_MIN_TICK || 427 period > LPCIB_TCOTIMER2_MAX_TICK) 428 return EINVAL; 429 } else { 430 if (period < LPCIB_TCOTIMER_MIN_TICK || 431 period > LPCIB_TCOTIMER_MAX_TICK) 432 return EINVAL; 433 } 434 435 /* Stop the TCO timer, */ 436 tcotimer_stop(sc); 437 438 /* set the timeout, */ 439 if (sc->sc_has_rcba) { 440 /* ICH6 or newer */ 441 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 442 LPCIB_TCO_TMR2); 443 ich6period &= 0xfc00; 444 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 445 LPCIB_TCO_TMR2, ich6period | period); 446 } else { 447 /* ICH5 or older */ 448 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 449 LPCIB_TCO_TMR); 450 period &= 0xc0; 451 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 452 LPCIB_TCO_TMR, period); 453 } 454 455 /* and start/reload the timer. */ 456 tcotimer_start(sc); 457 tcotimer_tickle(smw); 458 } 459 460 return 0; 461 } 462 463 static int 464 tcotimer_tickle(struct sysmon_wdog *smw) 465 { 466 struct lpcib_softc *sc = smw->smw_cookie; 467 468 /* any value is allowed */ 469 if (sc->sc_has_rcba) 470 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 471 else 472 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 473 474 return 0; 475 } 476 477 static void 478 tcotimer_stop(struct lpcib_softc *sc) 479 { 480 uint16_t ioreg; 481 482 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 483 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 484 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 485 } 486 487 static void 488 tcotimer_start(struct lpcib_softc *sc) 489 { 490 uint16_t ioreg; 491 492 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 493 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 494 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 495 } 496 497 static void 498 tcotimer_status_reset(struct lpcib_softc *sc) 499 { 500 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 501 LPCIB_TCO1_STS_TIMEOUT); 502 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 503 LPCIB_TCO2_STS_BOOT_STS); 504 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 505 LPCIB_TCO2_STS_SECONDS_TO_STS); 506 } 507 508 /* 509 * Clear the No Reboot (NR) bit, this enables reboots when the timer 510 * reaches the timeout for the second time. 511 */ 512 static int 513 tcotimer_disable_noreboot(struct lpcib_softc *sc) 514 { 515 516 if (sc->sc_has_rcba) { 517 uint32_t status; 518 519 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET); 520 status &= ~LPCIB_GCS_NO_REBOOT; 521 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET, status); 522 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET); 523 if (status & LPCIB_GCS_NO_REBOOT) 524 goto error; 525 } else { 526 pcireg_t pcireg; 527 528 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 529 LPCIB_PCI_GEN_STA); 530 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 531 /* TCO timeout reset is disabled; try to enable it */ 532 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 533 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 534 LPCIB_PCI_GEN_STA, pcireg); 535 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 536 goto error; 537 } 538 } 539 540 return 0; 541 error: 542 aprint_error("%s: TCO timer reboot disabled by hardware; " 543 "hope SMBIOS properly handles it.\n", sc->sc_dev.dv_xname); 544 return EINVAL; 545 } 546 547 548 /* 549 * Intel ICH SpeedStep support. 550 */ 551 #define SS_READ(sc, reg) \ 552 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 553 #define SS_WRITE(sc, reg, val) \ 554 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 555 556 /* 557 * Linux driver says that SpeedStep on older chipsets cause 558 * lockups on Dell Inspiron 8000 and 8100. 559 */ 560 static int 561 speedstep_bad_hb_check(struct pci_attach_args *pa) 562 { 563 564 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 565 PCI_REVISION(pa->pa_class) < 5) 566 return 1; 567 568 return 0; 569 } 570 571 static void 572 speedstep_configure(struct lpcib_softc *sc) 573 { 574 const struct sysctlnode *node, *ssnode; 575 int rv; 576 577 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 578 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 579 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 580 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 581 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 582 uint8_t pmcon; 583 584 /* Enable SpeedStep if it isn't already enabled. */ 585 pmcon = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 586 LPCIB_PCI_GEN_PMCON_1); 587 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 588 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 589 LPCIB_PCI_GEN_PMCON_1, 590 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 591 592 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 593 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 594 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 595 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 596 goto err; 597 598 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 599 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 600 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 601 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 602 CTL_EOL)) != 0) 603 goto err; 604 605 /* XXX save the sc for IO tag/handle */ 606 speedstep_cookie = sc; 607 aprint_verbose("%s: SpeedStep enabled\n", sc->sc_dev.dv_xname); 608 } 609 610 return; 611 612 err: 613 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 614 } 615 616 /* 617 * get/set the SpeedStep state: 0 == low power, 1 == high power. 618 */ 619 static int 620 speedstep_sysctl_helper(SYSCTLFN_ARGS) 621 { 622 struct sysctlnode node; 623 struct lpcib_softc *sc = speedstep_cookie; 624 uint8_t state, state2; 625 int ostate, nstate, s, error = 0; 626 627 /* 628 * We do the dance with spl's to avoid being at high ipl during 629 * sysctl_lookup() which can both copyin and copyout. 630 */ 631 s = splserial(); 632 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 633 splx(s); 634 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 635 ostate = 1; 636 else 637 ostate = 0; 638 nstate = ostate; 639 640 node = *rnode; 641 node.sysctl_data = &nstate; 642 643 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 644 if (error || newp == NULL) 645 goto out; 646 647 /* Only two states are available */ 648 if (nstate != 0 && nstate != 1) { 649 error = EINVAL; 650 goto out; 651 } 652 653 s = splserial(); 654 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 655 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 656 ostate = 1; 657 else 658 ostate = 0; 659 660 if (ostate != nstate) { 661 uint8_t cntl; 662 663 if (nstate == 0) 664 state2 |= LPCIB_PM_SS_STATE_LOW; 665 else 666 state2 &= ~LPCIB_PM_SS_STATE_LOW; 667 668 /* 669 * Must disable bus master arbitration during the change. 670 */ 671 cntl = SS_READ(sc, LPCIB_PM_CTRL); 672 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 673 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 674 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 675 } 676 splx(s); 677 out: 678 return error; 679 } 680 681 #if NHPET > 0 682 struct lpcib_hpet_attach_arg { 683 bus_space_tag_t hpet_mem_t; 684 uint32_t hpet_reg; 685 }; 686 687 static int 688 lpcib_hpet_match(device_t parent, struct cfdata *match, void *aux) 689 { 690 struct lpcib_hpet_attach_arg *arg = aux; 691 bus_space_tag_t tag; 692 bus_space_handle_t handle; 693 694 tag = arg->hpet_mem_t; 695 696 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 697 aprint_verbose("%s: HPET window not mapped, skipping\n", 698 parent->dv_xname); 699 return 0; 700 } 701 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 702 703 return 1; 704 } 705 706 static void 707 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 708 { 709 struct hpet_softc *sc = device_private(self); 710 struct lpcib_hpet_attach_arg *arg = aux; 711 712 aprint_naive("\n"); 713 aprint_normal("\n"); 714 715 sc->sc_memt = arg->hpet_mem_t; 716 717 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 718 &sc->sc_memh)) { 719 aprint_error("%s: HPET memory window could not be mapped", 720 sc->sc_dev.dv_xname); 721 return; 722 } 723 724 hpet_attach_subr(sc); 725 } 726 727 CFATTACH_DECL(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 728 lpcib_hpet_attach, NULL, NULL); 729 730 static void 731 lpcib_hpet_configure(struct lpcib_softc *sc) 732 { 733 struct lpcib_hpet_attach_arg arg; 734 uint32_t hpet_reg, val; 735 736 if (sc->sc_has_ich5_hpet) { 737 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_GEN_CNTL); 738 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 739 case LPCIB_ICH5_HPTC_0000: 740 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 741 break; 742 case LPCIB_ICH5_HPTC_1000: 743 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 744 break; 745 case LPCIB_ICH5_HPTC_2000: 746 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 747 break; 748 case LPCIB_ICH5_HPTC_3000: 749 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 750 break; 751 default: 752 return; 753 } 754 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 755 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_GEN_CNTL, val); 756 } else if (sc->sc_has_rcba) { 757 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 758 LPCIB_RCBA_HPTC); 759 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 760 case LPCIB_RCBA_HPTC_0000: 761 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 762 break; 763 case LPCIB_RCBA_HPTC_1000: 764 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 765 break; 766 case LPCIB_RCBA_HPTC_2000: 767 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 768 break; 769 case LPCIB_RCBA_HPTC_3000: 770 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 771 break; 772 default: 773 return; 774 } 775 val |= LPCIB_RCBA_HPTC_EN; 776 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 777 val); 778 } else { 779 /* No HPET here */ 780 return; 781 } 782 783 arg.hpet_mem_t = sc->sc_pa.pa_memt; 784 arg.hpet_reg = hpet_reg; 785 786 config_found_ia((struct device *)sc, "hpetichbus", &arg, NULL); 787 } 788 #endif 789
Indexes created Wed Oct 01 18:09:54 GMT 2025