ichlpcib.c revision 1.4.6.3
1 /* $NetBSD: ichlpcib.c,v 1.4.6.3 2007/09/04 15:54:04 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 41 * 42 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 43 * some power management and monitoring functions. 44 * Currently we support the watchdog timer, SpeedStep (on some systems) 45 * and the power management timer. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.4.6.3 2007/09/04 15:54:04 joerg Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/sysctl.h> 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 #include <dev/ic/i82801lpcreg.h> 65 #include <dev/ic/acpipmtimer.h> 66 67 struct lpcib_softc { 68 /* Device object. */ 69 struct device sc_dev; 70 71 pci_chipset_tag_t sc_pc; 72 pcitag_t sc_pcitag; 73 struct pci_attach_args sc_pa; 74 75 /* Watchdog variables. */ 76 struct sysmon_wdog sc_smw; 77 bus_space_tag_t sc_iot; 78 bus_space_handle_t sc_ioh; 79 80 /* Power management */ 81 void *sc_powerhook; 82 struct pci_conf_state sc_pciconf; 83 pcireg_t sc_pirq[8]; 84 }; 85 86 static int lpcibmatch(struct device *, struct cfdata *, void *); 87 static void lpcibattach(struct device *, struct device *, void *); 88 static void lpcib_powerhook(int, void *); 89 90 static void pmtimer_configure(struct lpcib_softc *); 91 92 static void tcotimer_configure(struct lpcib_softc *); 93 static int tcotimer_setmode(struct sysmon_wdog *); 94 static int tcotimer_tickle(struct sysmon_wdog *); 95 static void tcotimer_stop(struct lpcib_softc *); 96 static void tcotimer_start(struct lpcib_softc *); 97 static void tcotimer_status_reset(struct lpcib_softc *); 98 static int tcotimer_disable_noreboot(struct lpcib_softc *, bus_space_tag_t, 99 bus_space_handle_t); 100 101 static void speedstep_configure(struct lpcib_softc *); 102 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 103 104 struct lpcib_softc *speedstep_cookie; /* XXX */ 105 static int lpcib_ich6 = 0; 106 107 /* Defined in arch/.../pci/pcib.c. */ 108 extern void pcibattach(struct device *, struct device *, void *); 109 110 CFATTACH_DECL(ichlpcib, sizeof(struct lpcib_softc), 111 lpcibmatch, lpcibattach, NULL, NULL); 112 113 /* 114 * Autoconf callbacks. 115 */ 116 static int 117 lpcibmatch(struct device *parent, struct cfdata *match, void *aux) 118 { 119 struct pci_attach_args *pa = aux; 120 121 /* We are ISA bridge, of course */ 122 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 123 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 124 return 0; 125 126 /* Matches only Intel ICH */ 127 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 128 switch (PCI_PRODUCT(pa->pa_id)) { 129 case PCI_PRODUCT_INTEL_82801AA_LPC: /* ICH */ 130 case PCI_PRODUCT_INTEL_82801AB_LPC: /* ICH0 */ 131 case PCI_PRODUCT_INTEL_82801BA_LPC: /* ICH2 */ 132 case PCI_PRODUCT_INTEL_82801BAM_LPC: /* ICH2-M */ 133 case PCI_PRODUCT_INTEL_82801CA_LPC: /* ICH3-S */ 134 case PCI_PRODUCT_INTEL_82801CAM_LPC: /* ICH3-M */ 135 case PCI_PRODUCT_INTEL_82801DB_LPC: /* ICH4 */ 136 case PCI_PRODUCT_INTEL_82801DB_ISA: /* ICH4-M */ 137 case PCI_PRODUCT_INTEL_82801EB_LPC: /* ICH5 */ 138 return 10; 139 case PCI_PRODUCT_INTEL_82801FB_LPC: /* ICH6 */ 140 case PCI_PRODUCT_INTEL_82801FBM_LPC: /* ICH6-M */ 141 case PCI_PRODUCT_INTEL_82801G_LPC: /* ICH7 */ 142 case PCI_PRODUCT_INTEL_82801GBM_LPC: /* ICH7-M */ 143 case PCI_PRODUCT_INTEL_82801GHM_LPC: /* ICH7-M DH */ 144 case PCI_PRODUCT_INTEL_82801H_LPC: /* ICH8 */ 145 case PCI_PRODUCT_INTEL_82801HH_LPC: /* ICH8 DH */ 146 case PCI_PRODUCT_INTEL_82801HO_LPC: /* ICH8 DO */ 147 case PCI_PRODUCT_INTEL_82801HBM_LPC: /* iCH8-M */ 148 case PCI_PRODUCT_INTEL_82801IH_LPC: /* ICH9 */ 149 case PCI_PRODUCT_INTEL_82801IR_LPC: /* ICH9-R */ 150 case PCI_PRODUCT_INTEL_82801IB_LPC: /* ICH9 ? */ 151 lpcib_ich6 = 1; 152 return 10; /* prior to pcib */ 153 } 154 } 155 156 return 0; 157 } 158 159 static void 160 lpcibattach(struct device *parent, struct device *self, void *aux) 161 { 162 struct pci_attach_args *pa = aux; 163 struct lpcib_softc *sc = (void*) self; 164 165 sc->sc_pc = pa->pa_pc; 166 sc->sc_pcitag = pa->pa_tag; 167 sc->sc_pa = *pa; 168 169 pcibattach(parent, self, aux); 170 171 /* 172 * Part of our I/O registers are used as ACPI PM regs. 173 * Since our ACPI subsystem accesses the I/O space directly so far, 174 * we do not have to bother bus_space I/O map confliction. 175 */ 176 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 177 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 178 aprint_error("%s: can't map power management i/o space", 179 sc->sc_dev.dv_xname); 180 return; 181 } 182 183 /* Set up the power management timer. */ 184 pmtimer_configure(sc); 185 186 /* Set up the TCO (watchdog). */ 187 tcotimer_configure(sc); 188 189 /* Set up SpeedStep. */ 190 speedstep_configure(sc); 191 192 /* Install powerhook */ 193 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 194 lpcib_powerhook, sc); 195 if (sc->sc_powerhook == NULL) 196 aprint_error("%s: can't establish powerhook\n", 197 sc->sc_dev.dv_xname); 198 } 199 200 static void 201 lpcib_powerhook(int why, void *opaque) 202 { 203 struct lpcib_softc *sc; 204 pci_chipset_tag_t pc; 205 pcitag_t tag; 206 207 sc = (struct lpcib_softc *)opaque; 208 pc = sc->sc_pc; 209 tag = sc->sc_pcitag; 210 211 switch (why) { 212 case PWR_SUSPEND: 213 pci_conf_capture(pc, tag, &sc->sc_pciconf); 214 215 /* capture PIRQ routing control registers */ 216 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 217 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQB_ROUT); 218 sc->sc_pirq[2] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQC_ROUT); 219 sc->sc_pirq[3] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQD_ROUT); 220 sc->sc_pirq[4] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 221 sc->sc_pirq[5] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQF_ROUT); 222 sc->sc_pirq[6] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQG_ROUT); 223 sc->sc_pirq[7] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQH_ROUT); 224 225 break; 226 227 case PWR_RESUME: 228 pci_conf_restore(pc, tag, &sc->sc_pciconf); 229 230 /* restore PIRQ routing control registers */ 231 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 232 pci_conf_write(pc, tag, LPCIB_PCI_PIRQB_ROUT, sc->sc_pirq[1]); 233 pci_conf_write(pc, tag, LPCIB_PCI_PIRQC_ROUT, sc->sc_pirq[2]); 234 pci_conf_write(pc, tag, LPCIB_PCI_PIRQD_ROUT, sc->sc_pirq[3]); 235 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[4]); 236 pci_conf_write(pc, tag, LPCIB_PCI_PIRQF_ROUT, sc->sc_pirq[5]); 237 pci_conf_write(pc, tag, LPCIB_PCI_PIRQG_ROUT, sc->sc_pirq[6]); 238 pci_conf_write(pc, tag, LPCIB_PCI_PIRQH_ROUT, sc->sc_pirq[7]); 239 240 break; 241 } 242 } 243 244 /* 245 * Initialize the power management timer. 246 */ 247 static void 248 pmtimer_configure(struct lpcib_softc *sc) 249 { 250 pcireg_t control; 251 252 /* 253 * Check if power management I/O space is enabled and enable the ACPI_EN 254 * bit if it's disabled. 255 */ 256 control = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL); 257 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 258 control |= LPCIB_PCI_ACPI_CNTL_EN; 259 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL, 260 control); 261 } 262 263 /* Attach our PM timer with the generic acpipmtimer function */ 264 acpipmtimer_attach(&sc->sc_dev, sc->sc_iot, sc->sc_ioh, 265 LPCIB_PM1_TMR, 0); 266 } 267 268 /* 269 * Initialize the watchdog timer. 270 */ 271 static void 272 tcotimer_configure(struct lpcib_softc *sc) 273 { 274 bus_space_handle_t gcs_memh; 275 pcireg_t pcireg; 276 uint32_t ioreg; 277 unsigned int period; 278 279 /* 280 * Map the memory space necessary for GCS (General Control 281 * and Status Register). This is where the No Reboot (NR) bit 282 * lives on ICH6 and newer. 283 */ 284 if (lpcib_ich6) { 285 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_RCBA); 286 pcireg &= 0xffffc000; 287 if (bus_space_map(sc->sc_pa.pa_memt, pcireg + LPCIB_GCS_OFFSET, 288 LPCIB_GCS_SIZE, 0, &gcs_memh)) { 289 aprint_error("%s: can't map GCS memory space; " 290 "TCO timer disabled\n", sc->sc_dev.dv_xname); 291 return; 292 } 293 } 294 295 /* 296 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 297 * in the SMI_EN register is the last chance. 298 */ 299 if (tcotimer_disable_noreboot(sc, sc->sc_pa.pa_memt, gcs_memh)) { 300 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 301 ioreg |= LPCIB_SMI_EN_TCO_EN; 302 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 303 } 304 305 /* Reset the watchdog status registers. */ 306 tcotimer_status_reset(sc); 307 308 /* Explicitly stop the TCO timer. */ 309 tcotimer_stop(sc); 310 311 /* 312 * Register the driver with the sysmon watchdog framework. 313 */ 314 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 315 sc->sc_smw.smw_cookie = sc; 316 sc->sc_smw.smw_setmode = tcotimer_setmode; 317 sc->sc_smw.smw_tickle = tcotimer_tickle; 318 if (lpcib_ich6) 319 period = LPCIB_TCOTIMER2_MAX_TICK; 320 else 321 period = LPCIB_TCOTIMER_MAX_TICK; 322 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 323 324 if (sysmon_wdog_register(&sc->sc_smw)) { 325 aprint_error("%s: unable to register TCO timer" 326 "as a sysmon watchdog device.\n", 327 sc->sc_dev.dv_xname); 328 return; 329 } 330 331 aprint_verbose("%s: TCO (watchdog) timer configured.\n", 332 sc->sc_dev.dv_xname); 333 } 334 335 /* 336 * Sysmon watchdog callbacks. 337 */ 338 static int 339 tcotimer_setmode(struct sysmon_wdog *smw) 340 { 341 struct lpcib_softc *sc = smw->smw_cookie; 342 unsigned int period; 343 uint16_t ich6period = 0; 344 345 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 346 /* Stop the TCO timer. */ 347 tcotimer_stop(sc); 348 } else { 349 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 350 /* 351 * ICH5 or older are limited to 4s min and 39s max. 352 * ICH6 or newer are limited to 2s min and 613s max. 353 */ 354 if (!lpcib_ich6) { 355 if (period < LPCIB_TCOTIMER_MIN_TICK || 356 period > LPCIB_TCOTIMER_MAX_TICK) 357 return EINVAL; 358 } else { 359 if (period < LPCIB_TCOTIMER2_MIN_TICK || 360 period > LPCIB_TCOTIMER2_MAX_TICK) 361 return EINVAL; 362 } 363 364 /* Stop the TCO timer, */ 365 tcotimer_stop(sc); 366 367 /* set the timeout, */ 368 if (lpcib_ich6) { 369 /* ICH6 or newer */ 370 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 371 LPCIB_TCO_TMR2); 372 ich6period &= 0xfc00; 373 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 374 LPCIB_TCO_TMR2, ich6period | period); 375 } else { 376 /* ICH5 or older */ 377 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 378 LPCIB_TCO_TMR); 379 period &= 0xc0; 380 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 381 LPCIB_TCO_TMR, period); 382 } 383 384 /* and start/reload the timer. */ 385 tcotimer_start(sc); 386 tcotimer_tickle(smw); 387 } 388 389 return 0; 390 } 391 392 static int 393 tcotimer_tickle(struct sysmon_wdog *smw) 394 { 395 struct lpcib_softc *sc = smw->smw_cookie; 396 397 /* any value is allowed */ 398 if (!lpcib_ich6) 399 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 400 else 401 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 402 403 return 0; 404 } 405 406 static void 407 tcotimer_stop(struct lpcib_softc *sc) 408 { 409 uint16_t ioreg; 410 411 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 412 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 413 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 414 } 415 416 static void 417 tcotimer_start(struct lpcib_softc *sc) 418 { 419 uint16_t ioreg; 420 421 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 422 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 423 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 424 } 425 426 static void 427 tcotimer_status_reset(struct lpcib_softc *sc) 428 { 429 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 430 LPCIB_TCO1_STS_TIMEOUT); 431 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 432 LPCIB_TCO2_STS_BOOT_STS); 433 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 434 LPCIB_TCO2_STS_SECONDS_TO_STS); 435 } 436 437 /* 438 * Clear the No Reboot (NR) bit, this enables reboots when the timer 439 * reaches the timeout for the second time. 440 */ 441 static int 442 tcotimer_disable_noreboot(struct lpcib_softc *sc, bus_space_tag_t gcs_memt, 443 bus_space_handle_t gcs_memh) 444 { 445 pcireg_t pcireg; 446 uint16_t status = 0; 447 448 if (!lpcib_ich6) { 449 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 450 LPCIB_PCI_GEN_STA); 451 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 452 /* TCO timeout reset is disabled; try to enable it */ 453 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 454 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 455 LPCIB_PCI_GEN_STA, pcireg); 456 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 457 goto error; 458 } 459 } else { 460 status = bus_space_read_4(gcs_memt, gcs_memh, 0); 461 status &= ~LPCIB_GCS_NO_REBOOT; 462 bus_space_write_4(gcs_memt, gcs_memh, 0, status); 463 status = bus_space_read_4(gcs_memt, gcs_memh, 0); 464 bus_space_unmap(gcs_memt, gcs_memh, LPCIB_GCS_SIZE); 465 if (status & LPCIB_GCS_NO_REBOOT) 466 goto error; 467 } 468 469 return 0; 470 error: 471 aprint_error("%s: TCO timer reboot disabled by hardware; " 472 "hope SMBIOS properly handles it.\n", sc->sc_dev.dv_xname); 473 return EINVAL; 474 } 475 476 477 /* 478 * Intel ICH SpeedStep support. 479 */ 480 #define SS_READ(sc, reg) \ 481 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 482 #define SS_WRITE(sc, reg, val) \ 483 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 484 485 /* 486 * Linux driver says that SpeedStep on older chipsets cause 487 * lockups on Dell Inspiron 8000 and 8100. 488 */ 489 static int 490 speedstep_bad_hb_check(struct pci_attach_args *pa) 491 { 492 493 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 494 PCI_REVISION(pa->pa_class) < 5) 495 return 1; 496 497 return 0; 498 } 499 500 static void 501 speedstep_configure(struct lpcib_softc *sc) 502 { 503 const struct sysctlnode *node, *ssnode; 504 int rv; 505 506 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 507 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 508 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 509 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 510 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 511 uint8_t pmcon; 512 513 /* Enable SpeedStep if it isn't already enabled. */ 514 pmcon = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 515 LPCIB_PCI_GEN_PMCON_1); 516 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 517 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 518 LPCIB_PCI_GEN_PMCON_1, 519 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 520 521 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 522 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 523 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 524 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 525 goto err; 526 527 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 528 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 529 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 530 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 531 CTL_EOL)) != 0) 532 goto err; 533 534 /* XXX save the sc for IO tag/handle */ 535 speedstep_cookie = sc; 536 aprint_verbose("%s: SpeedStep enabled\n", sc->sc_dev.dv_xname); 537 } 538 539 return; 540 541 err: 542 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 543 } 544 545 /* 546 * get/set the SpeedStep state: 0 == low power, 1 == high power. 547 */ 548 static int 549 speedstep_sysctl_helper(SYSCTLFN_ARGS) 550 { 551 struct sysctlnode node; 552 struct lpcib_softc *sc = speedstep_cookie; 553 uint8_t state, state2; 554 int ostate, nstate, s, error = 0; 555 556 /* 557 * We do the dance with spl's to avoid being at high ipl during 558 * sysctl_lookup() which can both copyin and copyout. 559 */ 560 s = splserial(); 561 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 562 splx(s); 563 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 564 ostate = 1; 565 else 566 ostate = 0; 567 nstate = ostate; 568 569 node = *rnode; 570 node.sysctl_data = &nstate; 571 572 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 573 if (error || newp == NULL) 574 goto out; 575 576 /* Only two states are available */ 577 if (nstate != 0 && nstate != 1) { 578 error = EINVAL; 579 goto out; 580 } 581 582 s = splserial(); 583 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 584 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 585 ostate = 1; 586 else 587 ostate = 0; 588 589 if (ostate != nstate) { 590 uint8_t cntl; 591 592 if (nstate == 0) 593 state2 |= LPCIB_PM_SS_STATE_LOW; 594 else 595 state2 &= ~LPCIB_PM_SS_STATE_LOW; 596 597 /* 598 * Must disable bus master arbitration during the change. 599 */ 600 cntl = SS_READ(sc, LPCIB_PM_CTRL); 601 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 602 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 603 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 604 } 605 splx(s); 606 out: 607 return error; 608 } 609
Indexes created Wed Oct 01 18:09:54 GMT 2025