ichlpcib.c revision 1.4.6.4
1 /* $NetBSD: ichlpcib.c,v 1.4.6.4 2007/09/04 16:08:56 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 41 * 42 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 43 * some power management and monitoring functions. 44 * Currently we support the watchdog timer, SpeedStep (on some systems) 45 * and the power management timer. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.4.6.4 2007/09/04 16:08:56 joerg Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/sysctl.h> 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 #include <dev/ic/i82801lpcreg.h> 65 #include <dev/ic/acpipmtimer.h> 66 67 struct lpcib_softc { 68 /* Device object. */ 69 struct device sc_dev; 70 71 pci_chipset_tag_t sc_pc; 72 pcitag_t sc_pcitag; 73 struct pci_attach_args sc_pa; 74 75 /* Watchdog variables. */ 76 struct sysmon_wdog sc_smw; 77 bus_space_tag_t sc_iot; 78 bus_space_handle_t sc_ioh; 79 80 /* Power management */ 81 struct pci_conf_state sc_pciconf; 82 pcireg_t sc_pirq[8]; 83 pcireg_t sc_pmcon; 84 pcireg_t sc_fwhsel2; 85 }; 86 87 static int lpcibmatch(struct device *, struct cfdata *, void *); 88 static void lpcibattach(struct device *, struct device *, void *); 89 static pnp_status_t lpcib_power(device_t, pnp_request_t, void *); 90 91 static void pmtimer_configure(struct lpcib_softc *); 92 93 static void tcotimer_configure(struct lpcib_softc *); 94 static int tcotimer_setmode(struct sysmon_wdog *); 95 static int tcotimer_tickle(struct sysmon_wdog *); 96 static void tcotimer_stop(struct lpcib_softc *); 97 static void tcotimer_start(struct lpcib_softc *); 98 static void tcotimer_status_reset(struct lpcib_softc *); 99 static int tcotimer_disable_noreboot(struct lpcib_softc *, bus_space_tag_t, 100 bus_space_handle_t); 101 102 static void speedstep_configure(struct lpcib_softc *); 103 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 104 105 struct lpcib_softc *speedstep_cookie; /* XXX */ 106 static int lpcib_ich6 = 0; 107 108 /* Defined in arch/.../pci/pcib.c. */ 109 extern void pcibattach(struct device *, struct device *, void *); 110 111 CFATTACH_DECL(ichlpcib, sizeof(struct lpcib_softc), 112 lpcibmatch, lpcibattach, NULL, NULL); 113 114 /* 115 * Autoconf callbacks. 116 */ 117 static int 118 lpcibmatch(struct device *parent, struct cfdata *match, void *aux) 119 { 120 struct pci_attach_args *pa = aux; 121 122 /* We are ISA bridge, of course */ 123 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 124 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 125 return 0; 126 127 /* Matches only Intel ICH */ 128 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 129 switch (PCI_PRODUCT(pa->pa_id)) { 130 case PCI_PRODUCT_INTEL_82801AA_LPC: /* ICH */ 131 case PCI_PRODUCT_INTEL_82801AB_LPC: /* ICH0 */ 132 case PCI_PRODUCT_INTEL_82801BA_LPC: /* ICH2 */ 133 case PCI_PRODUCT_INTEL_82801BAM_LPC: /* ICH2-M */ 134 case PCI_PRODUCT_INTEL_82801CA_LPC: /* ICH3-S */ 135 case PCI_PRODUCT_INTEL_82801CAM_LPC: /* ICH3-M */ 136 case PCI_PRODUCT_INTEL_82801DB_LPC: /* ICH4 */ 137 case PCI_PRODUCT_INTEL_82801DB_ISA: /* ICH4-M */ 138 case PCI_PRODUCT_INTEL_82801EB_LPC: /* ICH5 */ 139 return 10; 140 case PCI_PRODUCT_INTEL_82801FB_LPC: /* ICH6 */ 141 case PCI_PRODUCT_INTEL_82801FBM_LPC: /* ICH6-M */ 142 case PCI_PRODUCT_INTEL_82801G_LPC: /* ICH7 */ 143 case PCI_PRODUCT_INTEL_82801GBM_LPC: /* ICH7-M */ 144 case PCI_PRODUCT_INTEL_82801GHM_LPC: /* ICH7-M DH */ 145 case PCI_PRODUCT_INTEL_82801H_LPC: /* ICH8 */ 146 case PCI_PRODUCT_INTEL_82801HH_LPC: /* ICH8 DH */ 147 case PCI_PRODUCT_INTEL_82801HO_LPC: /* ICH8 DO */ 148 case PCI_PRODUCT_INTEL_82801HBM_LPC: /* iCH8-M */ 149 case PCI_PRODUCT_INTEL_82801IH_LPC: /* ICH9 */ 150 case PCI_PRODUCT_INTEL_82801IR_LPC: /* ICH9-R */ 151 case PCI_PRODUCT_INTEL_82801IB_LPC: /* ICH9 ? */ 152 lpcib_ich6 = 1; 153 return 10; /* prior to pcib */ 154 } 155 } 156 157 return 0; 158 } 159 160 static void 161 lpcibattach(struct device *parent, struct device *self, void *aux) 162 { 163 struct pci_attach_args *pa = aux; 164 struct lpcib_softc *sc = (void*) self; 165 pnp_status_t status; 166 167 sc->sc_pc = pa->pa_pc; 168 sc->sc_pcitag = pa->pa_tag; 169 sc->sc_pa = *pa; 170 171 pcibattach(parent, self, aux); 172 173 /* 174 * Part of our I/O registers are used as ACPI PM regs. 175 * Since our ACPI subsystem accesses the I/O space directly so far, 176 * we do not have to bother bus_space I/O map confliction. 177 */ 178 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 179 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 180 aprint_error("%s: can't map power management i/o space", 181 sc->sc_dev.dv_xname); 182 return; 183 } 184 185 /* Set up the power management timer. */ 186 pmtimer_configure(sc); 187 188 /* Set up the TCO (watchdog). */ 189 tcotimer_configure(sc); 190 191 /* Set up SpeedStep. */ 192 speedstep_configure(sc); 193 194 /* Install power handler */ 195 status = pnp_register(self, lpcib_power); 196 if (status != PNP_STATUS_SUCCESS) 197 aprint_error("%s: couldn't establish power handler\n", 198 device_xname(self)); 199 } 200 201 static pnp_status_t 202 lpcib_power(device_t dv, pnp_request_t req, void *opaque) 203 { 204 struct lpcib_softc *sc; 205 pnp_state_t *state; 206 pnp_capabilities_t *caps; 207 pci_chipset_tag_t pc; 208 pcitag_t tag; 209 pcireg_t val; 210 int off; 211 212 sc = device_private(dv); 213 pc = sc->sc_pc; 214 tag = sc->sc_pcitag; 215 216 switch (req) { 217 case PNP_REQUEST_GET_CAPABILITIES: 218 caps = (pnp_capabilities_t *)opaque; 219 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &off, &val)) 220 caps->state = PNP_STATE_D0 | PNP_STATE_D3; 221 else 222 caps->state = pci_pnp_capabilities(val); 223 break; 224 case PNP_REQUEST_GET_STATE: 225 state = (pnp_state_t *)opaque; 226 if (pci_get_powerstate(pc, tag, &val) != 0) 227 *state = PNP_STATE_D0; 228 else 229 *state = pci_pnp_powerstate(val); 230 break; 231 case PNP_REQUEST_SET_STATE: 232 state = (pnp_state_t *)opaque; 233 234 switch (*state) { 235 case PNP_STATE_D3: 236 val = PCI_PMCSR_STATE_D3; 237 pci_conf_capture(pc, tag, &sc->sc_pciconf); 238 239 /* capture PIRQ routing control registers */ 240 sc->sc_pirq[0] = pci_conf_read(pc, tag, 241 LPCIB_PCI_PIRQA_ROUT); 242 sc->sc_pirq[1] = pci_conf_read(pc, tag, 243 LPCIB_PCI_PIRQB_ROUT); 244 sc->sc_pirq[2] = pci_conf_read(pc, tag, 245 LPCIB_PCI_PIRQC_ROUT); 246 sc->sc_pirq[3] = pci_conf_read(pc, tag, 247 LPCIB_PCI_PIRQD_ROUT); 248 sc->sc_pirq[4] = pci_conf_read(pc, tag, 249 LPCIB_PCI_PIRQE_ROUT); 250 sc->sc_pirq[5] = pci_conf_read(pc, tag, 251 LPCIB_PCI_PIRQF_ROUT); 252 sc->sc_pirq[6] = pci_conf_read(pc, tag, 253 LPCIB_PCI_PIRQG_ROUT); 254 sc->sc_pirq[7] = pci_conf_read(pc, tag, 255 LPCIB_PCI_PIRQH_ROUT); 256 257 sc->sc_pmcon = pci_conf_read(pc, tag, 258 LPCIB_PCI_GEN_PMCON_1); 259 sc->sc_fwhsel2 = pci_conf_read(pc, tag, 260 LPCIB_PCI_GEN_STA); 261 262 break; 263 case PNP_STATE_D0: 264 val = PCI_PMCSR_STATE_D0; 265 266 break; 267 default: 268 return PNP_STATUS_UNSUPPORTED; 269 } 270 271 (void)pci_set_powerstate(pc, tag, val); 272 273 if (*state != PNP_STATE_D0) 274 break; 275 276 pci_conf_restore(pc, tag, &sc->sc_pciconf); 277 278 /* restore PIRQ routing control registers */ 279 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, 280 sc->sc_pirq[0]); 281 pci_conf_write(pc, tag, LPCIB_PCI_PIRQB_ROUT, 282 sc->sc_pirq[1]); 283 pci_conf_write(pc, tag, LPCIB_PCI_PIRQC_ROUT, 284 sc->sc_pirq[2]); 285 pci_conf_write(pc, tag, LPCIB_PCI_PIRQD_ROUT, 286 sc->sc_pirq[3]); 287 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, 288 sc->sc_pirq[4]); 289 pci_conf_write(pc, tag, LPCIB_PCI_PIRQF_ROUT, 290 sc->sc_pirq[5]); 291 pci_conf_write(pc, tag, LPCIB_PCI_PIRQG_ROUT, 292 sc->sc_pirq[6]); 293 pci_conf_write(pc, tag, LPCIB_PCI_PIRQH_ROUT, 294 sc->sc_pirq[7]); 295 296 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 297 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 298 299 break; 300 default: 301 return PNP_STATUS_UNSUPPORTED; 302 } 303 304 return PNP_STATUS_SUCCESS; 305 } 306 307 /* 308 * Initialize the power management timer. 309 */ 310 static void 311 pmtimer_configure(struct lpcib_softc *sc) 312 { 313 pcireg_t control; 314 315 /* 316 * Check if power management I/O space is enabled and enable the ACPI_EN 317 * bit if it's disabled. 318 */ 319 control = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL); 320 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 321 control |= LPCIB_PCI_ACPI_CNTL_EN; 322 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL, 323 control); 324 } 325 326 /* Attach our PM timer with the generic acpipmtimer function */ 327 acpipmtimer_attach(&sc->sc_dev, sc->sc_iot, sc->sc_ioh, 328 LPCIB_PM1_TMR, 0); 329 } 330 331 /* 332 * Initialize the watchdog timer. 333 */ 334 static void 335 tcotimer_configure(struct lpcib_softc *sc) 336 { 337 bus_space_handle_t gcs_memh; 338 pcireg_t pcireg; 339 uint32_t ioreg; 340 unsigned int period; 341 342 /* 343 * Map the memory space necessary for GCS (General Control 344 * and Status Register). This is where the No Reboot (NR) bit 345 * lives on ICH6 and newer. 346 */ 347 if (lpcib_ich6) { 348 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_RCBA); 349 pcireg &= 0xffffc000; 350 if (bus_space_map(sc->sc_pa.pa_memt, pcireg + LPCIB_GCS_OFFSET, 351 LPCIB_GCS_SIZE, 0, &gcs_memh)) { 352 aprint_error("%s: can't map GCS memory space; " 353 "TCO timer disabled\n", sc->sc_dev.dv_xname); 354 return; 355 } 356 } 357 358 /* 359 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 360 * in the SMI_EN register is the last chance. 361 */ 362 if (tcotimer_disable_noreboot(sc, sc->sc_pa.pa_memt, gcs_memh)) { 363 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 364 ioreg |= LPCIB_SMI_EN_TCO_EN; 365 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 366 } 367 368 /* Reset the watchdog status registers. */ 369 tcotimer_status_reset(sc); 370 371 /* Explicitly stop the TCO timer. */ 372 tcotimer_stop(sc); 373 374 /* 375 * Register the driver with the sysmon watchdog framework. 376 */ 377 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 378 sc->sc_smw.smw_cookie = sc; 379 sc->sc_smw.smw_setmode = tcotimer_setmode; 380 sc->sc_smw.smw_tickle = tcotimer_tickle; 381 if (lpcib_ich6) 382 period = LPCIB_TCOTIMER2_MAX_TICK; 383 else 384 period = LPCIB_TCOTIMER_MAX_TICK; 385 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 386 387 if (sysmon_wdog_register(&sc->sc_smw)) { 388 aprint_error("%s: unable to register TCO timer" 389 "as a sysmon watchdog device.\n", 390 sc->sc_dev.dv_xname); 391 return; 392 } 393 394 aprint_verbose("%s: TCO (watchdog) timer configured.\n", 395 sc->sc_dev.dv_xname); 396 } 397 398 /* 399 * Sysmon watchdog callbacks. 400 */ 401 static int 402 tcotimer_setmode(struct sysmon_wdog *smw) 403 { 404 struct lpcib_softc *sc = smw->smw_cookie; 405 unsigned int period; 406 uint16_t ich6period = 0; 407 408 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 409 /* Stop the TCO timer. */ 410 tcotimer_stop(sc); 411 } else { 412 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 413 /* 414 * ICH5 or older are limited to 4s min and 39s max. 415 * ICH6 or newer are limited to 2s min and 613s max. 416 */ 417 if (!lpcib_ich6) { 418 if (period < LPCIB_TCOTIMER_MIN_TICK || 419 period > LPCIB_TCOTIMER_MAX_TICK) 420 return EINVAL; 421 } else { 422 if (period < LPCIB_TCOTIMER2_MIN_TICK || 423 period > LPCIB_TCOTIMER2_MAX_TICK) 424 return EINVAL; 425 } 426 427 /* Stop the TCO timer, */ 428 tcotimer_stop(sc); 429 430 /* set the timeout, */ 431 if (lpcib_ich6) { 432 /* ICH6 or newer */ 433 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 434 LPCIB_TCO_TMR2); 435 ich6period &= 0xfc00; 436 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 437 LPCIB_TCO_TMR2, ich6period | period); 438 } else { 439 /* ICH5 or older */ 440 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 441 LPCIB_TCO_TMR); 442 period &= 0xc0; 443 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 444 LPCIB_TCO_TMR, period); 445 } 446 447 /* and start/reload the timer. */ 448 tcotimer_start(sc); 449 tcotimer_tickle(smw); 450 } 451 452 return 0; 453 } 454 455 static int 456 tcotimer_tickle(struct sysmon_wdog *smw) 457 { 458 struct lpcib_softc *sc = smw->smw_cookie; 459 460 /* any value is allowed */ 461 if (!lpcib_ich6) 462 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 463 else 464 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 465 466 return 0; 467 } 468 469 static void 470 tcotimer_stop(struct lpcib_softc *sc) 471 { 472 uint16_t ioreg; 473 474 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 475 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 476 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 477 } 478 479 static void 480 tcotimer_start(struct lpcib_softc *sc) 481 { 482 uint16_t ioreg; 483 484 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 485 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 486 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 487 } 488 489 static void 490 tcotimer_status_reset(struct lpcib_softc *sc) 491 { 492 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 493 LPCIB_TCO1_STS_TIMEOUT); 494 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 495 LPCIB_TCO2_STS_BOOT_STS); 496 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 497 LPCIB_TCO2_STS_SECONDS_TO_STS); 498 } 499 500 /* 501 * Clear the No Reboot (NR) bit, this enables reboots when the timer 502 * reaches the timeout for the second time. 503 */ 504 static int 505 tcotimer_disable_noreboot(struct lpcib_softc *sc, bus_space_tag_t gcs_memt, 506 bus_space_handle_t gcs_memh) 507 { 508 pcireg_t pcireg; 509 uint16_t status = 0; 510 511 if (!lpcib_ich6) { 512 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 513 LPCIB_PCI_GEN_STA); 514 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 515 /* TCO timeout reset is disabled; try to enable it */ 516 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 517 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 518 LPCIB_PCI_GEN_STA, pcireg); 519 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 520 goto error; 521 } 522 } else { 523 status = bus_space_read_4(gcs_memt, gcs_memh, 0); 524 status &= ~LPCIB_GCS_NO_REBOOT; 525 bus_space_write_4(gcs_memt, gcs_memh, 0, status); 526 status = bus_space_read_4(gcs_memt, gcs_memh, 0); 527 bus_space_unmap(gcs_memt, gcs_memh, LPCIB_GCS_SIZE); 528 if (status & LPCIB_GCS_NO_REBOOT) 529 goto error; 530 } 531 532 return 0; 533 error: 534 aprint_error("%s: TCO timer reboot disabled by hardware; " 535 "hope SMBIOS properly handles it.\n", sc->sc_dev.dv_xname); 536 return EINVAL; 537 } 538 539 540 /* 541 * Intel ICH SpeedStep support. 542 */ 543 #define SS_READ(sc, reg) \ 544 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 545 #define SS_WRITE(sc, reg, val) \ 546 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 547 548 /* 549 * Linux driver says that SpeedStep on older chipsets cause 550 * lockups on Dell Inspiron 8000 and 8100. 551 */ 552 static int 553 speedstep_bad_hb_check(struct pci_attach_args *pa) 554 { 555 556 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 557 PCI_REVISION(pa->pa_class) < 5) 558 return 1; 559 560 return 0; 561 } 562 563 static void 564 speedstep_configure(struct lpcib_softc *sc) 565 { 566 const struct sysctlnode *node, *ssnode; 567 int rv; 568 569 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 570 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 571 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 572 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 573 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 574 uint8_t pmcon; 575 576 /* Enable SpeedStep if it isn't already enabled. */ 577 pmcon = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 578 LPCIB_PCI_GEN_PMCON_1); 579 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 580 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 581 LPCIB_PCI_GEN_PMCON_1, 582 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 583 584 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 585 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 586 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 587 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 588 goto err; 589 590 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 591 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 592 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 593 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 594 CTL_EOL)) != 0) 595 goto err; 596 597 /* XXX save the sc for IO tag/handle */ 598 speedstep_cookie = sc; 599 aprint_verbose("%s: SpeedStep enabled\n", sc->sc_dev.dv_xname); 600 } 601 602 return; 603 604 err: 605 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 606 } 607 608 /* 609 * get/set the SpeedStep state: 0 == low power, 1 == high power. 610 */ 611 static int 612 speedstep_sysctl_helper(SYSCTLFN_ARGS) 613 { 614 struct sysctlnode node; 615 struct lpcib_softc *sc = speedstep_cookie; 616 uint8_t state, state2; 617 int ostate, nstate, s, error = 0; 618 619 /* 620 * We do the dance with spl's to avoid being at high ipl during 621 * sysctl_lookup() which can both copyin and copyout. 622 */ 623 s = splserial(); 624 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 625 splx(s); 626 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 627 ostate = 1; 628 else 629 ostate = 0; 630 nstate = ostate; 631 632 node = *rnode; 633 node.sysctl_data = &nstate; 634 635 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 636 if (error || newp == NULL) 637 goto out; 638 639 /* Only two states are available */ 640 if (nstate != 0 && nstate != 1) { 641 error = EINVAL; 642 goto out; 643 } 644 645 s = splserial(); 646 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 647 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 648 ostate = 1; 649 else 650 ostate = 0; 651 652 if (ostate != nstate) { 653 uint8_t cntl; 654 655 if (nstate == 0) 656 state2 |= LPCIB_PM_SS_STATE_LOW; 657 else 658 state2 &= ~LPCIB_PM_SS_STATE_LOW; 659 660 /* 661 * Must disable bus master arbitration during the change. 662 */ 663 cntl = SS_READ(sc, LPCIB_PM_CTRL); 664 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 665 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 666 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 667 } 668 splx(s); 669 out: 670 return error; 671 } 672
Indexes created Wed Oct 01 18:09:54 GMT 2025