ichlpcib.c revision 1.40
1 /* $NetBSD: ichlpcib.c,v 1.40 2013/09/17 01:16:45 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.40 2013/09/17 01:16:45 jakllsch Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 264 265 { 0, 0, 0, 0 }, 266 }; 267 268 /* 269 * Autoconf callbacks. 270 */ 271 static int 272 lpcibmatch(device_t parent, cfdata_t match, void *aux) 273 { 274 struct pci_attach_args *pa = aux; 275 struct lpcib_device *lpcib_dev; 276 277 /* We are ISA bridge, of course */ 278 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 279 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 280 return 0; 281 282 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 283 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 284 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 285 return 10; 286 } 287 288 return 0; 289 } 290 291 static void 292 lpcibattach(device_t parent, device_t self, void *aux) 293 { 294 struct pci_attach_args *pa = aux; 295 struct lpcib_softc *sc = device_private(self); 296 struct lpcib_device *lpcib_dev; 297 298 sc->sc_pa = *pa; 299 300 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 301 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 302 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 303 continue; 304 sc->sc_has_rcba = lpcib_dev->has_rcba; 305 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 306 break; 307 } 308 309 pcibattach(parent, self, aux); 310 311 /* 312 * Part of our I/O registers are used as ACPI PM regs. 313 * Since our ACPI subsystem accesses the I/O space directly so far, 314 * we do not have to bother bus_space I/O map confliction. 315 */ 316 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 317 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 318 aprint_error_dev(self, "can't map power management i/o space\n"); 319 return; 320 } 321 322 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 323 LPCIB_PCI_GEN_PMCON_1); 324 325 /* For ICH6 and later, always enable RCBA */ 326 if (sc->sc_has_rcba) { 327 pcireg_t rcba; 328 329 sc->sc_rcbat = sc->sc_pa.pa_memt; 330 331 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 332 LPCIB_RCBA); 333 if ((rcba & LPCIB_RCBA_EN) == 0) { 334 aprint_error_dev(self, "RCBA is not enabled\n"); 335 return; 336 } 337 rcba &= ~LPCIB_RCBA_EN; 338 339 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 340 &sc->sc_rcbah)) { 341 aprint_error_dev(self, "RCBA could not be mapped\n"); 342 return; 343 } 344 } 345 346 /* Set up the power management timer. */ 347 pmtimer_configure(self); 348 349 /* Set up the TCO (watchdog). */ 350 tcotimer_configure(self); 351 352 /* Set up SpeedStep. */ 353 speedstep_configure(self); 354 355 /* Set up HPET. */ 356 lpcib_hpet_configure(self); 357 358 #if NGPIO > 0 359 /* Set up GPIO */ 360 lpcib_gpio_configure(self); 361 #endif 362 363 #if NFWHRNG > 0 364 lpcib_fwh_configure(self); 365 #endif 366 367 /* Install power handler */ 368 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 369 lpcib_shutdown)) 370 aprint_error_dev(self, "couldn't establish power handler\n"); 371 } 372 373 static void 374 lpcibchilddet(device_t self, device_t child) 375 { 376 struct lpcib_softc *sc = device_private(self); 377 uint32_t val; 378 379 #if NFWHRNG > 0 380 if (sc->sc_fwhbus == child) { 381 sc->sc_fwhbus = NULL; 382 return; 383 } 384 #endif 385 #if NGPIO > 0 386 if (sc->sc_gpiobus == child) { 387 sc->sc_gpiobus = NULL; 388 return; 389 } 390 #endif 391 if (sc->sc_hpetbus != child) { 392 pcibchilddet(self, child); 393 return; 394 } 395 sc->sc_hpetbus = NULL; 396 if (sc->sc_has_ich5_hpet) { 397 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 398 LPCIB_PCI_GEN_CNTL); 399 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 400 case LPCIB_ICH5_HPTC_0000: 401 case LPCIB_ICH5_HPTC_1000: 402 case LPCIB_ICH5_HPTC_2000: 403 case LPCIB_ICH5_HPTC_3000: 404 break; 405 default: 406 return; 407 } 408 val &= ~LPCIB_ICH5_HPTC_EN; 409 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 410 LPCIB_PCI_GEN_CNTL, val); 411 } else if (sc->sc_has_rcba) { 412 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 413 LPCIB_RCBA_HPTC); 414 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 415 case LPCIB_RCBA_HPTC_0000: 416 case LPCIB_RCBA_HPTC_1000: 417 case LPCIB_RCBA_HPTC_2000: 418 case LPCIB_RCBA_HPTC_3000: 419 break; 420 default: 421 return; 422 } 423 val &= ~LPCIB_RCBA_HPTC_EN; 424 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 425 val); 426 } 427 } 428 429 static int 430 lpcibrescan(device_t self, const char *ifattr, const int *locators) 431 { 432 struct lpcib_softc *sc = device_private(self); 433 434 #if NFWHRNG > 0 435 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 436 lpcib_fwh_configure(self); 437 #endif 438 439 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 440 lpcib_hpet_configure(self); 441 442 #if NGPIO > 0 443 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 444 lpcib_gpio_configure(self); 445 #endif 446 447 return pcibrescan(self, ifattr, locators); 448 } 449 450 static int 451 lpcibdetach(device_t self, int flags) 452 { 453 struct lpcib_softc *sc = device_private(self); 454 int rc; 455 456 pmf_device_deregister(self); 457 458 #if NFWHRNG > 0 459 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 460 return rc; 461 #endif 462 463 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 464 return rc; 465 466 #if NGPIO > 0 467 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 468 return rc; 469 #endif 470 471 /* Set up SpeedStep. */ 472 speedstep_unconfigure(self); 473 474 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 475 return rc; 476 477 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 478 return rc; 479 480 if (sc->sc_has_rcba) 481 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 482 483 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 484 485 return pcibdetach(self, flags); 486 } 487 488 static bool 489 lpcib_shutdown(device_t dv, int howto) 490 { 491 struct lpcib_softc *sc = device_private(dv); 492 493 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 494 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 495 496 return true; 497 } 498 499 static bool 500 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 501 { 502 struct lpcib_softc *sc = device_private(dv); 503 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 504 pcitag_t tag = sc->sc_pcib.sc_tag; 505 506 /* capture PIRQ routing control registers */ 507 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 508 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 509 510 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 511 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 512 513 if (sc->sc_has_rcba) { 514 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 515 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 516 LPCIB_RCBA_HPTC); 517 } else if (sc->sc_has_ich5_hpet) { 518 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 519 } 520 521 return true; 522 } 523 524 static bool 525 lpcib_resume(device_t dv, const pmf_qual_t *qual) 526 { 527 struct lpcib_softc *sc = device_private(dv); 528 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 529 pcitag_t tag = sc->sc_pcib.sc_tag; 530 531 /* restore PIRQ routing control registers */ 532 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 533 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 534 535 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 536 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 537 538 if (sc->sc_has_rcba) { 539 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 540 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 541 sc->sc_hpet_reg); 542 } else if (sc->sc_has_ich5_hpet) { 543 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 544 } 545 546 return true; 547 } 548 549 /* 550 * Initialize the power management timer. 551 */ 552 static void 553 pmtimer_configure(device_t self) 554 { 555 struct lpcib_softc *sc = device_private(self); 556 pcireg_t control; 557 558 /* 559 * Check if power management I/O space is enabled and enable the ACPI_EN 560 * bit if it's disabled. 561 */ 562 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 563 LPCIB_PCI_ACPI_CNTL); 564 sc->sc_acpi_cntl = control; 565 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 566 control |= LPCIB_PCI_ACPI_CNTL_EN; 567 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 568 LPCIB_PCI_ACPI_CNTL, control); 569 } 570 571 /* Attach our PM timer with the generic acpipmtimer function */ 572 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 573 LPCIB_PM1_TMR, 0); 574 } 575 576 static int 577 pmtimer_unconfigure(device_t self, int flags) 578 { 579 struct lpcib_softc *sc = device_private(self); 580 int rc; 581 582 if (sc->sc_pmtimer != NULL && 583 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 584 return rc; 585 586 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 587 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 588 589 return 0; 590 } 591 592 /* 593 * Initialize the watchdog timer. 594 */ 595 static void 596 tcotimer_configure(device_t self) 597 { 598 struct lpcib_softc *sc = device_private(self); 599 uint32_t ioreg; 600 unsigned int period; 601 602 /* Explicitly stop the TCO timer. */ 603 tcotimer_stop(sc); 604 605 /* 606 * Enable TCO timeout SMI only if the hardware reset does not 607 * work. We don't know what the SMBIOS does. 608 */ 609 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 610 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 611 612 /* 613 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 614 * in the SMI_EN register is the last chance. 615 */ 616 if (tcotimer_disable_noreboot(self)) { 617 ioreg |= LPCIB_SMI_EN_TCO_EN; 618 } 619 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 620 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 621 } 622 623 /* Reset the watchdog status registers. */ 624 tcotimer_status_reset(sc); 625 626 /* 627 * Register the driver with the sysmon watchdog framework. 628 */ 629 sc->sc_smw.smw_name = device_xname(self); 630 sc->sc_smw.smw_cookie = sc; 631 sc->sc_smw.smw_setmode = tcotimer_setmode; 632 sc->sc_smw.smw_tickle = tcotimer_tickle; 633 if (sc->sc_has_rcba) 634 period = LPCIB_TCOTIMER2_MAX_TICK; 635 else 636 period = LPCIB_TCOTIMER_MAX_TICK; 637 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 638 639 if (sysmon_wdog_register(&sc->sc_smw)) { 640 aprint_error_dev(self, "unable to register TCO timer" 641 "as a sysmon watchdog device.\n"); 642 return; 643 } 644 645 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 646 } 647 648 static int 649 tcotimer_unconfigure(device_t self, int flags) 650 { 651 struct lpcib_softc *sc = device_private(self); 652 int rc; 653 654 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 655 if (rc == ERESTART) 656 rc = EINTR; 657 return rc; 658 } 659 660 /* Explicitly stop the TCO timer. */ 661 tcotimer_stop(sc); 662 663 /* XXX Set No Reboot? */ 664 665 return 0; 666 } 667 668 669 /* 670 * Sysmon watchdog callbacks. 671 */ 672 static int 673 tcotimer_setmode(struct sysmon_wdog *smw) 674 { 675 struct lpcib_softc *sc = smw->smw_cookie; 676 unsigned int period; 677 uint16_t ich6period = 0; 678 uint8_t ich5period = 0; 679 680 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 681 /* Stop the TCO timer. */ 682 tcotimer_stop(sc); 683 } else { 684 /* 685 * ICH6 or newer are limited to 2s min and 613s max. 686 * ICH5 or older are limited to 4s min and 39s max. 687 */ 688 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 689 if (sc->sc_has_rcba) { 690 if (period < LPCIB_TCOTIMER2_MIN_TICK || 691 period > LPCIB_TCOTIMER2_MAX_TICK) 692 return EINVAL; 693 } else { 694 if (period < LPCIB_TCOTIMER_MIN_TICK || 695 period > LPCIB_TCOTIMER_MAX_TICK) 696 return EINVAL; 697 } 698 699 /* Stop the TCO timer, */ 700 tcotimer_stop(sc); 701 702 /* set the timeout, */ 703 if (sc->sc_has_rcba) { 704 /* ICH6 or newer */ 705 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 706 LPCIB_TCO_TMR2); 707 ich6period &= 0xfc00; 708 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 709 LPCIB_TCO_TMR2, ich6period | period); 710 } else { 711 /* ICH5 or older */ 712 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 713 LPCIB_TCO_TMR); 714 ich5period &= 0xc0; 715 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 716 LPCIB_TCO_TMR, ich5period | period); 717 } 718 719 /* and start/reload the timer. */ 720 tcotimer_start(sc); 721 tcotimer_tickle(smw); 722 } 723 724 return 0; 725 } 726 727 static int 728 tcotimer_tickle(struct sysmon_wdog *smw) 729 { 730 struct lpcib_softc *sc = smw->smw_cookie; 731 732 /* any value is allowed */ 733 if (sc->sc_has_rcba) 734 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 735 else 736 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 737 738 return 0; 739 } 740 741 static void 742 tcotimer_stop(struct lpcib_softc *sc) 743 { 744 uint16_t ioreg; 745 746 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 747 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 748 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 749 } 750 751 static void 752 tcotimer_start(struct lpcib_softc *sc) 753 { 754 uint16_t ioreg; 755 756 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 757 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 758 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 759 } 760 761 static void 762 tcotimer_status_reset(struct lpcib_softc *sc) 763 { 764 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 765 LPCIB_TCO1_STS_TIMEOUT); 766 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 767 LPCIB_TCO2_STS_BOOT_STS); 768 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 769 LPCIB_TCO2_STS_SECONDS_TO_STS); 770 } 771 772 /* 773 * Clear the No Reboot (NR) bit, this enables reboots when the timer 774 * reaches the timeout for the second time. 775 */ 776 static int 777 tcotimer_disable_noreboot(device_t self) 778 { 779 struct lpcib_softc *sc = device_private(self); 780 781 if (sc->sc_has_rcba) { 782 uint32_t status; 783 784 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 785 LPCIB_GCS_OFFSET); 786 status &= ~LPCIB_GCS_NO_REBOOT; 787 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 788 LPCIB_GCS_OFFSET, status); 789 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 790 LPCIB_GCS_OFFSET); 791 if (status & LPCIB_GCS_NO_REBOOT) 792 goto error; 793 } else { 794 pcireg_t pcireg; 795 796 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 797 LPCIB_PCI_GEN_STA); 798 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 799 /* TCO timeout reset is disabled; try to enable it */ 800 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 801 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 802 LPCIB_PCI_GEN_STA, pcireg); 803 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 804 goto error; 805 } 806 } 807 808 return 0; 809 error: 810 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 811 "hope SMBIOS properly handles it.\n"); 812 return EINVAL; 813 } 814 815 816 /* 817 * Intel ICH SpeedStep support. 818 */ 819 #define SS_READ(sc, reg) \ 820 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 821 #define SS_WRITE(sc, reg, val) \ 822 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 823 824 /* 825 * Linux driver says that SpeedStep on older chipsets cause 826 * lockups on Dell Inspiron 8000 and 8100. 827 * It should also not be enabled on systems with the 82855GM 828 * Hub, which typically have an EST-enabled CPU. 829 */ 830 static int 831 speedstep_bad_hb_check(const struct pci_attach_args *pa) 832 { 833 834 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 835 PCI_REVISION(pa->pa_class) < 5) 836 return 1; 837 838 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 839 return 1; 840 841 return 0; 842 } 843 844 static void 845 speedstep_configure(device_t self) 846 { 847 struct lpcib_softc *sc = device_private(self); 848 const struct sysctlnode *node, *ssnode; 849 int rv; 850 851 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 852 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 853 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 854 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 855 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 856 pcireg_t pmcon; 857 858 /* Enable SpeedStep if it isn't already enabled. */ 859 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 860 LPCIB_PCI_GEN_PMCON_1); 861 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 862 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 863 LPCIB_PCI_GEN_PMCON_1, 864 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 865 866 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 867 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 868 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 869 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 870 goto err; 871 872 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 873 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 874 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 875 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 876 CTL_EOL)) != 0) 877 goto err; 878 879 /* XXX save the sc for IO tag/handle */ 880 speedstep_cookie = sc; 881 aprint_verbose_dev(self, "SpeedStep enabled\n"); 882 } 883 884 return; 885 886 err: 887 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 888 } 889 890 static void 891 speedstep_unconfigure(device_t self) 892 { 893 struct lpcib_softc *sc = device_private(self); 894 895 sysctl_teardown(&sc->sc_log); 896 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 897 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 898 899 speedstep_cookie = NULL; 900 } 901 902 /* 903 * get/set the SpeedStep state: 0 == low power, 1 == high power. 904 */ 905 static int 906 speedstep_sysctl_helper(SYSCTLFN_ARGS) 907 { 908 struct sysctlnode node; 909 struct lpcib_softc *sc = speedstep_cookie; 910 uint8_t state, state2; 911 int ostate, nstate, s, error = 0; 912 913 /* 914 * We do the dance with spl's to avoid being at high ipl during 915 * sysctl_lookup() which can both copyin and copyout. 916 */ 917 s = splserial(); 918 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 919 splx(s); 920 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 921 ostate = 1; 922 else 923 ostate = 0; 924 nstate = ostate; 925 926 node = *rnode; 927 node.sysctl_data = &nstate; 928 929 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 930 if (error || newp == NULL) 931 goto out; 932 933 /* Only two states are available */ 934 if (nstate != 0 && nstate != 1) { 935 error = EINVAL; 936 goto out; 937 } 938 939 s = splserial(); 940 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 941 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 942 ostate = 1; 943 else 944 ostate = 0; 945 946 if (ostate != nstate) { 947 uint8_t cntl; 948 949 if (nstate == 0) 950 state2 |= LPCIB_PM_SS_STATE_LOW; 951 else 952 state2 &= ~LPCIB_PM_SS_STATE_LOW; 953 954 /* 955 * Must disable bus master arbitration during the change. 956 */ 957 cntl = SS_READ(sc, LPCIB_PM_CTRL); 958 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 959 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 960 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 961 } 962 splx(s); 963 out: 964 return error; 965 } 966 967 static void 968 lpcib_hpet_configure(device_t self) 969 { 970 struct lpcib_softc *sc = device_private(self); 971 struct lpcib_hpet_attach_args arg; 972 uint32_t hpet_reg, val; 973 974 if (sc->sc_has_ich5_hpet) { 975 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 976 LPCIB_PCI_GEN_CNTL); 977 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 978 case LPCIB_ICH5_HPTC_0000: 979 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 980 break; 981 case LPCIB_ICH5_HPTC_1000: 982 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 983 break; 984 case LPCIB_ICH5_HPTC_2000: 985 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 986 break; 987 case LPCIB_ICH5_HPTC_3000: 988 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 989 break; 990 default: 991 return; 992 } 993 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 994 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 995 LPCIB_PCI_GEN_CNTL, val); 996 } else if (sc->sc_has_rcba) { 997 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 998 LPCIB_RCBA_HPTC); 999 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 1000 case LPCIB_RCBA_HPTC_0000: 1001 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 1002 break; 1003 case LPCIB_RCBA_HPTC_1000: 1004 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 1005 break; 1006 case LPCIB_RCBA_HPTC_2000: 1007 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1008 break; 1009 case LPCIB_RCBA_HPTC_3000: 1010 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1011 break; 1012 default: 1013 return; 1014 } 1015 val |= LPCIB_RCBA_HPTC_EN; 1016 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1017 val); 1018 } else { 1019 /* No HPET here */ 1020 return; 1021 } 1022 1023 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1024 arg.hpet_reg = hpet_reg; 1025 1026 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1027 } 1028 1029 static int 1030 lpcib_hpet_unconfigure(device_t self, int flags) 1031 { 1032 struct lpcib_softc *sc = device_private(self); 1033 int rc; 1034 1035 if (sc->sc_hpetbus != NULL && 1036 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1037 return rc; 1038 1039 return 0; 1040 } 1041 1042 #if NGPIO > 0 1043 static void 1044 lpcib_gpio_configure(device_t self) 1045 { 1046 struct lpcib_softc *sc = device_private(self); 1047 struct gpiobus_attach_args gba; 1048 pcireg_t gpio_cntl; 1049 uint32_t use, io, bit; 1050 int pin, shift, base_reg, cntl_reg, reg; 1051 1052 /* this implies ICH >= 6, and thus different mapreg */ 1053 if (sc->sc_has_rcba) { 1054 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1055 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1056 } else { 1057 base_reg = LPCIB_PCI_GPIO_BASE; 1058 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1059 } 1060 1061 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1062 cntl_reg); 1063 1064 /* Is GPIO enabled? */ 1065 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1066 return; 1067 1068 if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1069 &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1070 NULL, &sc->sc_gpio_ios)) { 1071 aprint_error_dev(self, "can't map general purpose i/o space\n"); 1072 return; 1073 } 1074 1075 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1076 1077 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1078 sc->sc_gpio_pins[pin].pin_num = pin; 1079 1080 /* Read initial state */ 1081 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1082 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1083 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1084 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1085 shift = pin % 32; 1086 bit = __BIT(shift); 1087 1088 if ((use & bit) != 0) { 1089 sc->sc_gpio_pins[pin].pin_caps = 1090 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1091 if (pin < 32) 1092 sc->sc_gpio_pins[pin].pin_caps |= 1093 GPIO_PIN_PULSATE; 1094 if ((io & bit) != 0) 1095 sc->sc_gpio_pins[pin].pin_flags = 1096 GPIO_PIN_INPUT; 1097 else 1098 sc->sc_gpio_pins[pin].pin_flags = 1099 GPIO_PIN_OUTPUT; 1100 } else 1101 sc->sc_gpio_pins[pin].pin_caps = 0; 1102 1103 if (lpcib_gpio_pin_read(sc, pin) == 0) 1104 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1105 else 1106 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1107 1108 } 1109 1110 /* Create controller tag */ 1111 sc->sc_gpio_gc.gp_cookie = sc; 1112 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1113 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1114 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1115 1116 memset(&gba, 0, sizeof(gba)); 1117 1118 gba.gba_gc = &sc->sc_gpio_gc; 1119 gba.gba_pins = sc->sc_gpio_pins; 1120 gba.gba_npins = LPCIB_GPIO_NPINS; 1121 1122 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1123 } 1124 1125 static int 1126 lpcib_gpio_unconfigure(device_t self, int flags) 1127 { 1128 struct lpcib_softc *sc = device_private(self); 1129 int rc; 1130 1131 if (sc->sc_gpiobus != NULL && 1132 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1133 return rc; 1134 1135 mutex_destroy(&sc->sc_gpio_mtx); 1136 1137 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1138 1139 return 0; 1140 } 1141 1142 static int 1143 lpcib_gpio_pin_read(void *arg, int pin) 1144 { 1145 struct lpcib_softc *sc = arg; 1146 uint32_t data; 1147 int reg, shift; 1148 1149 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1150 shift = pin % 32; 1151 1152 mutex_enter(&sc->sc_gpio_mtx); 1153 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1154 mutex_exit(&sc->sc_gpio_mtx); 1155 1156 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1157 } 1158 1159 static void 1160 lpcib_gpio_pin_write(void *arg, int pin, int value) 1161 { 1162 struct lpcib_softc *sc = arg; 1163 uint32_t data; 1164 int reg, shift; 1165 1166 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1167 shift = pin % 32; 1168 1169 mutex_enter(&sc->sc_gpio_mtx); 1170 1171 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1172 1173 if(value) 1174 data |= __BIT(shift); 1175 else 1176 data &= ~__BIT(shift); 1177 1178 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1179 1180 mutex_exit(&sc->sc_gpio_mtx); 1181 } 1182 1183 static void 1184 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1185 { 1186 struct lpcib_softc *sc = arg; 1187 uint32_t data; 1188 int reg, shift; 1189 1190 shift = pin % 32; 1191 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1192 1193 mutex_enter(&sc->sc_gpio_mtx); 1194 1195 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1196 1197 if (flags & GPIO_PIN_OUTPUT) 1198 data &= ~__BIT(shift); 1199 1200 if (flags & GPIO_PIN_INPUT) 1201 data |= __BIT(shift); 1202 1203 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1204 1205 1206 if (pin < 32) { 1207 reg = LPCIB_GPIO_GPO_BLINK; 1208 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1209 1210 if (flags & GPIO_PIN_PULSATE) 1211 data |= __BIT(shift); 1212 else 1213 data &= ~__BIT(shift); 1214 1215 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1216 } 1217 1218 mutex_exit(&sc->sc_gpio_mtx); 1219 } 1220 #endif 1221 1222 #if NFWHRNG > 0 1223 static void 1224 lpcib_fwh_configure(device_t self) 1225 { 1226 struct lpcib_softc *sc; 1227 pcireg_t pr; 1228 1229 sc = device_private(self); 1230 1231 if (sc->sc_has_rcba) { 1232 /* 1233 * Very unlikely to find a 82802 on a ICH6 or newer. 1234 * Also the write enable register moved at that point. 1235 */ 1236 return; 1237 } else { 1238 /* Enable FWH write to identify FWH. */ 1239 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1240 LPCIB_PCI_BIOS_CNTL); 1241 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1242 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1243 } 1244 1245 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1246 1247 /* restore previous write enable setting */ 1248 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1249 LPCIB_PCI_BIOS_CNTL, pr); 1250 } 1251 1252 static int 1253 lpcib_fwh_unconfigure(device_t self, int flags) 1254 { 1255 struct lpcib_softc *sc = device_private(self); 1256 int rc; 1257 1258 if (sc->sc_fwhbus != NULL && 1259 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1260 return rc; 1261 1262 return 0; 1263 } 1264 #endif 1265
Indexes created Tue Sep 30 17:09:57 GMT 2025