ichlpcib.c revision 1.41
1 /* $NetBSD: ichlpcib.c,v 1.41 2014/01/03 23:18:48 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.41 2014/01/03 23:18:48 msaitoh Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 264 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 268 269 { 0, 0, 0, 0 }, 270 }; 271 272 /* 273 * Autoconf callbacks. 274 */ 275 static int 276 lpcibmatch(device_t parent, cfdata_t match, void *aux) 277 { 278 struct pci_attach_args *pa = aux; 279 struct lpcib_device *lpcib_dev; 280 281 /* We are ISA bridge, of course */ 282 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 283 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 284 return 0; 285 286 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 287 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 288 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 289 return 10; 290 } 291 292 return 0; 293 } 294 295 static void 296 lpcibattach(device_t parent, device_t self, void *aux) 297 { 298 struct pci_attach_args *pa = aux; 299 struct lpcib_softc *sc = device_private(self); 300 struct lpcib_device *lpcib_dev; 301 302 sc->sc_pa = *pa; 303 304 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 305 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 306 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 307 continue; 308 sc->sc_has_rcba = lpcib_dev->has_rcba; 309 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 310 break; 311 } 312 313 pcibattach(parent, self, aux); 314 315 /* 316 * Part of our I/O registers are used as ACPI PM regs. 317 * Since our ACPI subsystem accesses the I/O space directly so far, 318 * we do not have to bother bus_space I/O map confliction. 319 */ 320 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 321 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 322 aprint_error_dev(self, "can't map power management i/o space\n"); 323 return; 324 } 325 326 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 327 LPCIB_PCI_GEN_PMCON_1); 328 329 /* For ICH6 and later, always enable RCBA */ 330 if (sc->sc_has_rcba) { 331 pcireg_t rcba; 332 333 sc->sc_rcbat = sc->sc_pa.pa_memt; 334 335 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 336 LPCIB_RCBA); 337 if ((rcba & LPCIB_RCBA_EN) == 0) { 338 aprint_error_dev(self, "RCBA is not enabled\n"); 339 return; 340 } 341 rcba &= ~LPCIB_RCBA_EN; 342 343 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 344 &sc->sc_rcbah)) { 345 aprint_error_dev(self, "RCBA could not be mapped\n"); 346 return; 347 } 348 } 349 350 /* Set up the power management timer. */ 351 pmtimer_configure(self); 352 353 /* Set up the TCO (watchdog). */ 354 tcotimer_configure(self); 355 356 /* Set up SpeedStep. */ 357 speedstep_configure(self); 358 359 /* Set up HPET. */ 360 lpcib_hpet_configure(self); 361 362 #if NGPIO > 0 363 /* Set up GPIO */ 364 lpcib_gpio_configure(self); 365 #endif 366 367 #if NFWHRNG > 0 368 lpcib_fwh_configure(self); 369 #endif 370 371 /* Install power handler */ 372 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 373 lpcib_shutdown)) 374 aprint_error_dev(self, "couldn't establish power handler\n"); 375 } 376 377 static void 378 lpcibchilddet(device_t self, device_t child) 379 { 380 struct lpcib_softc *sc = device_private(self); 381 uint32_t val; 382 383 #if NFWHRNG > 0 384 if (sc->sc_fwhbus == child) { 385 sc->sc_fwhbus = NULL; 386 return; 387 } 388 #endif 389 #if NGPIO > 0 390 if (sc->sc_gpiobus == child) { 391 sc->sc_gpiobus = NULL; 392 return; 393 } 394 #endif 395 if (sc->sc_hpetbus != child) { 396 pcibchilddet(self, child); 397 return; 398 } 399 sc->sc_hpetbus = NULL; 400 if (sc->sc_has_ich5_hpet) { 401 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 402 LPCIB_PCI_GEN_CNTL); 403 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 404 case LPCIB_ICH5_HPTC_0000: 405 case LPCIB_ICH5_HPTC_1000: 406 case LPCIB_ICH5_HPTC_2000: 407 case LPCIB_ICH5_HPTC_3000: 408 break; 409 default: 410 return; 411 } 412 val &= ~LPCIB_ICH5_HPTC_EN; 413 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 414 LPCIB_PCI_GEN_CNTL, val); 415 } else if (sc->sc_has_rcba) { 416 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 417 LPCIB_RCBA_HPTC); 418 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 419 case LPCIB_RCBA_HPTC_0000: 420 case LPCIB_RCBA_HPTC_1000: 421 case LPCIB_RCBA_HPTC_2000: 422 case LPCIB_RCBA_HPTC_3000: 423 break; 424 default: 425 return; 426 } 427 val &= ~LPCIB_RCBA_HPTC_EN; 428 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 429 val); 430 } 431 } 432 433 static int 434 lpcibrescan(device_t self, const char *ifattr, const int *locators) 435 { 436 struct lpcib_softc *sc = device_private(self); 437 438 #if NFWHRNG > 0 439 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 440 lpcib_fwh_configure(self); 441 #endif 442 443 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 444 lpcib_hpet_configure(self); 445 446 #if NGPIO > 0 447 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 448 lpcib_gpio_configure(self); 449 #endif 450 451 return pcibrescan(self, ifattr, locators); 452 } 453 454 static int 455 lpcibdetach(device_t self, int flags) 456 { 457 struct lpcib_softc *sc = device_private(self); 458 int rc; 459 460 pmf_device_deregister(self); 461 462 #if NFWHRNG > 0 463 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 464 return rc; 465 #endif 466 467 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 468 return rc; 469 470 #if NGPIO > 0 471 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 472 return rc; 473 #endif 474 475 /* Set up SpeedStep. */ 476 speedstep_unconfigure(self); 477 478 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 479 return rc; 480 481 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 482 return rc; 483 484 if (sc->sc_has_rcba) 485 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 486 487 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 488 489 return pcibdetach(self, flags); 490 } 491 492 static bool 493 lpcib_shutdown(device_t dv, int howto) 494 { 495 struct lpcib_softc *sc = device_private(dv); 496 497 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 498 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 499 500 return true; 501 } 502 503 static bool 504 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 505 { 506 struct lpcib_softc *sc = device_private(dv); 507 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 508 pcitag_t tag = sc->sc_pcib.sc_tag; 509 510 /* capture PIRQ routing control registers */ 511 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 512 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 513 514 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 515 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 516 517 if (sc->sc_has_rcba) { 518 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 519 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 520 LPCIB_RCBA_HPTC); 521 } else if (sc->sc_has_ich5_hpet) { 522 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 523 } 524 525 return true; 526 } 527 528 static bool 529 lpcib_resume(device_t dv, const pmf_qual_t *qual) 530 { 531 struct lpcib_softc *sc = device_private(dv); 532 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 533 pcitag_t tag = sc->sc_pcib.sc_tag; 534 535 /* restore PIRQ routing control registers */ 536 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 537 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 538 539 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 540 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 541 542 if (sc->sc_has_rcba) { 543 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 544 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 545 sc->sc_hpet_reg); 546 } else if (sc->sc_has_ich5_hpet) { 547 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 548 } 549 550 return true; 551 } 552 553 /* 554 * Initialize the power management timer. 555 */ 556 static void 557 pmtimer_configure(device_t self) 558 { 559 struct lpcib_softc *sc = device_private(self); 560 pcireg_t control; 561 562 /* 563 * Check if power management I/O space is enabled and enable the ACPI_EN 564 * bit if it's disabled. 565 */ 566 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 567 LPCIB_PCI_ACPI_CNTL); 568 sc->sc_acpi_cntl = control; 569 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 570 control |= LPCIB_PCI_ACPI_CNTL_EN; 571 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 572 LPCIB_PCI_ACPI_CNTL, control); 573 } 574 575 /* Attach our PM timer with the generic acpipmtimer function */ 576 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 577 LPCIB_PM1_TMR, 0); 578 } 579 580 static int 581 pmtimer_unconfigure(device_t self, int flags) 582 { 583 struct lpcib_softc *sc = device_private(self); 584 int rc; 585 586 if (sc->sc_pmtimer != NULL && 587 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 588 return rc; 589 590 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 591 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 592 593 return 0; 594 } 595 596 /* 597 * Initialize the watchdog timer. 598 */ 599 static void 600 tcotimer_configure(device_t self) 601 { 602 struct lpcib_softc *sc = device_private(self); 603 uint32_t ioreg; 604 unsigned int period; 605 606 /* Explicitly stop the TCO timer. */ 607 tcotimer_stop(sc); 608 609 /* 610 * Enable TCO timeout SMI only if the hardware reset does not 611 * work. We don't know what the SMBIOS does. 612 */ 613 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 614 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 615 616 /* 617 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 618 * in the SMI_EN register is the last chance. 619 */ 620 if (tcotimer_disable_noreboot(self)) { 621 ioreg |= LPCIB_SMI_EN_TCO_EN; 622 } 623 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 624 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 625 } 626 627 /* Reset the watchdog status registers. */ 628 tcotimer_status_reset(sc); 629 630 /* 631 * Register the driver with the sysmon watchdog framework. 632 */ 633 sc->sc_smw.smw_name = device_xname(self); 634 sc->sc_smw.smw_cookie = sc; 635 sc->sc_smw.smw_setmode = tcotimer_setmode; 636 sc->sc_smw.smw_tickle = tcotimer_tickle; 637 if (sc->sc_has_rcba) 638 period = LPCIB_TCOTIMER2_MAX_TICK; 639 else 640 period = LPCIB_TCOTIMER_MAX_TICK; 641 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 642 643 if (sysmon_wdog_register(&sc->sc_smw)) { 644 aprint_error_dev(self, "unable to register TCO timer" 645 "as a sysmon watchdog device.\n"); 646 return; 647 } 648 649 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 650 } 651 652 static int 653 tcotimer_unconfigure(device_t self, int flags) 654 { 655 struct lpcib_softc *sc = device_private(self); 656 int rc; 657 658 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 659 if (rc == ERESTART) 660 rc = EINTR; 661 return rc; 662 } 663 664 /* Explicitly stop the TCO timer. */ 665 tcotimer_stop(sc); 666 667 /* XXX Set No Reboot? */ 668 669 return 0; 670 } 671 672 673 /* 674 * Sysmon watchdog callbacks. 675 */ 676 static int 677 tcotimer_setmode(struct sysmon_wdog *smw) 678 { 679 struct lpcib_softc *sc = smw->smw_cookie; 680 unsigned int period; 681 uint16_t ich6period = 0; 682 uint8_t ich5period = 0; 683 684 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 685 /* Stop the TCO timer. */ 686 tcotimer_stop(sc); 687 } else { 688 /* 689 * ICH6 or newer are limited to 2s min and 613s max. 690 * ICH5 or older are limited to 4s min and 39s max. 691 */ 692 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 693 if (sc->sc_has_rcba) { 694 if (period < LPCIB_TCOTIMER2_MIN_TICK || 695 period > LPCIB_TCOTIMER2_MAX_TICK) 696 return EINVAL; 697 } else { 698 if (period < LPCIB_TCOTIMER_MIN_TICK || 699 period > LPCIB_TCOTIMER_MAX_TICK) 700 return EINVAL; 701 } 702 703 /* Stop the TCO timer, */ 704 tcotimer_stop(sc); 705 706 /* set the timeout, */ 707 if (sc->sc_has_rcba) { 708 /* ICH6 or newer */ 709 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 710 LPCIB_TCO_TMR2); 711 ich6period &= 0xfc00; 712 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 713 LPCIB_TCO_TMR2, ich6period | period); 714 } else { 715 /* ICH5 or older */ 716 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 717 LPCIB_TCO_TMR); 718 ich5period &= 0xc0; 719 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 720 LPCIB_TCO_TMR, ich5period | period); 721 } 722 723 /* and start/reload the timer. */ 724 tcotimer_start(sc); 725 tcotimer_tickle(smw); 726 } 727 728 return 0; 729 } 730 731 static int 732 tcotimer_tickle(struct sysmon_wdog *smw) 733 { 734 struct lpcib_softc *sc = smw->smw_cookie; 735 736 /* any value is allowed */ 737 if (sc->sc_has_rcba) 738 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 739 else 740 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 741 742 return 0; 743 } 744 745 static void 746 tcotimer_stop(struct lpcib_softc *sc) 747 { 748 uint16_t ioreg; 749 750 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 751 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 752 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 753 } 754 755 static void 756 tcotimer_start(struct lpcib_softc *sc) 757 { 758 uint16_t ioreg; 759 760 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 761 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 762 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 763 } 764 765 static void 766 tcotimer_status_reset(struct lpcib_softc *sc) 767 { 768 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 769 LPCIB_TCO1_STS_TIMEOUT); 770 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 771 LPCIB_TCO2_STS_BOOT_STS); 772 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 773 LPCIB_TCO2_STS_SECONDS_TO_STS); 774 } 775 776 /* 777 * Clear the No Reboot (NR) bit, this enables reboots when the timer 778 * reaches the timeout for the second time. 779 */ 780 static int 781 tcotimer_disable_noreboot(device_t self) 782 { 783 struct lpcib_softc *sc = device_private(self); 784 785 if (sc->sc_has_rcba) { 786 uint32_t status; 787 788 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 789 LPCIB_GCS_OFFSET); 790 status &= ~LPCIB_GCS_NO_REBOOT; 791 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 792 LPCIB_GCS_OFFSET, status); 793 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 794 LPCIB_GCS_OFFSET); 795 if (status & LPCIB_GCS_NO_REBOOT) 796 goto error; 797 } else { 798 pcireg_t pcireg; 799 800 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 801 LPCIB_PCI_GEN_STA); 802 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 803 /* TCO timeout reset is disabled; try to enable it */ 804 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 805 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 806 LPCIB_PCI_GEN_STA, pcireg); 807 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 808 goto error; 809 } 810 } 811 812 return 0; 813 error: 814 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 815 "hope SMBIOS properly handles it.\n"); 816 return EINVAL; 817 } 818 819 820 /* 821 * Intel ICH SpeedStep support. 822 */ 823 #define SS_READ(sc, reg) \ 824 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 825 #define SS_WRITE(sc, reg, val) \ 826 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 827 828 /* 829 * Linux driver says that SpeedStep on older chipsets cause 830 * lockups on Dell Inspiron 8000 and 8100. 831 * It should also not be enabled on systems with the 82855GM 832 * Hub, which typically have an EST-enabled CPU. 833 */ 834 static int 835 speedstep_bad_hb_check(const struct pci_attach_args *pa) 836 { 837 838 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 839 PCI_REVISION(pa->pa_class) < 5) 840 return 1; 841 842 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 843 return 1; 844 845 return 0; 846 } 847 848 static void 849 speedstep_configure(device_t self) 850 { 851 struct lpcib_softc *sc = device_private(self); 852 const struct sysctlnode *node, *ssnode; 853 int rv; 854 855 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 856 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 857 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 858 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 859 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 860 pcireg_t pmcon; 861 862 /* Enable SpeedStep if it isn't already enabled. */ 863 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 864 LPCIB_PCI_GEN_PMCON_1); 865 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 866 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 867 LPCIB_PCI_GEN_PMCON_1, 868 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 869 870 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 871 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 872 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 873 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 874 goto err; 875 876 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 877 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 878 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 879 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 880 CTL_EOL)) != 0) 881 goto err; 882 883 /* XXX save the sc for IO tag/handle */ 884 speedstep_cookie = sc; 885 aprint_verbose_dev(self, "SpeedStep enabled\n"); 886 } 887 888 return; 889 890 err: 891 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 892 } 893 894 static void 895 speedstep_unconfigure(device_t self) 896 { 897 struct lpcib_softc *sc = device_private(self); 898 899 sysctl_teardown(&sc->sc_log); 900 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 901 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 902 903 speedstep_cookie = NULL; 904 } 905 906 /* 907 * get/set the SpeedStep state: 0 == low power, 1 == high power. 908 */ 909 static int 910 speedstep_sysctl_helper(SYSCTLFN_ARGS) 911 { 912 struct sysctlnode node; 913 struct lpcib_softc *sc = speedstep_cookie; 914 uint8_t state, state2; 915 int ostate, nstate, s, error = 0; 916 917 /* 918 * We do the dance with spl's to avoid being at high ipl during 919 * sysctl_lookup() which can both copyin and copyout. 920 */ 921 s = splserial(); 922 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 923 splx(s); 924 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 925 ostate = 1; 926 else 927 ostate = 0; 928 nstate = ostate; 929 930 node = *rnode; 931 node.sysctl_data = &nstate; 932 933 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 934 if (error || newp == NULL) 935 goto out; 936 937 /* Only two states are available */ 938 if (nstate != 0 && nstate != 1) { 939 error = EINVAL; 940 goto out; 941 } 942 943 s = splserial(); 944 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 945 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 946 ostate = 1; 947 else 948 ostate = 0; 949 950 if (ostate != nstate) { 951 uint8_t cntl; 952 953 if (nstate == 0) 954 state2 |= LPCIB_PM_SS_STATE_LOW; 955 else 956 state2 &= ~LPCIB_PM_SS_STATE_LOW; 957 958 /* 959 * Must disable bus master arbitration during the change. 960 */ 961 cntl = SS_READ(sc, LPCIB_PM_CTRL); 962 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 963 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 964 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 965 } 966 splx(s); 967 out: 968 return error; 969 } 970 971 static void 972 lpcib_hpet_configure(device_t self) 973 { 974 struct lpcib_softc *sc = device_private(self); 975 struct lpcib_hpet_attach_args arg; 976 uint32_t hpet_reg, val; 977 978 if (sc->sc_has_ich5_hpet) { 979 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 980 LPCIB_PCI_GEN_CNTL); 981 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 982 case LPCIB_ICH5_HPTC_0000: 983 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 984 break; 985 case LPCIB_ICH5_HPTC_1000: 986 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 987 break; 988 case LPCIB_ICH5_HPTC_2000: 989 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 990 break; 991 case LPCIB_ICH5_HPTC_3000: 992 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 993 break; 994 default: 995 return; 996 } 997 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 998 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 999 LPCIB_PCI_GEN_CNTL, val); 1000 } else if (sc->sc_has_rcba) { 1001 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 1002 LPCIB_RCBA_HPTC); 1003 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 1004 case LPCIB_RCBA_HPTC_0000: 1005 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 1006 break; 1007 case LPCIB_RCBA_HPTC_1000: 1008 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 1009 break; 1010 case LPCIB_RCBA_HPTC_2000: 1011 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1012 break; 1013 case LPCIB_RCBA_HPTC_3000: 1014 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1015 break; 1016 default: 1017 return; 1018 } 1019 val |= LPCIB_RCBA_HPTC_EN; 1020 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1021 val); 1022 } else { 1023 /* No HPET here */ 1024 return; 1025 } 1026 1027 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1028 arg.hpet_reg = hpet_reg; 1029 1030 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1031 } 1032 1033 static int 1034 lpcib_hpet_unconfigure(device_t self, int flags) 1035 { 1036 struct lpcib_softc *sc = device_private(self); 1037 int rc; 1038 1039 if (sc->sc_hpetbus != NULL && 1040 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1041 return rc; 1042 1043 return 0; 1044 } 1045 1046 #if NGPIO > 0 1047 static void 1048 lpcib_gpio_configure(device_t self) 1049 { 1050 struct lpcib_softc *sc = device_private(self); 1051 struct gpiobus_attach_args gba; 1052 pcireg_t gpio_cntl; 1053 uint32_t use, io, bit; 1054 int pin, shift, base_reg, cntl_reg, reg; 1055 1056 /* this implies ICH >= 6, and thus different mapreg */ 1057 if (sc->sc_has_rcba) { 1058 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1059 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1060 } else { 1061 base_reg = LPCIB_PCI_GPIO_BASE; 1062 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1063 } 1064 1065 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1066 cntl_reg); 1067 1068 /* Is GPIO enabled? */ 1069 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1070 return; 1071 1072 if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1073 &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1074 NULL, &sc->sc_gpio_ios)) { 1075 aprint_error_dev(self, "can't map general purpose i/o space\n"); 1076 return; 1077 } 1078 1079 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1080 1081 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1082 sc->sc_gpio_pins[pin].pin_num = pin; 1083 1084 /* Read initial state */ 1085 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1086 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1087 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1088 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1089 shift = pin % 32; 1090 bit = __BIT(shift); 1091 1092 if ((use & bit) != 0) { 1093 sc->sc_gpio_pins[pin].pin_caps = 1094 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1095 if (pin < 32) 1096 sc->sc_gpio_pins[pin].pin_caps |= 1097 GPIO_PIN_PULSATE; 1098 if ((io & bit) != 0) 1099 sc->sc_gpio_pins[pin].pin_flags = 1100 GPIO_PIN_INPUT; 1101 else 1102 sc->sc_gpio_pins[pin].pin_flags = 1103 GPIO_PIN_OUTPUT; 1104 } else 1105 sc->sc_gpio_pins[pin].pin_caps = 0; 1106 1107 if (lpcib_gpio_pin_read(sc, pin) == 0) 1108 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1109 else 1110 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1111 1112 } 1113 1114 /* Create controller tag */ 1115 sc->sc_gpio_gc.gp_cookie = sc; 1116 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1117 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1118 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1119 1120 memset(&gba, 0, sizeof(gba)); 1121 1122 gba.gba_gc = &sc->sc_gpio_gc; 1123 gba.gba_pins = sc->sc_gpio_pins; 1124 gba.gba_npins = LPCIB_GPIO_NPINS; 1125 1126 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1127 } 1128 1129 static int 1130 lpcib_gpio_unconfigure(device_t self, int flags) 1131 { 1132 struct lpcib_softc *sc = device_private(self); 1133 int rc; 1134 1135 if (sc->sc_gpiobus != NULL && 1136 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1137 return rc; 1138 1139 mutex_destroy(&sc->sc_gpio_mtx); 1140 1141 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1142 1143 return 0; 1144 } 1145 1146 static int 1147 lpcib_gpio_pin_read(void *arg, int pin) 1148 { 1149 struct lpcib_softc *sc = arg; 1150 uint32_t data; 1151 int reg, shift; 1152 1153 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1154 shift = pin % 32; 1155 1156 mutex_enter(&sc->sc_gpio_mtx); 1157 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1158 mutex_exit(&sc->sc_gpio_mtx); 1159 1160 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1161 } 1162 1163 static void 1164 lpcib_gpio_pin_write(void *arg, int pin, int value) 1165 { 1166 struct lpcib_softc *sc = arg; 1167 uint32_t data; 1168 int reg, shift; 1169 1170 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1171 shift = pin % 32; 1172 1173 mutex_enter(&sc->sc_gpio_mtx); 1174 1175 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1176 1177 if(value) 1178 data |= __BIT(shift); 1179 else 1180 data &= ~__BIT(shift); 1181 1182 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1183 1184 mutex_exit(&sc->sc_gpio_mtx); 1185 } 1186 1187 static void 1188 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1189 { 1190 struct lpcib_softc *sc = arg; 1191 uint32_t data; 1192 int reg, shift; 1193 1194 shift = pin % 32; 1195 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1196 1197 mutex_enter(&sc->sc_gpio_mtx); 1198 1199 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1200 1201 if (flags & GPIO_PIN_OUTPUT) 1202 data &= ~__BIT(shift); 1203 1204 if (flags & GPIO_PIN_INPUT) 1205 data |= __BIT(shift); 1206 1207 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1208 1209 1210 if (pin < 32) { 1211 reg = LPCIB_GPIO_GPO_BLINK; 1212 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1213 1214 if (flags & GPIO_PIN_PULSATE) 1215 data |= __BIT(shift); 1216 else 1217 data &= ~__BIT(shift); 1218 1219 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1220 } 1221 1222 mutex_exit(&sc->sc_gpio_mtx); 1223 } 1224 #endif 1225 1226 #if NFWHRNG > 0 1227 static void 1228 lpcib_fwh_configure(device_t self) 1229 { 1230 struct lpcib_softc *sc; 1231 pcireg_t pr; 1232 1233 sc = device_private(self); 1234 1235 if (sc->sc_has_rcba) { 1236 /* 1237 * Very unlikely to find a 82802 on a ICH6 or newer. 1238 * Also the write enable register moved at that point. 1239 */ 1240 return; 1241 } else { 1242 /* Enable FWH write to identify FWH. */ 1243 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1244 LPCIB_PCI_BIOS_CNTL); 1245 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1246 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1247 } 1248 1249 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1250 1251 /* restore previous write enable setting */ 1252 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1253 LPCIB_PCI_BIOS_CNTL, pr); 1254 } 1255 1256 static int 1257 lpcib_fwh_unconfigure(device_t self, int flags) 1258 { 1259 struct lpcib_softc *sc = device_private(self); 1260 int rc; 1261 1262 if (sc->sc_fwhbus != NULL && 1263 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1264 return rc; 1265 1266 return 0; 1267 } 1268 #endif 1269
Indexes created Tue Sep 30 11:09:46 GMT 2025