ichlpcib.c revision 1.42
1 /* $NetBSD: ichlpcib.c,v 1.42 2014/01/04 02:09:12 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.42 2014/01/04 02:09:12 msaitoh Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 264 #if 0 265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 269 #endif 270 271 { 0, 0, 0, 0 }, 272 }; 273 274 /* 275 * Autoconf callbacks. 276 */ 277 static int 278 lpcibmatch(device_t parent, cfdata_t match, void *aux) 279 { 280 struct pci_attach_args *pa = aux; 281 struct lpcib_device *lpcib_dev; 282 283 /* We are ISA bridge, of course */ 284 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 285 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 286 return 0; 287 288 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 289 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 290 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 291 return 10; 292 } 293 294 return 0; 295 } 296 297 static void 298 lpcibattach(device_t parent, device_t self, void *aux) 299 { 300 struct pci_attach_args *pa = aux; 301 struct lpcib_softc *sc = device_private(self); 302 struct lpcib_device *lpcib_dev; 303 304 sc->sc_pa = *pa; 305 306 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 307 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 308 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 309 continue; 310 sc->sc_has_rcba = lpcib_dev->has_rcba; 311 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 312 break; 313 } 314 315 pcibattach(parent, self, aux); 316 317 /* 318 * Part of our I/O registers are used as ACPI PM regs. 319 * Since our ACPI subsystem accesses the I/O space directly so far, 320 * we do not have to bother bus_space I/O map confliction. 321 */ 322 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 323 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 324 aprint_error_dev(self, "can't map power management i/o space\n"); 325 return; 326 } 327 328 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 329 LPCIB_PCI_GEN_PMCON_1); 330 331 /* For ICH6 and later, always enable RCBA */ 332 if (sc->sc_has_rcba) { 333 pcireg_t rcba; 334 335 sc->sc_rcbat = sc->sc_pa.pa_memt; 336 337 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 338 LPCIB_RCBA); 339 if ((rcba & LPCIB_RCBA_EN) == 0) { 340 aprint_error_dev(self, "RCBA is not enabled\n"); 341 return; 342 } 343 rcba &= ~LPCIB_RCBA_EN; 344 345 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 346 &sc->sc_rcbah)) { 347 aprint_error_dev(self, "RCBA could not be mapped\n"); 348 return; 349 } 350 } 351 352 /* Set up the power management timer. */ 353 pmtimer_configure(self); 354 355 /* Set up the TCO (watchdog). */ 356 tcotimer_configure(self); 357 358 /* Set up SpeedStep. */ 359 speedstep_configure(self); 360 361 /* Set up HPET. */ 362 lpcib_hpet_configure(self); 363 364 #if NGPIO > 0 365 /* Set up GPIO */ 366 lpcib_gpio_configure(self); 367 #endif 368 369 #if NFWHRNG > 0 370 lpcib_fwh_configure(self); 371 #endif 372 373 /* Install power handler */ 374 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 375 lpcib_shutdown)) 376 aprint_error_dev(self, "couldn't establish power handler\n"); 377 } 378 379 static void 380 lpcibchilddet(device_t self, device_t child) 381 { 382 struct lpcib_softc *sc = device_private(self); 383 uint32_t val; 384 385 #if NFWHRNG > 0 386 if (sc->sc_fwhbus == child) { 387 sc->sc_fwhbus = NULL; 388 return; 389 } 390 #endif 391 #if NGPIO > 0 392 if (sc->sc_gpiobus == child) { 393 sc->sc_gpiobus = NULL; 394 return; 395 } 396 #endif 397 if (sc->sc_hpetbus != child) { 398 pcibchilddet(self, child); 399 return; 400 } 401 sc->sc_hpetbus = NULL; 402 if (sc->sc_has_ich5_hpet) { 403 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 404 LPCIB_PCI_GEN_CNTL); 405 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 406 case LPCIB_ICH5_HPTC_0000: 407 case LPCIB_ICH5_HPTC_1000: 408 case LPCIB_ICH5_HPTC_2000: 409 case LPCIB_ICH5_HPTC_3000: 410 break; 411 default: 412 return; 413 } 414 val &= ~LPCIB_ICH5_HPTC_EN; 415 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 416 LPCIB_PCI_GEN_CNTL, val); 417 } else if (sc->sc_has_rcba) { 418 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 419 LPCIB_RCBA_HPTC); 420 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 421 case LPCIB_RCBA_HPTC_0000: 422 case LPCIB_RCBA_HPTC_1000: 423 case LPCIB_RCBA_HPTC_2000: 424 case LPCIB_RCBA_HPTC_3000: 425 break; 426 default: 427 return; 428 } 429 val &= ~LPCIB_RCBA_HPTC_EN; 430 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 431 val); 432 } 433 } 434 435 static int 436 lpcibrescan(device_t self, const char *ifattr, const int *locators) 437 { 438 struct lpcib_softc *sc = device_private(self); 439 440 #if NFWHRNG > 0 441 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 442 lpcib_fwh_configure(self); 443 #endif 444 445 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 446 lpcib_hpet_configure(self); 447 448 #if NGPIO > 0 449 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 450 lpcib_gpio_configure(self); 451 #endif 452 453 return pcibrescan(self, ifattr, locators); 454 } 455 456 static int 457 lpcibdetach(device_t self, int flags) 458 { 459 struct lpcib_softc *sc = device_private(self); 460 int rc; 461 462 pmf_device_deregister(self); 463 464 #if NFWHRNG > 0 465 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 466 return rc; 467 #endif 468 469 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 470 return rc; 471 472 #if NGPIO > 0 473 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 474 return rc; 475 #endif 476 477 /* Set up SpeedStep. */ 478 speedstep_unconfigure(self); 479 480 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 481 return rc; 482 483 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 484 return rc; 485 486 if (sc->sc_has_rcba) 487 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 488 489 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 490 491 return pcibdetach(self, flags); 492 } 493 494 static bool 495 lpcib_shutdown(device_t dv, int howto) 496 { 497 struct lpcib_softc *sc = device_private(dv); 498 499 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 500 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 501 502 return true; 503 } 504 505 static bool 506 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 507 { 508 struct lpcib_softc *sc = device_private(dv); 509 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 510 pcitag_t tag = sc->sc_pcib.sc_tag; 511 512 /* capture PIRQ routing control registers */ 513 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 514 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 515 516 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 517 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 518 519 if (sc->sc_has_rcba) { 520 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 521 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 522 LPCIB_RCBA_HPTC); 523 } else if (sc->sc_has_ich5_hpet) { 524 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 525 } 526 527 return true; 528 } 529 530 static bool 531 lpcib_resume(device_t dv, const pmf_qual_t *qual) 532 { 533 struct lpcib_softc *sc = device_private(dv); 534 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 535 pcitag_t tag = sc->sc_pcib.sc_tag; 536 537 /* restore PIRQ routing control registers */ 538 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 539 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 540 541 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 542 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 543 544 if (sc->sc_has_rcba) { 545 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 546 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 547 sc->sc_hpet_reg); 548 } else if (sc->sc_has_ich5_hpet) { 549 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 550 } 551 552 return true; 553 } 554 555 /* 556 * Initialize the power management timer. 557 */ 558 static void 559 pmtimer_configure(device_t self) 560 { 561 struct lpcib_softc *sc = device_private(self); 562 pcireg_t control; 563 564 /* 565 * Check if power management I/O space is enabled and enable the ACPI_EN 566 * bit if it's disabled. 567 */ 568 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 569 LPCIB_PCI_ACPI_CNTL); 570 sc->sc_acpi_cntl = control; 571 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 572 control |= LPCIB_PCI_ACPI_CNTL_EN; 573 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 574 LPCIB_PCI_ACPI_CNTL, control); 575 } 576 577 /* Attach our PM timer with the generic acpipmtimer function */ 578 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 579 LPCIB_PM1_TMR, 0); 580 } 581 582 static int 583 pmtimer_unconfigure(device_t self, int flags) 584 { 585 struct lpcib_softc *sc = device_private(self); 586 int rc; 587 588 if (sc->sc_pmtimer != NULL && 589 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 590 return rc; 591 592 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 593 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 594 595 return 0; 596 } 597 598 /* 599 * Initialize the watchdog timer. 600 */ 601 static void 602 tcotimer_configure(device_t self) 603 { 604 struct lpcib_softc *sc = device_private(self); 605 uint32_t ioreg; 606 unsigned int period; 607 608 /* Explicitly stop the TCO timer. */ 609 tcotimer_stop(sc); 610 611 /* 612 * Enable TCO timeout SMI only if the hardware reset does not 613 * work. We don't know what the SMBIOS does. 614 */ 615 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 616 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 617 618 /* 619 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 620 * in the SMI_EN register is the last chance. 621 */ 622 if (tcotimer_disable_noreboot(self)) { 623 ioreg |= LPCIB_SMI_EN_TCO_EN; 624 } 625 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 626 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 627 } 628 629 /* Reset the watchdog status registers. */ 630 tcotimer_status_reset(sc); 631 632 /* 633 * Register the driver with the sysmon watchdog framework. 634 */ 635 sc->sc_smw.smw_name = device_xname(self); 636 sc->sc_smw.smw_cookie = sc; 637 sc->sc_smw.smw_setmode = tcotimer_setmode; 638 sc->sc_smw.smw_tickle = tcotimer_tickle; 639 if (sc->sc_has_rcba) 640 period = LPCIB_TCOTIMER2_MAX_TICK; 641 else 642 period = LPCIB_TCOTIMER_MAX_TICK; 643 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 644 645 if (sysmon_wdog_register(&sc->sc_smw)) { 646 aprint_error_dev(self, "unable to register TCO timer" 647 "as a sysmon watchdog device.\n"); 648 return; 649 } 650 651 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 652 } 653 654 static int 655 tcotimer_unconfigure(device_t self, int flags) 656 { 657 struct lpcib_softc *sc = device_private(self); 658 int rc; 659 660 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 661 if (rc == ERESTART) 662 rc = EINTR; 663 return rc; 664 } 665 666 /* Explicitly stop the TCO timer. */ 667 tcotimer_stop(sc); 668 669 /* XXX Set No Reboot? */ 670 671 return 0; 672 } 673 674 675 /* 676 * Sysmon watchdog callbacks. 677 */ 678 static int 679 tcotimer_setmode(struct sysmon_wdog *smw) 680 { 681 struct lpcib_softc *sc = smw->smw_cookie; 682 unsigned int period; 683 uint16_t ich6period = 0; 684 uint8_t ich5period = 0; 685 686 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 687 /* Stop the TCO timer. */ 688 tcotimer_stop(sc); 689 } else { 690 /* 691 * ICH6 or newer are limited to 2s min and 613s max. 692 * ICH5 or older are limited to 4s min and 39s max. 693 */ 694 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 695 if (sc->sc_has_rcba) { 696 if (period < LPCIB_TCOTIMER2_MIN_TICK || 697 period > LPCIB_TCOTIMER2_MAX_TICK) 698 return EINVAL; 699 } else { 700 if (period < LPCIB_TCOTIMER_MIN_TICK || 701 period > LPCIB_TCOTIMER_MAX_TICK) 702 return EINVAL; 703 } 704 705 /* Stop the TCO timer, */ 706 tcotimer_stop(sc); 707 708 /* set the timeout, */ 709 if (sc->sc_has_rcba) { 710 /* ICH6 or newer */ 711 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 712 LPCIB_TCO_TMR2); 713 ich6period &= 0xfc00; 714 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 715 LPCIB_TCO_TMR2, ich6period | period); 716 } else { 717 /* ICH5 or older */ 718 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 719 LPCIB_TCO_TMR); 720 ich5period &= 0xc0; 721 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 722 LPCIB_TCO_TMR, ich5period | period); 723 } 724 725 /* and start/reload the timer. */ 726 tcotimer_start(sc); 727 tcotimer_tickle(smw); 728 } 729 730 return 0; 731 } 732 733 static int 734 tcotimer_tickle(struct sysmon_wdog *smw) 735 { 736 struct lpcib_softc *sc = smw->smw_cookie; 737 738 /* any value is allowed */ 739 if (sc->sc_has_rcba) 740 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 741 else 742 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 743 744 return 0; 745 } 746 747 static void 748 tcotimer_stop(struct lpcib_softc *sc) 749 { 750 uint16_t ioreg; 751 752 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 753 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 754 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 755 } 756 757 static void 758 tcotimer_start(struct lpcib_softc *sc) 759 { 760 uint16_t ioreg; 761 762 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 763 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 764 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 765 } 766 767 static void 768 tcotimer_status_reset(struct lpcib_softc *sc) 769 { 770 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 771 LPCIB_TCO1_STS_TIMEOUT); 772 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 773 LPCIB_TCO2_STS_BOOT_STS); 774 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 775 LPCIB_TCO2_STS_SECONDS_TO_STS); 776 } 777 778 /* 779 * Clear the No Reboot (NR) bit, this enables reboots when the timer 780 * reaches the timeout for the second time. 781 */ 782 static int 783 tcotimer_disable_noreboot(device_t self) 784 { 785 struct lpcib_softc *sc = device_private(self); 786 787 if (sc->sc_has_rcba) { 788 uint32_t status; 789 790 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 791 LPCIB_GCS_OFFSET); 792 status &= ~LPCIB_GCS_NO_REBOOT; 793 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 794 LPCIB_GCS_OFFSET, status); 795 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 796 LPCIB_GCS_OFFSET); 797 if (status & LPCIB_GCS_NO_REBOOT) 798 goto error; 799 } else { 800 pcireg_t pcireg; 801 802 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 803 LPCIB_PCI_GEN_STA); 804 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 805 /* TCO timeout reset is disabled; try to enable it */ 806 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 807 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 808 LPCIB_PCI_GEN_STA, pcireg); 809 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 810 goto error; 811 } 812 } 813 814 return 0; 815 error: 816 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 817 "hope SMBIOS properly handles it.\n"); 818 return EINVAL; 819 } 820 821 822 /* 823 * Intel ICH SpeedStep support. 824 */ 825 #define SS_READ(sc, reg) \ 826 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 827 #define SS_WRITE(sc, reg, val) \ 828 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 829 830 /* 831 * Linux driver says that SpeedStep on older chipsets cause 832 * lockups on Dell Inspiron 8000 and 8100. 833 * It should also not be enabled on systems with the 82855GM 834 * Hub, which typically have an EST-enabled CPU. 835 */ 836 static int 837 speedstep_bad_hb_check(const struct pci_attach_args *pa) 838 { 839 840 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 841 PCI_REVISION(pa->pa_class) < 5) 842 return 1; 843 844 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 845 return 1; 846 847 return 0; 848 } 849 850 static void 851 speedstep_configure(device_t self) 852 { 853 struct lpcib_softc *sc = device_private(self); 854 const struct sysctlnode *node, *ssnode; 855 int rv; 856 857 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 858 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 859 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 860 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 861 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 862 pcireg_t pmcon; 863 864 /* Enable SpeedStep if it isn't already enabled. */ 865 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 866 LPCIB_PCI_GEN_PMCON_1); 867 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 868 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 869 LPCIB_PCI_GEN_PMCON_1, 870 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 871 872 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 873 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 874 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 875 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 876 goto err; 877 878 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 879 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 880 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 881 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 882 CTL_EOL)) != 0) 883 goto err; 884 885 /* XXX save the sc for IO tag/handle */ 886 speedstep_cookie = sc; 887 aprint_verbose_dev(self, "SpeedStep enabled\n"); 888 } 889 890 return; 891 892 err: 893 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 894 } 895 896 static void 897 speedstep_unconfigure(device_t self) 898 { 899 struct lpcib_softc *sc = device_private(self); 900 901 sysctl_teardown(&sc->sc_log); 902 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 903 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 904 905 speedstep_cookie = NULL; 906 } 907 908 /* 909 * get/set the SpeedStep state: 0 == low power, 1 == high power. 910 */ 911 static int 912 speedstep_sysctl_helper(SYSCTLFN_ARGS) 913 { 914 struct sysctlnode node; 915 struct lpcib_softc *sc = speedstep_cookie; 916 uint8_t state, state2; 917 int ostate, nstate, s, error = 0; 918 919 /* 920 * We do the dance with spl's to avoid being at high ipl during 921 * sysctl_lookup() which can both copyin and copyout. 922 */ 923 s = splserial(); 924 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 925 splx(s); 926 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 927 ostate = 1; 928 else 929 ostate = 0; 930 nstate = ostate; 931 932 node = *rnode; 933 node.sysctl_data = &nstate; 934 935 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 936 if (error || newp == NULL) 937 goto out; 938 939 /* Only two states are available */ 940 if (nstate != 0 && nstate != 1) { 941 error = EINVAL; 942 goto out; 943 } 944 945 s = splserial(); 946 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 947 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 948 ostate = 1; 949 else 950 ostate = 0; 951 952 if (ostate != nstate) { 953 uint8_t cntl; 954 955 if (nstate == 0) 956 state2 |= LPCIB_PM_SS_STATE_LOW; 957 else 958 state2 &= ~LPCIB_PM_SS_STATE_LOW; 959 960 /* 961 * Must disable bus master arbitration during the change. 962 */ 963 cntl = SS_READ(sc, LPCIB_PM_CTRL); 964 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 965 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 966 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 967 } 968 splx(s); 969 out: 970 return error; 971 } 972 973 static void 974 lpcib_hpet_configure(device_t self) 975 { 976 struct lpcib_softc *sc = device_private(self); 977 struct lpcib_hpet_attach_args arg; 978 uint32_t hpet_reg, val; 979 980 if (sc->sc_has_ich5_hpet) { 981 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 982 LPCIB_PCI_GEN_CNTL); 983 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 984 case LPCIB_ICH5_HPTC_0000: 985 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 986 break; 987 case LPCIB_ICH5_HPTC_1000: 988 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 989 break; 990 case LPCIB_ICH5_HPTC_2000: 991 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 992 break; 993 case LPCIB_ICH5_HPTC_3000: 994 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 995 break; 996 default: 997 return; 998 } 999 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 1000 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1001 LPCIB_PCI_GEN_CNTL, val); 1002 } else if (sc->sc_has_rcba) { 1003 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 1004 LPCIB_RCBA_HPTC); 1005 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 1006 case LPCIB_RCBA_HPTC_0000: 1007 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 1008 break; 1009 case LPCIB_RCBA_HPTC_1000: 1010 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 1011 break; 1012 case LPCIB_RCBA_HPTC_2000: 1013 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1014 break; 1015 case LPCIB_RCBA_HPTC_3000: 1016 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1017 break; 1018 default: 1019 return; 1020 } 1021 val |= LPCIB_RCBA_HPTC_EN; 1022 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1023 val); 1024 } else { 1025 /* No HPET here */ 1026 return; 1027 } 1028 1029 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1030 arg.hpet_reg = hpet_reg; 1031 1032 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1033 } 1034 1035 static int 1036 lpcib_hpet_unconfigure(device_t self, int flags) 1037 { 1038 struct lpcib_softc *sc = device_private(self); 1039 int rc; 1040 1041 if (sc->sc_hpetbus != NULL && 1042 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1043 return rc; 1044 1045 return 0; 1046 } 1047 1048 #if NGPIO > 0 1049 static void 1050 lpcib_gpio_configure(device_t self) 1051 { 1052 struct lpcib_softc *sc = device_private(self); 1053 struct gpiobus_attach_args gba; 1054 pcireg_t gpio_cntl; 1055 uint32_t use, io, bit; 1056 int pin, shift, base_reg, cntl_reg, reg; 1057 1058 /* this implies ICH >= 6, and thus different mapreg */ 1059 if (sc->sc_has_rcba) { 1060 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1061 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1062 } else { 1063 base_reg = LPCIB_PCI_GPIO_BASE; 1064 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1065 } 1066 1067 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1068 cntl_reg); 1069 1070 /* Is GPIO enabled? */ 1071 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1072 return; 1073 1074 if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1075 &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1076 NULL, &sc->sc_gpio_ios)) { 1077 aprint_error_dev(self, "can't map general purpose i/o space\n"); 1078 return; 1079 } 1080 1081 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1082 1083 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1084 sc->sc_gpio_pins[pin].pin_num = pin; 1085 1086 /* Read initial state */ 1087 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1088 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1089 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1090 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1091 shift = pin % 32; 1092 bit = __BIT(shift); 1093 1094 if ((use & bit) != 0) { 1095 sc->sc_gpio_pins[pin].pin_caps = 1096 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1097 if (pin < 32) 1098 sc->sc_gpio_pins[pin].pin_caps |= 1099 GPIO_PIN_PULSATE; 1100 if ((io & bit) != 0) 1101 sc->sc_gpio_pins[pin].pin_flags = 1102 GPIO_PIN_INPUT; 1103 else 1104 sc->sc_gpio_pins[pin].pin_flags = 1105 GPIO_PIN_OUTPUT; 1106 } else 1107 sc->sc_gpio_pins[pin].pin_caps = 0; 1108 1109 if (lpcib_gpio_pin_read(sc, pin) == 0) 1110 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1111 else 1112 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1113 1114 } 1115 1116 /* Create controller tag */ 1117 sc->sc_gpio_gc.gp_cookie = sc; 1118 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1119 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1120 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1121 1122 memset(&gba, 0, sizeof(gba)); 1123 1124 gba.gba_gc = &sc->sc_gpio_gc; 1125 gba.gba_pins = sc->sc_gpio_pins; 1126 gba.gba_npins = LPCIB_GPIO_NPINS; 1127 1128 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1129 } 1130 1131 static int 1132 lpcib_gpio_unconfigure(device_t self, int flags) 1133 { 1134 struct lpcib_softc *sc = device_private(self); 1135 int rc; 1136 1137 if (sc->sc_gpiobus != NULL && 1138 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1139 return rc; 1140 1141 mutex_destroy(&sc->sc_gpio_mtx); 1142 1143 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1144 1145 return 0; 1146 } 1147 1148 static int 1149 lpcib_gpio_pin_read(void *arg, int pin) 1150 { 1151 struct lpcib_softc *sc = arg; 1152 uint32_t data; 1153 int reg, shift; 1154 1155 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1156 shift = pin % 32; 1157 1158 mutex_enter(&sc->sc_gpio_mtx); 1159 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1160 mutex_exit(&sc->sc_gpio_mtx); 1161 1162 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1163 } 1164 1165 static void 1166 lpcib_gpio_pin_write(void *arg, int pin, int value) 1167 { 1168 struct lpcib_softc *sc = arg; 1169 uint32_t data; 1170 int reg, shift; 1171 1172 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1173 shift = pin % 32; 1174 1175 mutex_enter(&sc->sc_gpio_mtx); 1176 1177 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1178 1179 if(value) 1180 data |= __BIT(shift); 1181 else 1182 data &= ~__BIT(shift); 1183 1184 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1185 1186 mutex_exit(&sc->sc_gpio_mtx); 1187 } 1188 1189 static void 1190 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1191 { 1192 struct lpcib_softc *sc = arg; 1193 uint32_t data; 1194 int reg, shift; 1195 1196 shift = pin % 32; 1197 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1198 1199 mutex_enter(&sc->sc_gpio_mtx); 1200 1201 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1202 1203 if (flags & GPIO_PIN_OUTPUT) 1204 data &= ~__BIT(shift); 1205 1206 if (flags & GPIO_PIN_INPUT) 1207 data |= __BIT(shift); 1208 1209 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1210 1211 1212 if (pin < 32) { 1213 reg = LPCIB_GPIO_GPO_BLINK; 1214 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1215 1216 if (flags & GPIO_PIN_PULSATE) 1217 data |= __BIT(shift); 1218 else 1219 data &= ~__BIT(shift); 1220 1221 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1222 } 1223 1224 mutex_exit(&sc->sc_gpio_mtx); 1225 } 1226 #endif 1227 1228 #if NFWHRNG > 0 1229 static void 1230 lpcib_fwh_configure(device_t self) 1231 { 1232 struct lpcib_softc *sc; 1233 pcireg_t pr; 1234 1235 sc = device_private(self); 1236 1237 if (sc->sc_has_rcba) { 1238 /* 1239 * Very unlikely to find a 82802 on a ICH6 or newer. 1240 * Also the write enable register moved at that point. 1241 */ 1242 return; 1243 } else { 1244 /* Enable FWH write to identify FWH. */ 1245 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1246 LPCIB_PCI_BIOS_CNTL); 1247 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1248 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1249 } 1250 1251 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1252 1253 /* restore previous write enable setting */ 1254 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1255 LPCIB_PCI_BIOS_CNTL, pr); 1256 } 1257 1258 static int 1259 lpcib_fwh_unconfigure(device_t self, int flags) 1260 { 1261 struct lpcib_softc *sc = device_private(self); 1262 int rc; 1263 1264 if (sc->sc_fwhbus != NULL && 1265 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1266 return rc; 1267 1268 return 0; 1269 } 1270 #endif 1271
Indexes created Tue Sep 30 11:09:46 GMT 2025