ichlpcib.c revision 1.43
1 /* $NetBSD: ichlpcib.c,v 1.43 2014/01/04 02:59:17 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.43 2014/01/04 02:59:17 msaitoh Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z68_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 264 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 265 #if 0 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 270 #endif 271 272 { 0, 0, 0, 0 }, 273 }; 274 275 /* 276 * Autoconf callbacks. 277 */ 278 static int 279 lpcibmatch(device_t parent, cfdata_t match, void *aux) 280 { 281 struct pci_attach_args *pa = aux; 282 struct lpcib_device *lpcib_dev; 283 284 /* We are ISA bridge, of course */ 285 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 286 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 287 return 0; 288 289 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 290 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 291 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 292 return 10; 293 } 294 295 return 0; 296 } 297 298 static void 299 lpcibattach(device_t parent, device_t self, void *aux) 300 { 301 struct pci_attach_args *pa = aux; 302 struct lpcib_softc *sc = device_private(self); 303 struct lpcib_device *lpcib_dev; 304 305 sc->sc_pa = *pa; 306 307 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 308 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 309 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 310 continue; 311 sc->sc_has_rcba = lpcib_dev->has_rcba; 312 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 313 break; 314 } 315 316 pcibattach(parent, self, aux); 317 318 /* 319 * Part of our I/O registers are used as ACPI PM regs. 320 * Since our ACPI subsystem accesses the I/O space directly so far, 321 * we do not have to bother bus_space I/O map confliction. 322 */ 323 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 324 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { 325 aprint_error_dev(self, "can't map power management i/o space\n"); 326 return; 327 } 328 329 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 330 LPCIB_PCI_GEN_PMCON_1); 331 332 /* For ICH6 and later, always enable RCBA */ 333 if (sc->sc_has_rcba) { 334 pcireg_t rcba; 335 336 sc->sc_rcbat = sc->sc_pa.pa_memt; 337 338 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 339 LPCIB_RCBA); 340 if ((rcba & LPCIB_RCBA_EN) == 0) { 341 aprint_error_dev(self, "RCBA is not enabled\n"); 342 return; 343 } 344 rcba &= ~LPCIB_RCBA_EN; 345 346 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 347 &sc->sc_rcbah)) { 348 aprint_error_dev(self, "RCBA could not be mapped\n"); 349 return; 350 } 351 } 352 353 /* Set up the power management timer. */ 354 pmtimer_configure(self); 355 356 /* Set up the TCO (watchdog). */ 357 tcotimer_configure(self); 358 359 /* Set up SpeedStep. */ 360 speedstep_configure(self); 361 362 /* Set up HPET. */ 363 lpcib_hpet_configure(self); 364 365 #if NGPIO > 0 366 /* Set up GPIO */ 367 lpcib_gpio_configure(self); 368 #endif 369 370 #if NFWHRNG > 0 371 lpcib_fwh_configure(self); 372 #endif 373 374 /* Install power handler */ 375 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 376 lpcib_shutdown)) 377 aprint_error_dev(self, "couldn't establish power handler\n"); 378 } 379 380 static void 381 lpcibchilddet(device_t self, device_t child) 382 { 383 struct lpcib_softc *sc = device_private(self); 384 uint32_t val; 385 386 #if NFWHRNG > 0 387 if (sc->sc_fwhbus == child) { 388 sc->sc_fwhbus = NULL; 389 return; 390 } 391 #endif 392 #if NGPIO > 0 393 if (sc->sc_gpiobus == child) { 394 sc->sc_gpiobus = NULL; 395 return; 396 } 397 #endif 398 if (sc->sc_hpetbus != child) { 399 pcibchilddet(self, child); 400 return; 401 } 402 sc->sc_hpetbus = NULL; 403 if (sc->sc_has_ich5_hpet) { 404 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 405 LPCIB_PCI_GEN_CNTL); 406 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 407 case LPCIB_ICH5_HPTC_0000: 408 case LPCIB_ICH5_HPTC_1000: 409 case LPCIB_ICH5_HPTC_2000: 410 case LPCIB_ICH5_HPTC_3000: 411 break; 412 default: 413 return; 414 } 415 val &= ~LPCIB_ICH5_HPTC_EN; 416 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 417 LPCIB_PCI_GEN_CNTL, val); 418 } else if (sc->sc_has_rcba) { 419 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 420 LPCIB_RCBA_HPTC); 421 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 422 case LPCIB_RCBA_HPTC_0000: 423 case LPCIB_RCBA_HPTC_1000: 424 case LPCIB_RCBA_HPTC_2000: 425 case LPCIB_RCBA_HPTC_3000: 426 break; 427 default: 428 return; 429 } 430 val &= ~LPCIB_RCBA_HPTC_EN; 431 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 432 val); 433 } 434 } 435 436 static int 437 lpcibrescan(device_t self, const char *ifattr, const int *locators) 438 { 439 struct lpcib_softc *sc = device_private(self); 440 441 #if NFWHRNG > 0 442 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 443 lpcib_fwh_configure(self); 444 #endif 445 446 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 447 lpcib_hpet_configure(self); 448 449 #if NGPIO > 0 450 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 451 lpcib_gpio_configure(self); 452 #endif 453 454 return pcibrescan(self, ifattr, locators); 455 } 456 457 static int 458 lpcibdetach(device_t self, int flags) 459 { 460 struct lpcib_softc *sc = device_private(self); 461 int rc; 462 463 pmf_device_deregister(self); 464 465 #if NFWHRNG > 0 466 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 467 return rc; 468 #endif 469 470 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 471 return rc; 472 473 #if NGPIO > 0 474 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 475 return rc; 476 #endif 477 478 /* Set up SpeedStep. */ 479 speedstep_unconfigure(self); 480 481 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 482 return rc; 483 484 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 485 return rc; 486 487 if (sc->sc_has_rcba) 488 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 489 490 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 491 492 return pcibdetach(self, flags); 493 } 494 495 static bool 496 lpcib_shutdown(device_t dv, int howto) 497 { 498 struct lpcib_softc *sc = device_private(dv); 499 500 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 501 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 502 503 return true; 504 } 505 506 static bool 507 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 508 { 509 struct lpcib_softc *sc = device_private(dv); 510 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 511 pcitag_t tag = sc->sc_pcib.sc_tag; 512 513 /* capture PIRQ routing control registers */ 514 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 515 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 516 517 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 518 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 519 520 if (sc->sc_has_rcba) { 521 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 522 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 523 LPCIB_RCBA_HPTC); 524 } else if (sc->sc_has_ich5_hpet) { 525 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 526 } 527 528 return true; 529 } 530 531 static bool 532 lpcib_resume(device_t dv, const pmf_qual_t *qual) 533 { 534 struct lpcib_softc *sc = device_private(dv); 535 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 536 pcitag_t tag = sc->sc_pcib.sc_tag; 537 538 /* restore PIRQ routing control registers */ 539 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 540 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 541 542 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 543 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 544 545 if (sc->sc_has_rcba) { 546 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 547 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 548 sc->sc_hpet_reg); 549 } else if (sc->sc_has_ich5_hpet) { 550 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 551 } 552 553 return true; 554 } 555 556 /* 557 * Initialize the power management timer. 558 */ 559 static void 560 pmtimer_configure(device_t self) 561 { 562 struct lpcib_softc *sc = device_private(self); 563 pcireg_t control; 564 565 /* 566 * Check if power management I/O space is enabled and enable the ACPI_EN 567 * bit if it's disabled. 568 */ 569 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 570 LPCIB_PCI_ACPI_CNTL); 571 sc->sc_acpi_cntl = control; 572 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 573 control |= LPCIB_PCI_ACPI_CNTL_EN; 574 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 575 LPCIB_PCI_ACPI_CNTL, control); 576 } 577 578 /* Attach our PM timer with the generic acpipmtimer function */ 579 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 580 LPCIB_PM1_TMR, 0); 581 } 582 583 static int 584 pmtimer_unconfigure(device_t self, int flags) 585 { 586 struct lpcib_softc *sc = device_private(self); 587 int rc; 588 589 if (sc->sc_pmtimer != NULL && 590 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 591 return rc; 592 593 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 594 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 595 596 return 0; 597 } 598 599 /* 600 * Initialize the watchdog timer. 601 */ 602 static void 603 tcotimer_configure(device_t self) 604 { 605 struct lpcib_softc *sc = device_private(self); 606 uint32_t ioreg; 607 unsigned int period; 608 609 /* Explicitly stop the TCO timer. */ 610 tcotimer_stop(sc); 611 612 /* 613 * Enable TCO timeout SMI only if the hardware reset does not 614 * work. We don't know what the SMBIOS does. 615 */ 616 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 617 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 618 619 /* 620 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 621 * in the SMI_EN register is the last chance. 622 */ 623 if (tcotimer_disable_noreboot(self)) { 624 ioreg |= LPCIB_SMI_EN_TCO_EN; 625 } 626 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 627 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 628 } 629 630 /* Reset the watchdog status registers. */ 631 tcotimer_status_reset(sc); 632 633 /* 634 * Register the driver with the sysmon watchdog framework. 635 */ 636 sc->sc_smw.smw_name = device_xname(self); 637 sc->sc_smw.smw_cookie = sc; 638 sc->sc_smw.smw_setmode = tcotimer_setmode; 639 sc->sc_smw.smw_tickle = tcotimer_tickle; 640 if (sc->sc_has_rcba) 641 period = LPCIB_TCOTIMER2_MAX_TICK; 642 else 643 period = LPCIB_TCOTIMER_MAX_TICK; 644 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 645 646 if (sysmon_wdog_register(&sc->sc_smw)) { 647 aprint_error_dev(self, "unable to register TCO timer" 648 "as a sysmon watchdog device.\n"); 649 return; 650 } 651 652 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 653 } 654 655 static int 656 tcotimer_unconfigure(device_t self, int flags) 657 { 658 struct lpcib_softc *sc = device_private(self); 659 int rc; 660 661 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 662 if (rc == ERESTART) 663 rc = EINTR; 664 return rc; 665 } 666 667 /* Explicitly stop the TCO timer. */ 668 tcotimer_stop(sc); 669 670 /* XXX Set No Reboot? */ 671 672 return 0; 673 } 674 675 676 /* 677 * Sysmon watchdog callbacks. 678 */ 679 static int 680 tcotimer_setmode(struct sysmon_wdog *smw) 681 { 682 struct lpcib_softc *sc = smw->smw_cookie; 683 unsigned int period; 684 uint16_t ich6period = 0; 685 uint8_t ich5period = 0; 686 687 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 688 /* Stop the TCO timer. */ 689 tcotimer_stop(sc); 690 } else { 691 /* 692 * ICH6 or newer are limited to 2s min and 613s max. 693 * ICH5 or older are limited to 4s min and 39s max. 694 */ 695 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 696 if (sc->sc_has_rcba) { 697 if (period < LPCIB_TCOTIMER2_MIN_TICK || 698 period > LPCIB_TCOTIMER2_MAX_TICK) 699 return EINVAL; 700 } else { 701 if (period < LPCIB_TCOTIMER_MIN_TICK || 702 period > LPCIB_TCOTIMER_MAX_TICK) 703 return EINVAL; 704 } 705 706 /* Stop the TCO timer, */ 707 tcotimer_stop(sc); 708 709 /* set the timeout, */ 710 if (sc->sc_has_rcba) { 711 /* ICH6 or newer */ 712 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 713 LPCIB_TCO_TMR2); 714 ich6period &= 0xfc00; 715 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 716 LPCIB_TCO_TMR2, ich6period | period); 717 } else { 718 /* ICH5 or older */ 719 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 720 LPCIB_TCO_TMR); 721 ich5period &= 0xc0; 722 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 723 LPCIB_TCO_TMR, ich5period | period); 724 } 725 726 /* and start/reload the timer. */ 727 tcotimer_start(sc); 728 tcotimer_tickle(smw); 729 } 730 731 return 0; 732 } 733 734 static int 735 tcotimer_tickle(struct sysmon_wdog *smw) 736 { 737 struct lpcib_softc *sc = smw->smw_cookie; 738 739 /* any value is allowed */ 740 if (sc->sc_has_rcba) 741 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 742 else 743 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 744 745 return 0; 746 } 747 748 static void 749 tcotimer_stop(struct lpcib_softc *sc) 750 { 751 uint16_t ioreg; 752 753 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 754 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 755 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 756 } 757 758 static void 759 tcotimer_start(struct lpcib_softc *sc) 760 { 761 uint16_t ioreg; 762 763 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 764 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 765 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 766 } 767 768 static void 769 tcotimer_status_reset(struct lpcib_softc *sc) 770 { 771 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 772 LPCIB_TCO1_STS_TIMEOUT); 773 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 774 LPCIB_TCO2_STS_BOOT_STS); 775 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 776 LPCIB_TCO2_STS_SECONDS_TO_STS); 777 } 778 779 /* 780 * Clear the No Reboot (NR) bit, this enables reboots when the timer 781 * reaches the timeout for the second time. 782 */ 783 static int 784 tcotimer_disable_noreboot(device_t self) 785 { 786 struct lpcib_softc *sc = device_private(self); 787 788 if (sc->sc_has_rcba) { 789 uint32_t status; 790 791 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 792 LPCIB_GCS_OFFSET); 793 status &= ~LPCIB_GCS_NO_REBOOT; 794 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 795 LPCIB_GCS_OFFSET, status); 796 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 797 LPCIB_GCS_OFFSET); 798 if (status & LPCIB_GCS_NO_REBOOT) 799 goto error; 800 } else { 801 pcireg_t pcireg; 802 803 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 804 LPCIB_PCI_GEN_STA); 805 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 806 /* TCO timeout reset is disabled; try to enable it */ 807 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 808 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 809 LPCIB_PCI_GEN_STA, pcireg); 810 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 811 goto error; 812 } 813 } 814 815 return 0; 816 error: 817 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 818 "hope SMBIOS properly handles it.\n"); 819 return EINVAL; 820 } 821 822 823 /* 824 * Intel ICH SpeedStep support. 825 */ 826 #define SS_READ(sc, reg) \ 827 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 828 #define SS_WRITE(sc, reg, val) \ 829 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 830 831 /* 832 * Linux driver says that SpeedStep on older chipsets cause 833 * lockups on Dell Inspiron 8000 and 8100. 834 * It should also not be enabled on systems with the 82855GM 835 * Hub, which typically have an EST-enabled CPU. 836 */ 837 static int 838 speedstep_bad_hb_check(const struct pci_attach_args *pa) 839 { 840 841 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 842 PCI_REVISION(pa->pa_class) < 5) 843 return 1; 844 845 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 846 return 1; 847 848 return 0; 849 } 850 851 static void 852 speedstep_configure(device_t self) 853 { 854 struct lpcib_softc *sc = device_private(self); 855 const struct sysctlnode *node, *ssnode; 856 int rv; 857 858 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 859 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 860 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 861 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 862 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 863 pcireg_t pmcon; 864 865 /* Enable SpeedStep if it isn't already enabled. */ 866 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 867 LPCIB_PCI_GEN_PMCON_1); 868 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 869 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 870 LPCIB_PCI_GEN_PMCON_1, 871 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 872 873 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 874 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 875 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 876 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 877 goto err; 878 879 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 880 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 881 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 882 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 883 CTL_EOL)) != 0) 884 goto err; 885 886 /* XXX save the sc for IO tag/handle */ 887 speedstep_cookie = sc; 888 aprint_verbose_dev(self, "SpeedStep enabled\n"); 889 } 890 891 return; 892 893 err: 894 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 895 } 896 897 static void 898 speedstep_unconfigure(device_t self) 899 { 900 struct lpcib_softc *sc = device_private(self); 901 902 sysctl_teardown(&sc->sc_log); 903 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 904 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 905 906 speedstep_cookie = NULL; 907 } 908 909 /* 910 * get/set the SpeedStep state: 0 == low power, 1 == high power. 911 */ 912 static int 913 speedstep_sysctl_helper(SYSCTLFN_ARGS) 914 { 915 struct sysctlnode node; 916 struct lpcib_softc *sc = speedstep_cookie; 917 uint8_t state, state2; 918 int ostate, nstate, s, error = 0; 919 920 /* 921 * We do the dance with spl's to avoid being at high ipl during 922 * sysctl_lookup() which can both copyin and copyout. 923 */ 924 s = splserial(); 925 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 926 splx(s); 927 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 928 ostate = 1; 929 else 930 ostate = 0; 931 nstate = ostate; 932 933 node = *rnode; 934 node.sysctl_data = &nstate; 935 936 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 937 if (error || newp == NULL) 938 goto out; 939 940 /* Only two states are available */ 941 if (nstate != 0 && nstate != 1) { 942 error = EINVAL; 943 goto out; 944 } 945 946 s = splserial(); 947 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 948 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 949 ostate = 1; 950 else 951 ostate = 0; 952 953 if (ostate != nstate) { 954 uint8_t cntl; 955 956 if (nstate == 0) 957 state2 |= LPCIB_PM_SS_STATE_LOW; 958 else 959 state2 &= ~LPCIB_PM_SS_STATE_LOW; 960 961 /* 962 * Must disable bus master arbitration during the change. 963 */ 964 cntl = SS_READ(sc, LPCIB_PM_CTRL); 965 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 966 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 967 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 968 } 969 splx(s); 970 out: 971 return error; 972 } 973 974 static void 975 lpcib_hpet_configure(device_t self) 976 { 977 struct lpcib_softc *sc = device_private(self); 978 struct lpcib_hpet_attach_args arg; 979 uint32_t hpet_reg, val; 980 981 if (sc->sc_has_ich5_hpet) { 982 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 983 LPCIB_PCI_GEN_CNTL); 984 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 985 case LPCIB_ICH5_HPTC_0000: 986 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 987 break; 988 case LPCIB_ICH5_HPTC_1000: 989 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 990 break; 991 case LPCIB_ICH5_HPTC_2000: 992 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 993 break; 994 case LPCIB_ICH5_HPTC_3000: 995 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 996 break; 997 default: 998 return; 999 } 1000 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 1001 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1002 LPCIB_PCI_GEN_CNTL, val); 1003 } else if (sc->sc_has_rcba) { 1004 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 1005 LPCIB_RCBA_HPTC); 1006 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 1007 case LPCIB_RCBA_HPTC_0000: 1008 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 1009 break; 1010 case LPCIB_RCBA_HPTC_1000: 1011 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 1012 break; 1013 case LPCIB_RCBA_HPTC_2000: 1014 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1015 break; 1016 case LPCIB_RCBA_HPTC_3000: 1017 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1018 break; 1019 default: 1020 return; 1021 } 1022 val |= LPCIB_RCBA_HPTC_EN; 1023 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1024 val); 1025 } else { 1026 /* No HPET here */ 1027 return; 1028 } 1029 1030 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1031 arg.hpet_reg = hpet_reg; 1032 1033 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1034 } 1035 1036 static int 1037 lpcib_hpet_unconfigure(device_t self, int flags) 1038 { 1039 struct lpcib_softc *sc = device_private(self); 1040 int rc; 1041 1042 if (sc->sc_hpetbus != NULL && 1043 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1044 return rc; 1045 1046 return 0; 1047 } 1048 1049 #if NGPIO > 0 1050 static void 1051 lpcib_gpio_configure(device_t self) 1052 { 1053 struct lpcib_softc *sc = device_private(self); 1054 struct gpiobus_attach_args gba; 1055 pcireg_t gpio_cntl; 1056 uint32_t use, io, bit; 1057 int pin, shift, base_reg, cntl_reg, reg; 1058 1059 /* this implies ICH >= 6, and thus different mapreg */ 1060 if (sc->sc_has_rcba) { 1061 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1062 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1063 } else { 1064 base_reg = LPCIB_PCI_GPIO_BASE; 1065 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1066 } 1067 1068 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1069 cntl_reg); 1070 1071 /* Is GPIO enabled? */ 1072 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1073 return; 1074 1075 if (pci_mapreg_map(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1076 &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1077 NULL, &sc->sc_gpio_ios)) { 1078 aprint_error_dev(self, "can't map general purpose i/o space\n"); 1079 return; 1080 } 1081 1082 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1083 1084 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1085 sc->sc_gpio_pins[pin].pin_num = pin; 1086 1087 /* Read initial state */ 1088 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1089 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1090 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1091 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1092 shift = pin % 32; 1093 bit = __BIT(shift); 1094 1095 if ((use & bit) != 0) { 1096 sc->sc_gpio_pins[pin].pin_caps = 1097 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1098 if (pin < 32) 1099 sc->sc_gpio_pins[pin].pin_caps |= 1100 GPIO_PIN_PULSATE; 1101 if ((io & bit) != 0) 1102 sc->sc_gpio_pins[pin].pin_flags = 1103 GPIO_PIN_INPUT; 1104 else 1105 sc->sc_gpio_pins[pin].pin_flags = 1106 GPIO_PIN_OUTPUT; 1107 } else 1108 sc->sc_gpio_pins[pin].pin_caps = 0; 1109 1110 if (lpcib_gpio_pin_read(sc, pin) == 0) 1111 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1112 else 1113 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1114 1115 } 1116 1117 /* Create controller tag */ 1118 sc->sc_gpio_gc.gp_cookie = sc; 1119 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1120 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1121 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1122 1123 memset(&gba, 0, sizeof(gba)); 1124 1125 gba.gba_gc = &sc->sc_gpio_gc; 1126 gba.gba_pins = sc->sc_gpio_pins; 1127 gba.gba_npins = LPCIB_GPIO_NPINS; 1128 1129 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1130 } 1131 1132 static int 1133 lpcib_gpio_unconfigure(device_t self, int flags) 1134 { 1135 struct lpcib_softc *sc = device_private(self); 1136 int rc; 1137 1138 if (sc->sc_gpiobus != NULL && 1139 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1140 return rc; 1141 1142 mutex_destroy(&sc->sc_gpio_mtx); 1143 1144 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1145 1146 return 0; 1147 } 1148 1149 static int 1150 lpcib_gpio_pin_read(void *arg, int pin) 1151 { 1152 struct lpcib_softc *sc = arg; 1153 uint32_t data; 1154 int reg, shift; 1155 1156 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1157 shift = pin % 32; 1158 1159 mutex_enter(&sc->sc_gpio_mtx); 1160 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1161 mutex_exit(&sc->sc_gpio_mtx); 1162 1163 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1164 } 1165 1166 static void 1167 lpcib_gpio_pin_write(void *arg, int pin, int value) 1168 { 1169 struct lpcib_softc *sc = arg; 1170 uint32_t data; 1171 int reg, shift; 1172 1173 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1174 shift = pin % 32; 1175 1176 mutex_enter(&sc->sc_gpio_mtx); 1177 1178 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1179 1180 if(value) 1181 data |= __BIT(shift); 1182 else 1183 data &= ~__BIT(shift); 1184 1185 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1186 1187 mutex_exit(&sc->sc_gpio_mtx); 1188 } 1189 1190 static void 1191 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1192 { 1193 struct lpcib_softc *sc = arg; 1194 uint32_t data; 1195 int reg, shift; 1196 1197 shift = pin % 32; 1198 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1199 1200 mutex_enter(&sc->sc_gpio_mtx); 1201 1202 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1203 1204 if (flags & GPIO_PIN_OUTPUT) 1205 data &= ~__BIT(shift); 1206 1207 if (flags & GPIO_PIN_INPUT) 1208 data |= __BIT(shift); 1209 1210 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1211 1212 1213 if (pin < 32) { 1214 reg = LPCIB_GPIO_GPO_BLINK; 1215 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1216 1217 if (flags & GPIO_PIN_PULSATE) 1218 data |= __BIT(shift); 1219 else 1220 data &= ~__BIT(shift); 1221 1222 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1223 } 1224 1225 mutex_exit(&sc->sc_gpio_mtx); 1226 } 1227 #endif 1228 1229 #if NFWHRNG > 0 1230 static void 1231 lpcib_fwh_configure(device_t self) 1232 { 1233 struct lpcib_softc *sc; 1234 pcireg_t pr; 1235 1236 sc = device_private(self); 1237 1238 if (sc->sc_has_rcba) { 1239 /* 1240 * Very unlikely to find a 82802 on a ICH6 or newer. 1241 * Also the write enable register moved at that point. 1242 */ 1243 return; 1244 } else { 1245 /* Enable FWH write to identify FWH. */ 1246 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1247 LPCIB_PCI_BIOS_CNTL); 1248 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1249 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1250 } 1251 1252 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1253 1254 /* restore previous write enable setting */ 1255 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1256 LPCIB_PCI_BIOS_CNTL, pr); 1257 } 1258 1259 static int 1260 lpcib_fwh_unconfigure(device_t self, int flags) 1261 { 1262 struct lpcib_softc *sc = device_private(self); 1263 int rc; 1264 1265 if (sc->sc_fwhbus != NULL && 1266 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1267 return rc; 1268 1269 return 0; 1270 } 1271 #endif 1272
Indexes created Tue Sep 30 11:09:46 GMT 2025