ichlpcib.c revision 1.43.4.1
1 /* $NetBSD: ichlpcib.c,v 1.43.4.1 2015/01/08 11:39:38 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.43.4.1 2015/01/08 11:39:38 martin Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z68_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 264 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 265 #if 0 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 270 #endif 271 272 { 0, 0, 0, 0 }, 273 }; 274 275 /* 276 * Autoconf callbacks. 277 */ 278 static int 279 lpcibmatch(device_t parent, cfdata_t match, void *aux) 280 { 281 struct pci_attach_args *pa = aux; 282 struct lpcib_device *lpcib_dev; 283 284 /* We are ISA bridge, of course */ 285 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 286 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 287 return 0; 288 289 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 290 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 291 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 292 return 10; 293 } 294 295 return 0; 296 } 297 298 static void 299 lpcibattach(device_t parent, device_t self, void *aux) 300 { 301 struct pci_attach_args *pa = aux; 302 struct lpcib_softc *sc = device_private(self); 303 struct lpcib_device *lpcib_dev; 304 305 sc->sc_pa = *pa; 306 307 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 308 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 309 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 310 continue; 311 sc->sc_has_rcba = lpcib_dev->has_rcba; 312 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 313 break; 314 } 315 316 pcibattach(parent, self, aux); 317 318 /* 319 * Part of our I/O registers are used as ACPI PM regs. 320 * Since our ACPI subsystem accesses the I/O space directly so far, 321 * we do not have to bother bus_space I/O map confliction. 322 * 323 * The PMBASE register is alike PCI BAR but not completely compatible 324 * with it. The PMBASE define the base address and the type but 325 * not describe the size. 326 */ 327 if (pci_mapreg_submap(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 328 LPCIB_PCI_PM_SIZE, 0, &sc->sc_iot, &sc->sc_ioh, NULL, 329 &sc->sc_iosize)) { 330 aprint_error_dev(self, "can't map power management i/o space\n"); 331 return; 332 } 333 334 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 335 LPCIB_PCI_GEN_PMCON_1); 336 337 /* For ICH6 and later, always enable RCBA */ 338 if (sc->sc_has_rcba) { 339 pcireg_t rcba; 340 341 sc->sc_rcbat = sc->sc_pa.pa_memt; 342 343 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 344 LPCIB_RCBA); 345 if ((rcba & LPCIB_RCBA_EN) == 0) { 346 aprint_error_dev(self, "RCBA is not enabled\n"); 347 return; 348 } 349 rcba &= ~LPCIB_RCBA_EN; 350 351 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 352 &sc->sc_rcbah)) { 353 aprint_error_dev(self, "RCBA could not be mapped\n"); 354 return; 355 } 356 } 357 358 /* Set up the power management timer. */ 359 pmtimer_configure(self); 360 361 /* Set up the TCO (watchdog). */ 362 tcotimer_configure(self); 363 364 /* Set up SpeedStep. */ 365 speedstep_configure(self); 366 367 /* Set up HPET. */ 368 lpcib_hpet_configure(self); 369 370 #if NGPIO > 0 371 /* Set up GPIO */ 372 lpcib_gpio_configure(self); 373 #endif 374 375 #if NFWHRNG > 0 376 lpcib_fwh_configure(self); 377 #endif 378 379 /* Install power handler */ 380 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 381 lpcib_shutdown)) 382 aprint_error_dev(self, "couldn't establish power handler\n"); 383 } 384 385 static void 386 lpcibchilddet(device_t self, device_t child) 387 { 388 struct lpcib_softc *sc = device_private(self); 389 uint32_t val; 390 391 #if NFWHRNG > 0 392 if (sc->sc_fwhbus == child) { 393 sc->sc_fwhbus = NULL; 394 return; 395 } 396 #endif 397 #if NGPIO > 0 398 if (sc->sc_gpiobus == child) { 399 sc->sc_gpiobus = NULL; 400 return; 401 } 402 #endif 403 if (sc->sc_hpetbus != child) { 404 pcibchilddet(self, child); 405 return; 406 } 407 sc->sc_hpetbus = NULL; 408 if (sc->sc_has_ich5_hpet) { 409 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 410 LPCIB_PCI_GEN_CNTL); 411 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 412 case LPCIB_ICH5_HPTC_0000: 413 case LPCIB_ICH5_HPTC_1000: 414 case LPCIB_ICH5_HPTC_2000: 415 case LPCIB_ICH5_HPTC_3000: 416 break; 417 default: 418 return; 419 } 420 val &= ~LPCIB_ICH5_HPTC_EN; 421 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 422 LPCIB_PCI_GEN_CNTL, val); 423 } else if (sc->sc_has_rcba) { 424 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 425 LPCIB_RCBA_HPTC); 426 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 427 case LPCIB_RCBA_HPTC_0000: 428 case LPCIB_RCBA_HPTC_1000: 429 case LPCIB_RCBA_HPTC_2000: 430 case LPCIB_RCBA_HPTC_3000: 431 break; 432 default: 433 return; 434 } 435 val &= ~LPCIB_RCBA_HPTC_EN; 436 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 437 val); 438 } 439 } 440 441 static int 442 lpcibrescan(device_t self, const char *ifattr, const int *locators) 443 { 444 struct lpcib_softc *sc = device_private(self); 445 446 #if NFWHRNG > 0 447 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 448 lpcib_fwh_configure(self); 449 #endif 450 451 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 452 lpcib_hpet_configure(self); 453 454 #if NGPIO > 0 455 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 456 lpcib_gpio_configure(self); 457 #endif 458 459 return pcibrescan(self, ifattr, locators); 460 } 461 462 static int 463 lpcibdetach(device_t self, int flags) 464 { 465 struct lpcib_softc *sc = device_private(self); 466 int rc; 467 468 pmf_device_deregister(self); 469 470 #if NFWHRNG > 0 471 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 472 return rc; 473 #endif 474 475 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 476 return rc; 477 478 #if NGPIO > 0 479 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 480 return rc; 481 #endif 482 483 /* Set up SpeedStep. */ 484 speedstep_unconfigure(self); 485 486 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 487 return rc; 488 489 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 490 return rc; 491 492 if (sc->sc_has_rcba) 493 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 494 495 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 496 497 return pcibdetach(self, flags); 498 } 499 500 static bool 501 lpcib_shutdown(device_t dv, int howto) 502 { 503 struct lpcib_softc *sc = device_private(dv); 504 505 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 506 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 507 508 return true; 509 } 510 511 static bool 512 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 513 { 514 struct lpcib_softc *sc = device_private(dv); 515 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 516 pcitag_t tag = sc->sc_pcib.sc_tag; 517 518 /* capture PIRQ routing control registers */ 519 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 520 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 521 522 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 523 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 524 525 if (sc->sc_has_rcba) { 526 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 527 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 528 LPCIB_RCBA_HPTC); 529 } else if (sc->sc_has_ich5_hpet) { 530 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 531 } 532 533 return true; 534 } 535 536 static bool 537 lpcib_resume(device_t dv, const pmf_qual_t *qual) 538 { 539 struct lpcib_softc *sc = device_private(dv); 540 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 541 pcitag_t tag = sc->sc_pcib.sc_tag; 542 543 /* restore PIRQ routing control registers */ 544 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 545 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 546 547 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 548 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 549 550 if (sc->sc_has_rcba) { 551 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 552 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 553 sc->sc_hpet_reg); 554 } else if (sc->sc_has_ich5_hpet) { 555 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 556 } 557 558 return true; 559 } 560 561 /* 562 * Initialize the power management timer. 563 */ 564 static void 565 pmtimer_configure(device_t self) 566 { 567 struct lpcib_softc *sc = device_private(self); 568 pcireg_t control; 569 570 /* 571 * Check if power management I/O space is enabled and enable the ACPI_EN 572 * bit if it's disabled. 573 */ 574 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 575 LPCIB_PCI_ACPI_CNTL); 576 sc->sc_acpi_cntl = control; 577 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 578 control |= LPCIB_PCI_ACPI_CNTL_EN; 579 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 580 LPCIB_PCI_ACPI_CNTL, control); 581 } 582 583 /* Attach our PM timer with the generic acpipmtimer function */ 584 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 585 LPCIB_PM1_TMR, 0); 586 } 587 588 static int 589 pmtimer_unconfigure(device_t self, int flags) 590 { 591 struct lpcib_softc *sc = device_private(self); 592 int rc; 593 594 if (sc->sc_pmtimer != NULL && 595 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 596 return rc; 597 598 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 599 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 600 601 return 0; 602 } 603 604 /* 605 * Initialize the watchdog timer. 606 */ 607 static void 608 tcotimer_configure(device_t self) 609 { 610 struct lpcib_softc *sc = device_private(self); 611 uint32_t ioreg; 612 unsigned int period; 613 614 /* Explicitly stop the TCO timer. */ 615 tcotimer_stop(sc); 616 617 /* 618 * Enable TCO timeout SMI only if the hardware reset does not 619 * work. We don't know what the SMBIOS does. 620 */ 621 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 622 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 623 624 /* 625 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 626 * in the SMI_EN register is the last chance. 627 */ 628 if (tcotimer_disable_noreboot(self)) { 629 ioreg |= LPCIB_SMI_EN_TCO_EN; 630 } 631 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 632 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 633 } 634 635 /* Reset the watchdog status registers. */ 636 tcotimer_status_reset(sc); 637 638 /* 639 * Register the driver with the sysmon watchdog framework. 640 */ 641 sc->sc_smw.smw_name = device_xname(self); 642 sc->sc_smw.smw_cookie = sc; 643 sc->sc_smw.smw_setmode = tcotimer_setmode; 644 sc->sc_smw.smw_tickle = tcotimer_tickle; 645 if (sc->sc_has_rcba) 646 period = LPCIB_TCOTIMER2_MAX_TICK; 647 else 648 period = LPCIB_TCOTIMER_MAX_TICK; 649 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 650 651 if (sysmon_wdog_register(&sc->sc_smw)) { 652 aprint_error_dev(self, "unable to register TCO timer" 653 "as a sysmon watchdog device.\n"); 654 return; 655 } 656 657 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 658 } 659 660 static int 661 tcotimer_unconfigure(device_t self, int flags) 662 { 663 struct lpcib_softc *sc = device_private(self); 664 int rc; 665 666 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 667 if (rc == ERESTART) 668 rc = EINTR; 669 return rc; 670 } 671 672 /* Explicitly stop the TCO timer. */ 673 tcotimer_stop(sc); 674 675 /* XXX Set No Reboot? */ 676 677 return 0; 678 } 679 680 681 /* 682 * Sysmon watchdog callbacks. 683 */ 684 static int 685 tcotimer_setmode(struct sysmon_wdog *smw) 686 { 687 struct lpcib_softc *sc = smw->smw_cookie; 688 unsigned int period; 689 uint16_t ich6period = 0; 690 uint8_t ich5period = 0; 691 692 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 693 /* Stop the TCO timer. */ 694 tcotimer_stop(sc); 695 } else { 696 /* 697 * ICH6 or newer are limited to 2s min and 613s max. 698 * ICH5 or older are limited to 4s min and 39s max. 699 */ 700 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 701 if (sc->sc_has_rcba) { 702 if (period < LPCIB_TCOTIMER2_MIN_TICK || 703 period > LPCIB_TCOTIMER2_MAX_TICK) 704 return EINVAL; 705 } else { 706 if (period < LPCIB_TCOTIMER_MIN_TICK || 707 period > LPCIB_TCOTIMER_MAX_TICK) 708 return EINVAL; 709 } 710 711 /* Stop the TCO timer, */ 712 tcotimer_stop(sc); 713 714 /* set the timeout, */ 715 if (sc->sc_has_rcba) { 716 /* ICH6 or newer */ 717 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 718 LPCIB_TCO_TMR2); 719 ich6period &= 0xfc00; 720 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 721 LPCIB_TCO_TMR2, ich6period | period); 722 } else { 723 /* ICH5 or older */ 724 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 725 LPCIB_TCO_TMR); 726 ich5period &= 0xc0; 727 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 728 LPCIB_TCO_TMR, ich5period | period); 729 } 730 731 /* and start/reload the timer. */ 732 tcotimer_start(sc); 733 tcotimer_tickle(smw); 734 } 735 736 return 0; 737 } 738 739 static int 740 tcotimer_tickle(struct sysmon_wdog *smw) 741 { 742 struct lpcib_softc *sc = smw->smw_cookie; 743 744 /* any value is allowed */ 745 if (sc->sc_has_rcba) 746 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 747 else 748 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 749 750 return 0; 751 } 752 753 static void 754 tcotimer_stop(struct lpcib_softc *sc) 755 { 756 uint16_t ioreg; 757 758 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 759 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 760 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 761 } 762 763 static void 764 tcotimer_start(struct lpcib_softc *sc) 765 { 766 uint16_t ioreg; 767 768 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 769 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 770 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 771 } 772 773 static void 774 tcotimer_status_reset(struct lpcib_softc *sc) 775 { 776 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 777 LPCIB_TCO1_STS_TIMEOUT); 778 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 779 LPCIB_TCO2_STS_BOOT_STS); 780 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 781 LPCIB_TCO2_STS_SECONDS_TO_STS); 782 } 783 784 /* 785 * Clear the No Reboot (NR) bit, this enables reboots when the timer 786 * reaches the timeout for the second time. 787 */ 788 static int 789 tcotimer_disable_noreboot(device_t self) 790 { 791 struct lpcib_softc *sc = device_private(self); 792 793 if (sc->sc_has_rcba) { 794 uint32_t status; 795 796 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 797 LPCIB_GCS_OFFSET); 798 status &= ~LPCIB_GCS_NO_REBOOT; 799 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 800 LPCIB_GCS_OFFSET, status); 801 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 802 LPCIB_GCS_OFFSET); 803 if (status & LPCIB_GCS_NO_REBOOT) 804 goto error; 805 } else { 806 pcireg_t pcireg; 807 808 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 809 LPCIB_PCI_GEN_STA); 810 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 811 /* TCO timeout reset is disabled; try to enable it */ 812 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 813 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 814 LPCIB_PCI_GEN_STA, pcireg); 815 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 816 goto error; 817 } 818 } 819 820 return 0; 821 error: 822 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 823 "hope SMBIOS properly handles it.\n"); 824 return EINVAL; 825 } 826 827 828 /* 829 * Intel ICH SpeedStep support. 830 */ 831 #define SS_READ(sc, reg) \ 832 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 833 #define SS_WRITE(sc, reg, val) \ 834 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 835 836 /* 837 * Linux driver says that SpeedStep on older chipsets cause 838 * lockups on Dell Inspiron 8000 and 8100. 839 * It should also not be enabled on systems with the 82855GM 840 * Hub, which typically have an EST-enabled CPU. 841 */ 842 static int 843 speedstep_bad_hb_check(const struct pci_attach_args *pa) 844 { 845 846 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 847 PCI_REVISION(pa->pa_class) < 5) 848 return 1; 849 850 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 851 return 1; 852 853 return 0; 854 } 855 856 static void 857 speedstep_configure(device_t self) 858 { 859 struct lpcib_softc *sc = device_private(self); 860 const struct sysctlnode *node, *ssnode; 861 int rv; 862 863 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 864 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 865 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 866 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 867 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 868 pcireg_t pmcon; 869 870 /* Enable SpeedStep if it isn't already enabled. */ 871 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 872 LPCIB_PCI_GEN_PMCON_1); 873 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 874 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 875 LPCIB_PCI_GEN_PMCON_1, 876 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 877 878 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 879 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 880 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 881 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 882 goto err; 883 884 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 885 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 886 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 887 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 888 CTL_EOL)) != 0) 889 goto err; 890 891 /* XXX save the sc for IO tag/handle */ 892 speedstep_cookie = sc; 893 aprint_verbose_dev(self, "SpeedStep enabled\n"); 894 } 895 896 return; 897 898 err: 899 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 900 } 901 902 static void 903 speedstep_unconfigure(device_t self) 904 { 905 struct lpcib_softc *sc = device_private(self); 906 907 sysctl_teardown(&sc->sc_log); 908 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 909 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 910 911 speedstep_cookie = NULL; 912 } 913 914 /* 915 * get/set the SpeedStep state: 0 == low power, 1 == high power. 916 */ 917 static int 918 speedstep_sysctl_helper(SYSCTLFN_ARGS) 919 { 920 struct sysctlnode node; 921 struct lpcib_softc *sc = speedstep_cookie; 922 uint8_t state, state2; 923 int ostate, nstate, s, error = 0; 924 925 /* 926 * We do the dance with spl's to avoid being at high ipl during 927 * sysctl_lookup() which can both copyin and copyout. 928 */ 929 s = splserial(); 930 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 931 splx(s); 932 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 933 ostate = 1; 934 else 935 ostate = 0; 936 nstate = ostate; 937 938 node = *rnode; 939 node.sysctl_data = &nstate; 940 941 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 942 if (error || newp == NULL) 943 goto out; 944 945 /* Only two states are available */ 946 if (nstate != 0 && nstate != 1) { 947 error = EINVAL; 948 goto out; 949 } 950 951 s = splserial(); 952 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 953 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 954 ostate = 1; 955 else 956 ostate = 0; 957 958 if (ostate != nstate) { 959 uint8_t cntl; 960 961 if (nstate == 0) 962 state2 |= LPCIB_PM_SS_STATE_LOW; 963 else 964 state2 &= ~LPCIB_PM_SS_STATE_LOW; 965 966 /* 967 * Must disable bus master arbitration during the change. 968 */ 969 cntl = SS_READ(sc, LPCIB_PM_CTRL); 970 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 971 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 972 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 973 } 974 splx(s); 975 out: 976 return error; 977 } 978 979 static void 980 lpcib_hpet_configure(device_t self) 981 { 982 struct lpcib_softc *sc = device_private(self); 983 struct lpcib_hpet_attach_args arg; 984 uint32_t hpet_reg, val; 985 986 if (sc->sc_has_ich5_hpet) { 987 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 988 LPCIB_PCI_GEN_CNTL); 989 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 990 case LPCIB_ICH5_HPTC_0000: 991 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 992 break; 993 case LPCIB_ICH5_HPTC_1000: 994 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 995 break; 996 case LPCIB_ICH5_HPTC_2000: 997 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 998 break; 999 case LPCIB_ICH5_HPTC_3000: 1000 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 1001 break; 1002 default: 1003 return; 1004 } 1005 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 1006 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1007 LPCIB_PCI_GEN_CNTL, val); 1008 } else if (sc->sc_has_rcba) { 1009 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 1010 LPCIB_RCBA_HPTC); 1011 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 1012 case LPCIB_RCBA_HPTC_0000: 1013 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 1014 break; 1015 case LPCIB_RCBA_HPTC_1000: 1016 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 1017 break; 1018 case LPCIB_RCBA_HPTC_2000: 1019 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1020 break; 1021 case LPCIB_RCBA_HPTC_3000: 1022 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1023 break; 1024 default: 1025 return; 1026 } 1027 val |= LPCIB_RCBA_HPTC_EN; 1028 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1029 val); 1030 } else { 1031 /* No HPET here */ 1032 return; 1033 } 1034 1035 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1036 arg.hpet_reg = hpet_reg; 1037 1038 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1039 } 1040 1041 static int 1042 lpcib_hpet_unconfigure(device_t self, int flags) 1043 { 1044 struct lpcib_softc *sc = device_private(self); 1045 int rc; 1046 1047 if (sc->sc_hpetbus != NULL && 1048 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1049 return rc; 1050 1051 return 0; 1052 } 1053 1054 #if NGPIO > 0 1055 static void 1056 lpcib_gpio_configure(device_t self) 1057 { 1058 struct lpcib_softc *sc = device_private(self); 1059 struct gpiobus_attach_args gba; 1060 pcireg_t gpio_cntl; 1061 uint32_t use, io, bit; 1062 int pin, shift, base_reg, cntl_reg, reg; 1063 int rv; 1064 1065 /* this implies ICH >= 6, and thus different mapreg */ 1066 if (sc->sc_has_rcba) { 1067 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1068 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1069 } else { 1070 base_reg = LPCIB_PCI_GPIO_BASE; 1071 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1072 } 1073 1074 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1075 cntl_reg); 1076 1077 /* Is GPIO enabled? */ 1078 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1079 return; 1080 /* 1081 * The GPIO_BASE register is alike PCI BAR but not completely 1082 * compatible with it. The PMBASE define the base address and the type 1083 * but not describe the size. 1084 */ 1085 rv = pci_mapreg_submap(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1086 LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1087 NULL, &sc->sc_gpio_ios); 1088 if (rv != 0) { 1089 aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv); 1090 return; 1091 } 1092 1093 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1094 1095 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1096 sc->sc_gpio_pins[pin].pin_num = pin; 1097 1098 /* Read initial state */ 1099 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1100 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1101 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1102 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1103 shift = pin % 32; 1104 bit = __BIT(shift); 1105 1106 if ((use & bit) != 0) { 1107 sc->sc_gpio_pins[pin].pin_caps = 1108 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1109 if (pin < 32) 1110 sc->sc_gpio_pins[pin].pin_caps |= 1111 GPIO_PIN_PULSATE; 1112 if ((io & bit) != 0) 1113 sc->sc_gpio_pins[pin].pin_flags = 1114 GPIO_PIN_INPUT; 1115 else 1116 sc->sc_gpio_pins[pin].pin_flags = 1117 GPIO_PIN_OUTPUT; 1118 } else 1119 sc->sc_gpio_pins[pin].pin_caps = 0; 1120 1121 if (lpcib_gpio_pin_read(sc, pin) == 0) 1122 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1123 else 1124 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1125 1126 } 1127 1128 /* Create controller tag */ 1129 sc->sc_gpio_gc.gp_cookie = sc; 1130 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1131 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1132 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1133 1134 memset(&gba, 0, sizeof(gba)); 1135 1136 gba.gba_gc = &sc->sc_gpio_gc; 1137 gba.gba_pins = sc->sc_gpio_pins; 1138 gba.gba_npins = LPCIB_GPIO_NPINS; 1139 1140 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1141 } 1142 1143 static int 1144 lpcib_gpio_unconfigure(device_t self, int flags) 1145 { 1146 struct lpcib_softc *sc = device_private(self); 1147 int rc; 1148 1149 if (sc->sc_gpiobus != NULL && 1150 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1151 return rc; 1152 1153 mutex_destroy(&sc->sc_gpio_mtx); 1154 1155 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1156 1157 return 0; 1158 } 1159 1160 static int 1161 lpcib_gpio_pin_read(void *arg, int pin) 1162 { 1163 struct lpcib_softc *sc = arg; 1164 uint32_t data; 1165 int reg, shift; 1166 1167 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1168 shift = pin % 32; 1169 1170 mutex_enter(&sc->sc_gpio_mtx); 1171 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1172 mutex_exit(&sc->sc_gpio_mtx); 1173 1174 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1175 } 1176 1177 static void 1178 lpcib_gpio_pin_write(void *arg, int pin, int value) 1179 { 1180 struct lpcib_softc *sc = arg; 1181 uint32_t data; 1182 int reg, shift; 1183 1184 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1185 shift = pin % 32; 1186 1187 mutex_enter(&sc->sc_gpio_mtx); 1188 1189 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1190 1191 if(value) 1192 data |= __BIT(shift); 1193 else 1194 data &= ~__BIT(shift); 1195 1196 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1197 1198 mutex_exit(&sc->sc_gpio_mtx); 1199 } 1200 1201 static void 1202 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1203 { 1204 struct lpcib_softc *sc = arg; 1205 uint32_t data; 1206 int reg, shift; 1207 1208 shift = pin % 32; 1209 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1210 1211 mutex_enter(&sc->sc_gpio_mtx); 1212 1213 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1214 1215 if (flags & GPIO_PIN_OUTPUT) 1216 data &= ~__BIT(shift); 1217 1218 if (flags & GPIO_PIN_INPUT) 1219 data |= __BIT(shift); 1220 1221 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1222 1223 1224 if (pin < 32) { 1225 reg = LPCIB_GPIO_GPO_BLINK; 1226 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1227 1228 if (flags & GPIO_PIN_PULSATE) 1229 data |= __BIT(shift); 1230 else 1231 data &= ~__BIT(shift); 1232 1233 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1234 } 1235 1236 mutex_exit(&sc->sc_gpio_mtx); 1237 } 1238 #endif 1239 1240 #if NFWHRNG > 0 1241 static void 1242 lpcib_fwh_configure(device_t self) 1243 { 1244 struct lpcib_softc *sc; 1245 pcireg_t pr; 1246 1247 sc = device_private(self); 1248 1249 if (sc->sc_has_rcba) { 1250 /* 1251 * Very unlikely to find a 82802 on a ICH6 or newer. 1252 * Also the write enable register moved at that point. 1253 */ 1254 return; 1255 } else { 1256 /* Enable FWH write to identify FWH. */ 1257 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1258 LPCIB_PCI_BIOS_CNTL); 1259 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1260 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1261 } 1262 1263 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1264 1265 /* restore previous write enable setting */ 1266 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1267 LPCIB_PCI_BIOS_CNTL, pr); 1268 } 1269 1270 static int 1271 lpcib_fwh_unconfigure(device_t self, int flags) 1272 { 1273 struct lpcib_softc *sc = device_private(self); 1274 int rc; 1275 1276 if (sc->sc_fwhbus != NULL && 1277 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1278 return rc; 1279 1280 return 0; 1281 } 1282 #endif 1283
Indexes created Wed Oct 01 18:09:54 GMT 2025