ichlpcib.c revision 1.43.4.2
1 /* $NetBSD: ichlpcib.c,v 1.43.4.2 2015/01/26 16:16:11 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.43.4.2 2015/01/26 16:16:11 martin Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z68_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 264 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 265 #if 0 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 270 #endif 271 272 { 0, 0, 0, 0 }, 273 }; 274 275 /* 276 * Autoconf callbacks. 277 */ 278 static int 279 lpcibmatch(device_t parent, cfdata_t match, void *aux) 280 { 281 struct pci_attach_args *pa = aux; 282 struct lpcib_device *lpcib_dev; 283 284 /* We are ISA bridge, of course */ 285 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 286 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 287 return 0; 288 289 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 290 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 291 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 292 return 10; 293 } 294 295 return 0; 296 } 297 298 static void 299 lpcibattach(device_t parent, device_t self, void *aux) 300 { 301 struct pci_attach_args *pa = aux; 302 struct lpcib_softc *sc = device_private(self); 303 struct lpcib_device *lpcib_dev; 304 pcireg_t pmbase; 305 306 sc->sc_pa = *pa; 307 308 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 309 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 310 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 311 continue; 312 sc->sc_has_rcba = lpcib_dev->has_rcba; 313 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 314 break; 315 } 316 317 pcibattach(parent, self, aux); 318 319 /* 320 * Part of our I/O registers are used as ACPI PM regs. 321 * Since our ACPI subsystem accesses the I/O space directly so far, 322 * we do not have to bother bus_space I/O map confliction. 323 * 324 * The PMBASE register is alike PCI BAR but not completely compatible 325 * with it. The PMBASE define the base address and the type but 326 * not describe the size. The value of the register may be lower 327 * than LPCIB_PCI_PM_SIZE. It makes impossible to use 328 * pci_mapreg_submap() because the function does range check. 329 */ 330 sc->sc_iot = pa->pa_iot; 331 pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE); 332 if (bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(pmbase), 333 LPCIB_PCI_PM_SIZE, 0, &sc->sc_ioh) != 0) { 334 aprint_error_dev(self, 335 "can't map power management i/o space\n"); 336 return; 337 } 338 339 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 340 LPCIB_PCI_GEN_PMCON_1); 341 342 /* For ICH6 and later, always enable RCBA */ 343 if (sc->sc_has_rcba) { 344 pcireg_t rcba; 345 346 sc->sc_rcbat = sc->sc_pa.pa_memt; 347 348 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 349 LPCIB_RCBA); 350 if ((rcba & LPCIB_RCBA_EN) == 0) { 351 aprint_error_dev(self, "RCBA is not enabled\n"); 352 return; 353 } 354 rcba &= ~LPCIB_RCBA_EN; 355 356 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 357 &sc->sc_rcbah)) { 358 aprint_error_dev(self, "RCBA could not be mapped\n"); 359 return; 360 } 361 } 362 363 /* Set up the power management timer. */ 364 pmtimer_configure(self); 365 366 /* Set up the TCO (watchdog). */ 367 tcotimer_configure(self); 368 369 /* Set up SpeedStep. */ 370 speedstep_configure(self); 371 372 /* Set up HPET. */ 373 lpcib_hpet_configure(self); 374 375 #if NGPIO > 0 376 /* Set up GPIO */ 377 lpcib_gpio_configure(self); 378 #endif 379 380 #if NFWHRNG > 0 381 lpcib_fwh_configure(self); 382 #endif 383 384 /* Install power handler */ 385 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 386 lpcib_shutdown)) 387 aprint_error_dev(self, "couldn't establish power handler\n"); 388 } 389 390 static void 391 lpcibchilddet(device_t self, device_t child) 392 { 393 struct lpcib_softc *sc = device_private(self); 394 uint32_t val; 395 396 #if NFWHRNG > 0 397 if (sc->sc_fwhbus == child) { 398 sc->sc_fwhbus = NULL; 399 return; 400 } 401 #endif 402 #if NGPIO > 0 403 if (sc->sc_gpiobus == child) { 404 sc->sc_gpiobus = NULL; 405 return; 406 } 407 #endif 408 if (sc->sc_hpetbus != child) { 409 pcibchilddet(self, child); 410 return; 411 } 412 sc->sc_hpetbus = NULL; 413 if (sc->sc_has_ich5_hpet) { 414 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 415 LPCIB_PCI_GEN_CNTL); 416 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 417 case LPCIB_ICH5_HPTC_0000: 418 case LPCIB_ICH5_HPTC_1000: 419 case LPCIB_ICH5_HPTC_2000: 420 case LPCIB_ICH5_HPTC_3000: 421 break; 422 default: 423 return; 424 } 425 val &= ~LPCIB_ICH5_HPTC_EN; 426 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 427 LPCIB_PCI_GEN_CNTL, val); 428 } else if (sc->sc_has_rcba) { 429 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 430 LPCIB_RCBA_HPTC); 431 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 432 case LPCIB_RCBA_HPTC_0000: 433 case LPCIB_RCBA_HPTC_1000: 434 case LPCIB_RCBA_HPTC_2000: 435 case LPCIB_RCBA_HPTC_3000: 436 break; 437 default: 438 return; 439 } 440 val &= ~LPCIB_RCBA_HPTC_EN; 441 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 442 val); 443 } 444 } 445 446 static int 447 lpcibrescan(device_t self, const char *ifattr, const int *locators) 448 { 449 struct lpcib_softc *sc = device_private(self); 450 451 #if NFWHRNG > 0 452 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 453 lpcib_fwh_configure(self); 454 #endif 455 456 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 457 lpcib_hpet_configure(self); 458 459 #if NGPIO > 0 460 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 461 lpcib_gpio_configure(self); 462 #endif 463 464 return pcibrescan(self, ifattr, locators); 465 } 466 467 static int 468 lpcibdetach(device_t self, int flags) 469 { 470 struct lpcib_softc *sc = device_private(self); 471 int rc; 472 473 pmf_device_deregister(self); 474 475 #if NFWHRNG > 0 476 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 477 return rc; 478 #endif 479 480 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 481 return rc; 482 483 #if NGPIO > 0 484 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 485 return rc; 486 #endif 487 488 /* Set up SpeedStep. */ 489 speedstep_unconfigure(self); 490 491 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 492 return rc; 493 494 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 495 return rc; 496 497 if (sc->sc_has_rcba) 498 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 499 500 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 501 502 return pcibdetach(self, flags); 503 } 504 505 static bool 506 lpcib_shutdown(device_t dv, int howto) 507 { 508 struct lpcib_softc *sc = device_private(dv); 509 510 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 511 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 512 513 return true; 514 } 515 516 static bool 517 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 518 { 519 struct lpcib_softc *sc = device_private(dv); 520 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 521 pcitag_t tag = sc->sc_pcib.sc_tag; 522 523 /* capture PIRQ routing control registers */ 524 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 525 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 526 527 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 528 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 529 530 if (sc->sc_has_rcba) { 531 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 532 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 533 LPCIB_RCBA_HPTC); 534 } else if (sc->sc_has_ich5_hpet) { 535 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 536 } 537 538 return true; 539 } 540 541 static bool 542 lpcib_resume(device_t dv, const pmf_qual_t *qual) 543 { 544 struct lpcib_softc *sc = device_private(dv); 545 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 546 pcitag_t tag = sc->sc_pcib.sc_tag; 547 548 /* restore PIRQ routing control registers */ 549 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 550 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 551 552 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 553 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 554 555 if (sc->sc_has_rcba) { 556 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 557 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 558 sc->sc_hpet_reg); 559 } else if (sc->sc_has_ich5_hpet) { 560 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 561 } 562 563 return true; 564 } 565 566 /* 567 * Initialize the power management timer. 568 */ 569 static void 570 pmtimer_configure(device_t self) 571 { 572 struct lpcib_softc *sc = device_private(self); 573 pcireg_t control; 574 575 /* 576 * Check if power management I/O space is enabled and enable the ACPI_EN 577 * bit if it's disabled. 578 */ 579 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 580 LPCIB_PCI_ACPI_CNTL); 581 sc->sc_acpi_cntl = control; 582 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 583 control |= LPCIB_PCI_ACPI_CNTL_EN; 584 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 585 LPCIB_PCI_ACPI_CNTL, control); 586 } 587 588 /* Attach our PM timer with the generic acpipmtimer function */ 589 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 590 LPCIB_PM1_TMR, 0); 591 } 592 593 static int 594 pmtimer_unconfigure(device_t self, int flags) 595 { 596 struct lpcib_softc *sc = device_private(self); 597 int rc; 598 599 if (sc->sc_pmtimer != NULL && 600 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 601 return rc; 602 603 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 604 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 605 606 return 0; 607 } 608 609 /* 610 * Initialize the watchdog timer. 611 */ 612 static void 613 tcotimer_configure(device_t self) 614 { 615 struct lpcib_softc *sc = device_private(self); 616 uint32_t ioreg; 617 unsigned int period; 618 619 /* Explicitly stop the TCO timer. */ 620 tcotimer_stop(sc); 621 622 /* 623 * Enable TCO timeout SMI only if the hardware reset does not 624 * work. We don't know what the SMBIOS does. 625 */ 626 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 627 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 628 629 /* 630 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 631 * in the SMI_EN register is the last chance. 632 */ 633 if (tcotimer_disable_noreboot(self)) { 634 ioreg |= LPCIB_SMI_EN_TCO_EN; 635 } 636 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 637 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 638 } 639 640 /* Reset the watchdog status registers. */ 641 tcotimer_status_reset(sc); 642 643 /* 644 * Register the driver with the sysmon watchdog framework. 645 */ 646 sc->sc_smw.smw_name = device_xname(self); 647 sc->sc_smw.smw_cookie = sc; 648 sc->sc_smw.smw_setmode = tcotimer_setmode; 649 sc->sc_smw.smw_tickle = tcotimer_tickle; 650 if (sc->sc_has_rcba) 651 period = LPCIB_TCOTIMER2_MAX_TICK; 652 else 653 period = LPCIB_TCOTIMER_MAX_TICK; 654 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 655 656 if (sysmon_wdog_register(&sc->sc_smw)) { 657 aprint_error_dev(self, "unable to register TCO timer" 658 "as a sysmon watchdog device.\n"); 659 return; 660 } 661 662 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 663 } 664 665 static int 666 tcotimer_unconfigure(device_t self, int flags) 667 { 668 struct lpcib_softc *sc = device_private(self); 669 int rc; 670 671 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 672 if (rc == ERESTART) 673 rc = EINTR; 674 return rc; 675 } 676 677 /* Explicitly stop the TCO timer. */ 678 tcotimer_stop(sc); 679 680 /* XXX Set No Reboot? */ 681 682 return 0; 683 } 684 685 686 /* 687 * Sysmon watchdog callbacks. 688 */ 689 static int 690 tcotimer_setmode(struct sysmon_wdog *smw) 691 { 692 struct lpcib_softc *sc = smw->smw_cookie; 693 unsigned int period; 694 uint16_t ich6period = 0; 695 uint8_t ich5period = 0; 696 697 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 698 /* Stop the TCO timer. */ 699 tcotimer_stop(sc); 700 } else { 701 /* 702 * ICH6 or newer are limited to 2s min and 613s max. 703 * ICH5 or older are limited to 4s min and 39s max. 704 */ 705 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 706 if (sc->sc_has_rcba) { 707 if (period < LPCIB_TCOTIMER2_MIN_TICK || 708 period > LPCIB_TCOTIMER2_MAX_TICK) 709 return EINVAL; 710 } else { 711 if (period < LPCIB_TCOTIMER_MIN_TICK || 712 period > LPCIB_TCOTIMER_MAX_TICK) 713 return EINVAL; 714 } 715 716 /* Stop the TCO timer, */ 717 tcotimer_stop(sc); 718 719 /* set the timeout, */ 720 if (sc->sc_has_rcba) { 721 /* ICH6 or newer */ 722 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 723 LPCIB_TCO_TMR2); 724 ich6period &= 0xfc00; 725 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 726 LPCIB_TCO_TMR2, ich6period | period); 727 } else { 728 /* ICH5 or older */ 729 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 730 LPCIB_TCO_TMR); 731 ich5period &= 0xc0; 732 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 733 LPCIB_TCO_TMR, ich5period | period); 734 } 735 736 /* and start/reload the timer. */ 737 tcotimer_start(sc); 738 tcotimer_tickle(smw); 739 } 740 741 return 0; 742 } 743 744 static int 745 tcotimer_tickle(struct sysmon_wdog *smw) 746 { 747 struct lpcib_softc *sc = smw->smw_cookie; 748 749 /* any value is allowed */ 750 if (sc->sc_has_rcba) 751 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 752 else 753 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 754 755 return 0; 756 } 757 758 static void 759 tcotimer_stop(struct lpcib_softc *sc) 760 { 761 uint16_t ioreg; 762 763 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 764 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 765 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 766 } 767 768 static void 769 tcotimer_start(struct lpcib_softc *sc) 770 { 771 uint16_t ioreg; 772 773 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 774 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 775 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 776 } 777 778 static void 779 tcotimer_status_reset(struct lpcib_softc *sc) 780 { 781 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 782 LPCIB_TCO1_STS_TIMEOUT); 783 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 784 LPCIB_TCO2_STS_BOOT_STS); 785 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 786 LPCIB_TCO2_STS_SECONDS_TO_STS); 787 } 788 789 /* 790 * Clear the No Reboot (NR) bit, this enables reboots when the timer 791 * reaches the timeout for the second time. 792 */ 793 static int 794 tcotimer_disable_noreboot(device_t self) 795 { 796 struct lpcib_softc *sc = device_private(self); 797 798 if (sc->sc_has_rcba) { 799 uint32_t status; 800 801 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 802 LPCIB_GCS_OFFSET); 803 status &= ~LPCIB_GCS_NO_REBOOT; 804 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 805 LPCIB_GCS_OFFSET, status); 806 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 807 LPCIB_GCS_OFFSET); 808 if (status & LPCIB_GCS_NO_REBOOT) 809 goto error; 810 } else { 811 pcireg_t pcireg; 812 813 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 814 LPCIB_PCI_GEN_STA); 815 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 816 /* TCO timeout reset is disabled; try to enable it */ 817 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 818 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 819 LPCIB_PCI_GEN_STA, pcireg); 820 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 821 goto error; 822 } 823 } 824 825 return 0; 826 error: 827 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 828 "hope SMBIOS properly handles it.\n"); 829 return EINVAL; 830 } 831 832 833 /* 834 * Intel ICH SpeedStep support. 835 */ 836 #define SS_READ(sc, reg) \ 837 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 838 #define SS_WRITE(sc, reg, val) \ 839 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 840 841 /* 842 * Linux driver says that SpeedStep on older chipsets cause 843 * lockups on Dell Inspiron 8000 and 8100. 844 * It should also not be enabled on systems with the 82855GM 845 * Hub, which typically have an EST-enabled CPU. 846 */ 847 static int 848 speedstep_bad_hb_check(const struct pci_attach_args *pa) 849 { 850 851 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 852 PCI_REVISION(pa->pa_class) < 5) 853 return 1; 854 855 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 856 return 1; 857 858 return 0; 859 } 860 861 static void 862 speedstep_configure(device_t self) 863 { 864 struct lpcib_softc *sc = device_private(self); 865 const struct sysctlnode *node, *ssnode; 866 int rv; 867 868 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 869 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 870 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 871 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 872 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 873 pcireg_t pmcon; 874 875 /* Enable SpeedStep if it isn't already enabled. */ 876 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 877 LPCIB_PCI_GEN_PMCON_1); 878 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 879 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 880 LPCIB_PCI_GEN_PMCON_1, 881 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 882 883 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 884 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 885 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 886 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 887 goto err; 888 889 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 890 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 891 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 892 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 893 CTL_EOL)) != 0) 894 goto err; 895 896 /* XXX save the sc for IO tag/handle */ 897 speedstep_cookie = sc; 898 aprint_verbose_dev(self, "SpeedStep enabled\n"); 899 } 900 901 return; 902 903 err: 904 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 905 } 906 907 static void 908 speedstep_unconfigure(device_t self) 909 { 910 struct lpcib_softc *sc = device_private(self); 911 912 sysctl_teardown(&sc->sc_log); 913 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 914 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 915 916 speedstep_cookie = NULL; 917 } 918 919 /* 920 * get/set the SpeedStep state: 0 == low power, 1 == high power. 921 */ 922 static int 923 speedstep_sysctl_helper(SYSCTLFN_ARGS) 924 { 925 struct sysctlnode node; 926 struct lpcib_softc *sc = speedstep_cookie; 927 uint8_t state, state2; 928 int ostate, nstate, s, error = 0; 929 930 /* 931 * We do the dance with spl's to avoid being at high ipl during 932 * sysctl_lookup() which can both copyin and copyout. 933 */ 934 s = splserial(); 935 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 936 splx(s); 937 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 938 ostate = 1; 939 else 940 ostate = 0; 941 nstate = ostate; 942 943 node = *rnode; 944 node.sysctl_data = &nstate; 945 946 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 947 if (error || newp == NULL) 948 goto out; 949 950 /* Only two states are available */ 951 if (nstate != 0 && nstate != 1) { 952 error = EINVAL; 953 goto out; 954 } 955 956 s = splserial(); 957 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 958 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 959 ostate = 1; 960 else 961 ostate = 0; 962 963 if (ostate != nstate) { 964 uint8_t cntl; 965 966 if (nstate == 0) 967 state2 |= LPCIB_PM_SS_STATE_LOW; 968 else 969 state2 &= ~LPCIB_PM_SS_STATE_LOW; 970 971 /* 972 * Must disable bus master arbitration during the change. 973 */ 974 cntl = SS_READ(sc, LPCIB_PM_CTRL); 975 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 976 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 977 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 978 } 979 splx(s); 980 out: 981 return error; 982 } 983 984 static void 985 lpcib_hpet_configure(device_t self) 986 { 987 struct lpcib_softc *sc = device_private(self); 988 struct lpcib_hpet_attach_args arg; 989 uint32_t hpet_reg, val; 990 991 if (sc->sc_has_ich5_hpet) { 992 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 993 LPCIB_PCI_GEN_CNTL); 994 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 995 case LPCIB_ICH5_HPTC_0000: 996 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 997 break; 998 case LPCIB_ICH5_HPTC_1000: 999 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 1000 break; 1001 case LPCIB_ICH5_HPTC_2000: 1002 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 1003 break; 1004 case LPCIB_ICH5_HPTC_3000: 1005 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 1006 break; 1007 default: 1008 return; 1009 } 1010 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 1011 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1012 LPCIB_PCI_GEN_CNTL, val); 1013 } else if (sc->sc_has_rcba) { 1014 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 1015 LPCIB_RCBA_HPTC); 1016 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 1017 case LPCIB_RCBA_HPTC_0000: 1018 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 1019 break; 1020 case LPCIB_RCBA_HPTC_1000: 1021 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 1022 break; 1023 case LPCIB_RCBA_HPTC_2000: 1024 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1025 break; 1026 case LPCIB_RCBA_HPTC_3000: 1027 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1028 break; 1029 default: 1030 return; 1031 } 1032 val |= LPCIB_RCBA_HPTC_EN; 1033 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1034 val); 1035 } else { 1036 /* No HPET here */ 1037 return; 1038 } 1039 1040 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1041 arg.hpet_reg = hpet_reg; 1042 1043 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1044 } 1045 1046 static int 1047 lpcib_hpet_unconfigure(device_t self, int flags) 1048 { 1049 struct lpcib_softc *sc = device_private(self); 1050 int rc; 1051 1052 if (sc->sc_hpetbus != NULL && 1053 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1054 return rc; 1055 1056 return 0; 1057 } 1058 1059 #if NGPIO > 0 1060 static void 1061 lpcib_gpio_configure(device_t self) 1062 { 1063 struct lpcib_softc *sc = device_private(self); 1064 struct gpiobus_attach_args gba; 1065 pcireg_t gpio_cntl; 1066 uint32_t use, io, bit; 1067 int pin, shift, base_reg, cntl_reg, reg; 1068 int rv; 1069 1070 /* this implies ICH >= 6, and thus different mapreg */ 1071 if (sc->sc_has_rcba) { 1072 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1073 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1074 } else { 1075 base_reg = LPCIB_PCI_GPIO_BASE; 1076 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1077 } 1078 1079 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1080 cntl_reg); 1081 1082 /* Is GPIO enabled? */ 1083 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1084 return; 1085 /* 1086 * The GPIO_BASE register is alike PCI BAR but not completely 1087 * compatible with it. The PMBASE define the base address and the type 1088 * but not describe the size. The value of the register may be lower 1089 * than LPCIB_PCI_GPIO_SIZE. It makes impossible to use 1090 * pci_mapreg_submap() because the function does range check. 1091 */ 1092 sc->sc_gpio_iot = sc->sc_pa.pa_iot; 1093 reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg); 1094 rv = bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(reg), 1095 LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_ioh); 1096 if (rv != 0) { 1097 aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv); 1098 return; 1099 } 1100 1101 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1102 1103 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1104 sc->sc_gpio_pins[pin].pin_num = pin; 1105 1106 /* Read initial state */ 1107 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1108 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1109 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1110 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1111 shift = pin % 32; 1112 bit = __BIT(shift); 1113 1114 if ((use & bit) != 0) { 1115 sc->sc_gpio_pins[pin].pin_caps = 1116 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1117 if (pin < 32) 1118 sc->sc_gpio_pins[pin].pin_caps |= 1119 GPIO_PIN_PULSATE; 1120 if ((io & bit) != 0) 1121 sc->sc_gpio_pins[pin].pin_flags = 1122 GPIO_PIN_INPUT; 1123 else 1124 sc->sc_gpio_pins[pin].pin_flags = 1125 GPIO_PIN_OUTPUT; 1126 } else 1127 sc->sc_gpio_pins[pin].pin_caps = 0; 1128 1129 if (lpcib_gpio_pin_read(sc, pin) == 0) 1130 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1131 else 1132 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1133 1134 } 1135 1136 /* Create controller tag */ 1137 sc->sc_gpio_gc.gp_cookie = sc; 1138 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1139 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1140 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1141 1142 memset(&gba, 0, sizeof(gba)); 1143 1144 gba.gba_gc = &sc->sc_gpio_gc; 1145 gba.gba_pins = sc->sc_gpio_pins; 1146 gba.gba_npins = LPCIB_GPIO_NPINS; 1147 1148 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1149 } 1150 1151 static int 1152 lpcib_gpio_unconfigure(device_t self, int flags) 1153 { 1154 struct lpcib_softc *sc = device_private(self); 1155 int rc; 1156 1157 if (sc->sc_gpiobus != NULL && 1158 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1159 return rc; 1160 1161 mutex_destroy(&sc->sc_gpio_mtx); 1162 1163 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1164 1165 return 0; 1166 } 1167 1168 static int 1169 lpcib_gpio_pin_read(void *arg, int pin) 1170 { 1171 struct lpcib_softc *sc = arg; 1172 uint32_t data; 1173 int reg, shift; 1174 1175 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1176 shift = pin % 32; 1177 1178 mutex_enter(&sc->sc_gpio_mtx); 1179 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1180 mutex_exit(&sc->sc_gpio_mtx); 1181 1182 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1183 } 1184 1185 static void 1186 lpcib_gpio_pin_write(void *arg, int pin, int value) 1187 { 1188 struct lpcib_softc *sc = arg; 1189 uint32_t data; 1190 int reg, shift; 1191 1192 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1193 shift = pin % 32; 1194 1195 mutex_enter(&sc->sc_gpio_mtx); 1196 1197 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1198 1199 if(value) 1200 data |= __BIT(shift); 1201 else 1202 data &= ~__BIT(shift); 1203 1204 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1205 1206 mutex_exit(&sc->sc_gpio_mtx); 1207 } 1208 1209 static void 1210 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1211 { 1212 struct lpcib_softc *sc = arg; 1213 uint32_t data; 1214 int reg, shift; 1215 1216 shift = pin % 32; 1217 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1218 1219 mutex_enter(&sc->sc_gpio_mtx); 1220 1221 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1222 1223 if (flags & GPIO_PIN_OUTPUT) 1224 data &= ~__BIT(shift); 1225 1226 if (flags & GPIO_PIN_INPUT) 1227 data |= __BIT(shift); 1228 1229 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1230 1231 1232 if (pin < 32) { 1233 reg = LPCIB_GPIO_GPO_BLINK; 1234 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1235 1236 if (flags & GPIO_PIN_PULSATE) 1237 data |= __BIT(shift); 1238 else 1239 data &= ~__BIT(shift); 1240 1241 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1242 } 1243 1244 mutex_exit(&sc->sc_gpio_mtx); 1245 } 1246 #endif 1247 1248 #if NFWHRNG > 0 1249 static void 1250 lpcib_fwh_configure(device_t self) 1251 { 1252 struct lpcib_softc *sc; 1253 pcireg_t pr; 1254 1255 sc = device_private(self); 1256 1257 if (sc->sc_has_rcba) { 1258 /* 1259 * Very unlikely to find a 82802 on a ICH6 or newer. 1260 * Also the write enable register moved at that point. 1261 */ 1262 return; 1263 } else { 1264 /* Enable FWH write to identify FWH. */ 1265 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1266 LPCIB_PCI_BIOS_CNTL); 1267 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1268 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1269 } 1270 1271 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1272 1273 /* restore previous write enable setting */ 1274 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1275 LPCIB_PCI_BIOS_CNTL, pr); 1276 } 1277 1278 static int 1279 lpcib_fwh_unconfigure(device_t self, int flags) 1280 { 1281 struct lpcib_softc *sc = device_private(self); 1282 int rc; 1283 1284 if (sc->sc_fwhbus != NULL && 1285 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1286 return rc; 1287 1288 return 0; 1289 } 1290 #endif 1291
Indexes created Wed Oct 01 18:09:54 GMT 2025