ichlpcib.c revision 1.43.4.5.2.1
1 /* $NetBSD: ichlpcib.c,v 1.43.4.5.2.1 2017/01/18 08:46:26 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.43.4.5.2.1 2017/01/18 08:46:26 skrll Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z68_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H97_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z97_LPC, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X99_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X99_LPC_2, 1, 0 }, 264 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE5G_M_LPC_4, 1, 0 }, 265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE5G_M_LPC_7, 1, 0 }, 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 270 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_LPC, 1, 0 }, 272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCL_LPC, 1, 0 }, 273 #if 0 274 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 276 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 277 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 278 #endif 279 280 { 0, 0, 0, 0 }, 281 }; 282 283 /* 284 * Allow user to enable GPIO functionality if they really need it. The 285 * vast majority of systems with an ICH should not expose GPIO to the 286 * kernel or user. In at least one instance the gpio_resume() handler 287 * on ICH GPIO was found to sabotage S3 suspend/resume. 288 */ 289 int ichlpcib_gpio_disable = 1; 290 291 /* 292 * Autoconf callbacks. 293 */ 294 static int 295 lpcibmatch(device_t parent, cfdata_t match, void *aux) 296 { 297 struct pci_attach_args *pa = aux; 298 struct lpcib_device *lpcib_dev; 299 300 /* We are ISA bridge, of course */ 301 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 302 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 303 return 0; 304 305 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 306 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 307 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 308 return 10; 309 } 310 311 return 0; 312 } 313 314 static void 315 lpcibattach(device_t parent, device_t self, void *aux) 316 { 317 struct pci_attach_args *pa = aux; 318 struct lpcib_softc *sc = device_private(self); 319 struct lpcib_device *lpcib_dev; 320 pcireg_t pmbase; 321 322 sc->sc_pa = *pa; 323 324 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 325 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 326 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 327 continue; 328 sc->sc_has_rcba = lpcib_dev->has_rcba; 329 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 330 break; 331 } 332 333 pcibattach(parent, self, aux); 334 335 /* 336 * Part of our I/O registers are used as ACPI PM regs. 337 * Since our ACPI subsystem accesses the I/O space directly so far, 338 * we do not have to bother bus_space I/O map confliction. 339 * 340 * The PMBASE register is alike PCI BAR but not completely compatible 341 * with it. The PMBASE define the base address and the type but 342 * not describe the size. The value of the register may be lower 343 * than LPCIB_PCI_PM_SIZE. It makes impossible to use 344 * pci_mapreg_submap() because the function does range check. 345 */ 346 sc->sc_iot = pa->pa_iot; 347 pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE); 348 if (bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(pmbase), 349 LPCIB_PCI_PM_SIZE, 0, &sc->sc_ioh) != 0) { 350 aprint_error_dev(self, 351 "can't map power management i/o space\n"); 352 return; 353 } 354 355 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 356 LPCIB_PCI_GEN_PMCON_1); 357 358 /* For ICH6 and later, always enable RCBA */ 359 if (sc->sc_has_rcba) { 360 pcireg_t rcba; 361 362 sc->sc_rcbat = sc->sc_pa.pa_memt; 363 364 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 365 LPCIB_RCBA); 366 if ((rcba & LPCIB_RCBA_EN) == 0) { 367 aprint_error_dev(self, "RCBA is not enabled\n"); 368 return; 369 } 370 rcba &= ~LPCIB_RCBA_EN; 371 372 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 373 &sc->sc_rcbah)) { 374 aprint_error_dev(self, "RCBA could not be mapped\n"); 375 return; 376 } 377 } 378 379 /* Set up the power management timer. */ 380 pmtimer_configure(self); 381 382 /* Set up the TCO (watchdog). */ 383 tcotimer_configure(self); 384 385 /* Set up SpeedStep. */ 386 speedstep_configure(self); 387 388 /* Set up HPET. */ 389 lpcib_hpet_configure(self); 390 391 #if NGPIO > 0 392 /* Set up GPIO */ 393 lpcib_gpio_configure(self); 394 #endif 395 396 #if NFWHRNG > 0 397 lpcib_fwh_configure(self); 398 #endif 399 400 /* Install power handler */ 401 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 402 lpcib_shutdown)) 403 aprint_error_dev(self, "couldn't establish power handler\n"); 404 } 405 406 static void 407 lpcibchilddet(device_t self, device_t child) 408 { 409 struct lpcib_softc *sc = device_private(self); 410 uint32_t val; 411 412 #if NFWHRNG > 0 413 if (sc->sc_fwhbus == child) { 414 sc->sc_fwhbus = NULL; 415 return; 416 } 417 #endif 418 #if NGPIO > 0 419 if (sc->sc_gpiobus == child) { 420 sc->sc_gpiobus = NULL; 421 return; 422 } 423 #endif 424 if (sc->sc_hpetbus != child) { 425 pcibchilddet(self, child); 426 return; 427 } 428 sc->sc_hpetbus = NULL; 429 if (sc->sc_has_ich5_hpet) { 430 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 431 LPCIB_PCI_GEN_CNTL); 432 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 433 case LPCIB_ICH5_HPTC_0000: 434 case LPCIB_ICH5_HPTC_1000: 435 case LPCIB_ICH5_HPTC_2000: 436 case LPCIB_ICH5_HPTC_3000: 437 break; 438 default: 439 return; 440 } 441 val &= ~LPCIB_ICH5_HPTC_EN; 442 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 443 LPCIB_PCI_GEN_CNTL, val); 444 } else if (sc->sc_has_rcba) { 445 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 446 LPCIB_RCBA_HPTC); 447 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 448 case LPCIB_RCBA_HPTC_0000: 449 case LPCIB_RCBA_HPTC_1000: 450 case LPCIB_RCBA_HPTC_2000: 451 case LPCIB_RCBA_HPTC_3000: 452 break; 453 default: 454 return; 455 } 456 val &= ~LPCIB_RCBA_HPTC_EN; 457 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 458 val); 459 } 460 } 461 462 static int 463 lpcibrescan(device_t self, const char *ifattr, const int *locators) 464 { 465 struct lpcib_softc *sc = device_private(self); 466 467 #if NFWHRNG > 0 468 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 469 lpcib_fwh_configure(self); 470 #endif 471 472 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 473 lpcib_hpet_configure(self); 474 475 #if NGPIO > 0 476 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 477 lpcib_gpio_configure(self); 478 #endif 479 480 return pcibrescan(self, ifattr, locators); 481 } 482 483 static int 484 lpcibdetach(device_t self, int flags) 485 { 486 struct lpcib_softc *sc = device_private(self); 487 int rc; 488 489 pmf_device_deregister(self); 490 491 #if NFWHRNG > 0 492 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 493 return rc; 494 #endif 495 496 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 497 return rc; 498 499 #if NGPIO > 0 500 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 501 return rc; 502 #endif 503 504 /* Set up SpeedStep. */ 505 speedstep_unconfigure(self); 506 507 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 508 return rc; 509 510 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 511 return rc; 512 513 if (sc->sc_has_rcba) 514 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 515 516 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 517 518 return pcibdetach(self, flags); 519 } 520 521 static bool 522 lpcib_shutdown(device_t dv, int howto) 523 { 524 struct lpcib_softc *sc = device_private(dv); 525 526 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 527 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 528 529 return true; 530 } 531 532 static bool 533 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 534 { 535 struct lpcib_softc *sc = device_private(dv); 536 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 537 pcitag_t tag = sc->sc_pcib.sc_tag; 538 539 /* capture PIRQ routing control registers */ 540 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 541 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 542 543 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 544 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 545 546 if (sc->sc_has_rcba) { 547 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 548 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 549 LPCIB_RCBA_HPTC); 550 } else if (sc->sc_has_ich5_hpet) { 551 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 552 } 553 554 return true; 555 } 556 557 static bool 558 lpcib_resume(device_t dv, const pmf_qual_t *qual) 559 { 560 struct lpcib_softc *sc = device_private(dv); 561 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 562 pcitag_t tag = sc->sc_pcib.sc_tag; 563 564 /* restore PIRQ routing control registers */ 565 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 566 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 567 568 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 569 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 570 571 if (sc->sc_has_rcba) { 572 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 573 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 574 sc->sc_hpet_reg); 575 } else if (sc->sc_has_ich5_hpet) { 576 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 577 } 578 579 return true; 580 } 581 582 /* 583 * Initialize the power management timer. 584 */ 585 static void 586 pmtimer_configure(device_t self) 587 { 588 struct lpcib_softc *sc = device_private(self); 589 pcireg_t control; 590 591 /* 592 * Check if power management I/O space is enabled and enable the ACPI_EN 593 * bit if it's disabled. 594 */ 595 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 596 LPCIB_PCI_ACPI_CNTL); 597 sc->sc_acpi_cntl = control; 598 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 599 control |= LPCIB_PCI_ACPI_CNTL_EN; 600 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 601 LPCIB_PCI_ACPI_CNTL, control); 602 } 603 604 /* Attach our PM timer with the generic acpipmtimer function */ 605 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 606 LPCIB_PM1_TMR, 0); 607 } 608 609 static int 610 pmtimer_unconfigure(device_t self, int flags) 611 { 612 struct lpcib_softc *sc = device_private(self); 613 int rc; 614 615 if (sc->sc_pmtimer != NULL && 616 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 617 return rc; 618 619 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 620 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 621 622 return 0; 623 } 624 625 /* 626 * Initialize the watchdog timer. 627 */ 628 static void 629 tcotimer_configure(device_t self) 630 { 631 struct lpcib_softc *sc = device_private(self); 632 uint32_t ioreg; 633 unsigned int period; 634 635 /* Explicitly stop the TCO timer. */ 636 tcotimer_stop(sc); 637 638 /* 639 * Enable TCO timeout SMI only if the hardware reset does not 640 * work. We don't know what the SMBIOS does. 641 */ 642 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 643 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 644 645 /* 646 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 647 * in the SMI_EN register is the last chance. 648 */ 649 if (tcotimer_disable_noreboot(self)) { 650 ioreg |= LPCIB_SMI_EN_TCO_EN; 651 } 652 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 653 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 654 } 655 656 /* Reset the watchdog status registers. */ 657 tcotimer_status_reset(sc); 658 659 /* 660 * Register the driver with the sysmon watchdog framework. 661 */ 662 sc->sc_smw.smw_name = device_xname(self); 663 sc->sc_smw.smw_cookie = sc; 664 sc->sc_smw.smw_setmode = tcotimer_setmode; 665 sc->sc_smw.smw_tickle = tcotimer_tickle; 666 if (sc->sc_has_rcba) 667 period = LPCIB_TCOTIMER2_MAX_TICK; 668 else 669 period = LPCIB_TCOTIMER_MAX_TICK; 670 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 671 672 if (sysmon_wdog_register(&sc->sc_smw)) { 673 aprint_error_dev(self, "unable to register TCO timer" 674 "as a sysmon watchdog device.\n"); 675 return; 676 } 677 678 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 679 } 680 681 static int 682 tcotimer_unconfigure(device_t self, int flags) 683 { 684 struct lpcib_softc *sc = device_private(self); 685 int rc; 686 687 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 688 if (rc == ERESTART) 689 rc = EINTR; 690 return rc; 691 } 692 693 /* Explicitly stop the TCO timer. */ 694 tcotimer_stop(sc); 695 696 /* XXX Set No Reboot? */ 697 698 return 0; 699 } 700 701 702 /* 703 * Sysmon watchdog callbacks. 704 */ 705 static int 706 tcotimer_setmode(struct sysmon_wdog *smw) 707 { 708 struct lpcib_softc *sc = smw->smw_cookie; 709 unsigned int period; 710 uint16_t ich6period = 0; 711 uint8_t ich5period = 0; 712 713 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 714 /* Stop the TCO timer. */ 715 tcotimer_stop(sc); 716 } else { 717 /* 718 * ICH6 or newer are limited to 2s min and 613s max. 719 * ICH5 or older are limited to 4s min and 39s max. 720 */ 721 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 722 if (sc->sc_has_rcba) { 723 if (period < LPCIB_TCOTIMER2_MIN_TICK || 724 period > LPCIB_TCOTIMER2_MAX_TICK) 725 return EINVAL; 726 } else { 727 if (period < LPCIB_TCOTIMER_MIN_TICK || 728 period > LPCIB_TCOTIMER_MAX_TICK) 729 return EINVAL; 730 } 731 732 /* Stop the TCO timer, */ 733 tcotimer_stop(sc); 734 735 /* set the timeout, */ 736 if (sc->sc_has_rcba) { 737 /* ICH6 or newer */ 738 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 739 LPCIB_TCO_TMR2); 740 ich6period &= 0xfc00; 741 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 742 LPCIB_TCO_TMR2, ich6period | period); 743 } else { 744 /* ICH5 or older */ 745 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 746 LPCIB_TCO_TMR); 747 ich5period &= 0xc0; 748 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 749 LPCIB_TCO_TMR, ich5period | period); 750 } 751 752 /* and start/reload the timer. */ 753 tcotimer_start(sc); 754 tcotimer_tickle(smw); 755 } 756 757 return 0; 758 } 759 760 static int 761 tcotimer_tickle(struct sysmon_wdog *smw) 762 { 763 struct lpcib_softc *sc = smw->smw_cookie; 764 765 /* any value is allowed */ 766 if (sc->sc_has_rcba) 767 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 768 else 769 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 770 771 return 0; 772 } 773 774 static void 775 tcotimer_stop(struct lpcib_softc *sc) 776 { 777 uint16_t ioreg; 778 779 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 780 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 781 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 782 } 783 784 static void 785 tcotimer_start(struct lpcib_softc *sc) 786 { 787 uint16_t ioreg; 788 789 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 790 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 791 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 792 } 793 794 static void 795 tcotimer_status_reset(struct lpcib_softc *sc) 796 { 797 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 798 LPCIB_TCO1_STS_TIMEOUT); 799 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 800 LPCIB_TCO2_STS_BOOT_STS); 801 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 802 LPCIB_TCO2_STS_SECONDS_TO_STS); 803 } 804 805 /* 806 * Clear the No Reboot (NR) bit, this enables reboots when the timer 807 * reaches the timeout for the second time. 808 */ 809 static int 810 tcotimer_disable_noreboot(device_t self) 811 { 812 struct lpcib_softc *sc = device_private(self); 813 814 if (sc->sc_has_rcba) { 815 uint32_t status; 816 817 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 818 LPCIB_GCS_OFFSET); 819 status &= ~LPCIB_GCS_NO_REBOOT; 820 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 821 LPCIB_GCS_OFFSET, status); 822 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 823 LPCIB_GCS_OFFSET); 824 if (status & LPCIB_GCS_NO_REBOOT) 825 goto error; 826 } else { 827 pcireg_t pcireg; 828 829 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 830 LPCIB_PCI_GEN_STA); 831 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 832 /* TCO timeout reset is disabled; try to enable it */ 833 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 834 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 835 LPCIB_PCI_GEN_STA, pcireg); 836 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 837 goto error; 838 } 839 } 840 841 return 0; 842 error: 843 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 844 "hope SMBIOS properly handles it.\n"); 845 return EINVAL; 846 } 847 848 849 /* 850 * Intel ICH SpeedStep support. 851 */ 852 #define SS_READ(sc, reg) \ 853 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 854 #define SS_WRITE(sc, reg, val) \ 855 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 856 857 /* 858 * Linux driver says that SpeedStep on older chipsets cause 859 * lockups on Dell Inspiron 8000 and 8100. 860 * It should also not be enabled on systems with the 82855GM 861 * Hub, which typically have an EST-enabled CPU. 862 */ 863 static int 864 speedstep_bad_hb_check(const struct pci_attach_args *pa) 865 { 866 867 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 868 PCI_REVISION(pa->pa_class) < 5) 869 return 1; 870 871 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 872 return 1; 873 874 return 0; 875 } 876 877 static void 878 speedstep_configure(device_t self) 879 { 880 struct lpcib_softc *sc = device_private(self); 881 const struct sysctlnode *node, *ssnode; 882 int rv; 883 884 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 885 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 886 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 887 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 888 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 889 pcireg_t pmcon; 890 891 /* Enable SpeedStep if it isn't already enabled. */ 892 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 893 LPCIB_PCI_GEN_PMCON_1); 894 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 895 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 896 LPCIB_PCI_GEN_PMCON_1, 897 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 898 899 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 900 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 901 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 902 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 903 goto err; 904 905 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 906 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 907 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 908 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 909 CTL_EOL)) != 0) 910 goto err; 911 912 /* XXX save the sc for IO tag/handle */ 913 speedstep_cookie = sc; 914 aprint_verbose_dev(self, "SpeedStep enabled\n"); 915 } 916 917 return; 918 919 err: 920 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 921 } 922 923 static void 924 speedstep_unconfigure(device_t self) 925 { 926 struct lpcib_softc *sc = device_private(self); 927 928 sysctl_teardown(&sc->sc_log); 929 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 930 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 931 932 speedstep_cookie = NULL; 933 } 934 935 /* 936 * get/set the SpeedStep state: 0 == low power, 1 == high power. 937 */ 938 static int 939 speedstep_sysctl_helper(SYSCTLFN_ARGS) 940 { 941 struct sysctlnode node; 942 struct lpcib_softc *sc = speedstep_cookie; 943 uint8_t state, state2; 944 int ostate, nstate, s, error = 0; 945 946 /* 947 * We do the dance with spl's to avoid being at high ipl during 948 * sysctl_lookup() which can both copyin and copyout. 949 */ 950 s = splserial(); 951 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 952 splx(s); 953 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 954 ostate = 1; 955 else 956 ostate = 0; 957 nstate = ostate; 958 959 node = *rnode; 960 node.sysctl_data = &nstate; 961 962 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 963 if (error || newp == NULL) 964 goto out; 965 966 /* Only two states are available */ 967 if (nstate != 0 && nstate != 1) { 968 error = EINVAL; 969 goto out; 970 } 971 972 s = splserial(); 973 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 974 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 975 ostate = 1; 976 else 977 ostate = 0; 978 979 if (ostate != nstate) { 980 uint8_t cntl; 981 982 if (nstate == 0) 983 state2 |= LPCIB_PM_SS_STATE_LOW; 984 else 985 state2 &= ~LPCIB_PM_SS_STATE_LOW; 986 987 /* 988 * Must disable bus master arbitration during the change. 989 */ 990 cntl = SS_READ(sc, LPCIB_PM_CTRL); 991 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 992 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 993 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 994 } 995 splx(s); 996 out: 997 return error; 998 } 999 1000 static void 1001 lpcib_hpet_configure(device_t self) 1002 { 1003 struct lpcib_softc *sc = device_private(self); 1004 struct lpcib_hpet_attach_args arg; 1005 uint32_t hpet_reg, val; 1006 1007 if (sc->sc_has_ich5_hpet) { 1008 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1009 LPCIB_PCI_GEN_CNTL); 1010 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 1011 case LPCIB_ICH5_HPTC_0000: 1012 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 1013 break; 1014 case LPCIB_ICH5_HPTC_1000: 1015 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 1016 break; 1017 case LPCIB_ICH5_HPTC_2000: 1018 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 1019 break; 1020 case LPCIB_ICH5_HPTC_3000: 1021 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 1022 break; 1023 default: 1024 return; 1025 } 1026 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 1027 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1028 LPCIB_PCI_GEN_CNTL, val); 1029 } else if (sc->sc_has_rcba) { 1030 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 1031 LPCIB_RCBA_HPTC); 1032 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 1033 case LPCIB_RCBA_HPTC_0000: 1034 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 1035 break; 1036 case LPCIB_RCBA_HPTC_1000: 1037 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 1038 break; 1039 case LPCIB_RCBA_HPTC_2000: 1040 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1041 break; 1042 case LPCIB_RCBA_HPTC_3000: 1043 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1044 break; 1045 default: 1046 return; 1047 } 1048 val |= LPCIB_RCBA_HPTC_EN; 1049 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1050 val); 1051 } else { 1052 /* No HPET here */ 1053 return; 1054 } 1055 1056 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1057 arg.hpet_reg = hpet_reg; 1058 1059 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1060 } 1061 1062 static int 1063 lpcib_hpet_unconfigure(device_t self, int flags) 1064 { 1065 struct lpcib_softc *sc = device_private(self); 1066 int rc; 1067 1068 if (sc->sc_hpetbus != NULL && 1069 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1070 return rc; 1071 1072 return 0; 1073 } 1074 1075 #if NGPIO > 0 1076 static void 1077 lpcib_gpio_configure(device_t self) 1078 { 1079 struct lpcib_softc *sc = device_private(self); 1080 struct gpiobus_attach_args gba; 1081 pcireg_t gpio_cntl; 1082 uint32_t use, io, bit; 1083 int pin, shift, base_reg, cntl_reg, reg; 1084 int rv; 1085 1086 if (ichlpcib_gpio_disable != 0) 1087 return; 1088 1089 /* this implies ICH >= 6, and thus different mapreg */ 1090 if (sc->sc_has_rcba) { 1091 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1092 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1093 } else { 1094 base_reg = LPCIB_PCI_GPIO_BASE; 1095 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1096 } 1097 1098 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1099 cntl_reg); 1100 1101 /* Is GPIO enabled? */ 1102 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1103 return; 1104 /* 1105 * The GPIO_BASE register is alike PCI BAR but not completely 1106 * compatible with it. The PMBASE define the base address and the type 1107 * but not describe the size. The value of the register may be lower 1108 * than LPCIB_PCI_GPIO_SIZE. It makes impossible to use 1109 * pci_mapreg_submap() because the function does range check. 1110 */ 1111 sc->sc_gpio_iot = sc->sc_pa.pa_iot; 1112 reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg); 1113 rv = bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(reg), 1114 LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_ioh); 1115 if (rv != 0) { 1116 aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv); 1117 return; 1118 } 1119 1120 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1121 1122 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1123 sc->sc_gpio_pins[pin].pin_num = pin; 1124 1125 /* Read initial state */ 1126 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1127 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1128 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1129 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1130 shift = pin % 32; 1131 bit = __BIT(shift); 1132 1133 if ((use & bit) != 0) { 1134 sc->sc_gpio_pins[pin].pin_caps = 1135 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1136 if (pin < 32) 1137 sc->sc_gpio_pins[pin].pin_caps |= 1138 GPIO_PIN_PULSATE; 1139 if ((io & bit) != 0) 1140 sc->sc_gpio_pins[pin].pin_flags = 1141 GPIO_PIN_INPUT; 1142 else 1143 sc->sc_gpio_pins[pin].pin_flags = 1144 GPIO_PIN_OUTPUT; 1145 } else 1146 sc->sc_gpio_pins[pin].pin_caps = 0; 1147 1148 if (lpcib_gpio_pin_read(sc, pin) == 0) 1149 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1150 else 1151 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1152 1153 } 1154 1155 /* Create controller tag */ 1156 sc->sc_gpio_gc.gp_cookie = sc; 1157 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1158 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1159 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1160 1161 memset(&gba, 0, sizeof(gba)); 1162 1163 gba.gba_gc = &sc->sc_gpio_gc; 1164 gba.gba_pins = sc->sc_gpio_pins; 1165 gba.gba_npins = LPCIB_GPIO_NPINS; 1166 1167 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1168 } 1169 1170 static int 1171 lpcib_gpio_unconfigure(device_t self, int flags) 1172 { 1173 struct lpcib_softc *sc = device_private(self); 1174 int rc; 1175 1176 if (sc->sc_gpiobus != NULL && 1177 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1178 return rc; 1179 1180 mutex_destroy(&sc->sc_gpio_mtx); 1181 1182 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1183 1184 return 0; 1185 } 1186 1187 static int 1188 lpcib_gpio_pin_read(void *arg, int pin) 1189 { 1190 struct lpcib_softc *sc = arg; 1191 uint32_t data; 1192 int reg, shift; 1193 1194 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1195 shift = pin % 32; 1196 1197 mutex_enter(&sc->sc_gpio_mtx); 1198 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1199 mutex_exit(&sc->sc_gpio_mtx); 1200 1201 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1202 } 1203 1204 static void 1205 lpcib_gpio_pin_write(void *arg, int pin, int value) 1206 { 1207 struct lpcib_softc *sc = arg; 1208 uint32_t data; 1209 int reg, shift; 1210 1211 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1212 shift = pin % 32; 1213 1214 mutex_enter(&sc->sc_gpio_mtx); 1215 1216 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1217 1218 if(value) 1219 data |= __BIT(shift); 1220 else 1221 data &= ~__BIT(shift); 1222 1223 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1224 1225 mutex_exit(&sc->sc_gpio_mtx); 1226 } 1227 1228 static void 1229 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1230 { 1231 struct lpcib_softc *sc = arg; 1232 uint32_t data; 1233 int reg, shift; 1234 1235 shift = pin % 32; 1236 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1237 1238 mutex_enter(&sc->sc_gpio_mtx); 1239 1240 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1241 1242 if (flags & GPIO_PIN_OUTPUT) 1243 data &= ~__BIT(shift); 1244 1245 if (flags & GPIO_PIN_INPUT) 1246 data |= __BIT(shift); 1247 1248 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1249 1250 1251 if (pin < 32) { 1252 reg = LPCIB_GPIO_GPO_BLINK; 1253 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1254 1255 if (flags & GPIO_PIN_PULSATE) 1256 data |= __BIT(shift); 1257 else 1258 data &= ~__BIT(shift); 1259 1260 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1261 } 1262 1263 mutex_exit(&sc->sc_gpio_mtx); 1264 } 1265 #endif 1266 1267 #if NFWHRNG > 0 1268 static void 1269 lpcib_fwh_configure(device_t self) 1270 { 1271 struct lpcib_softc *sc; 1272 pcireg_t pr; 1273 1274 sc = device_private(self); 1275 1276 if (sc->sc_has_rcba) { 1277 /* 1278 * Very unlikely to find a 82802 on a ICH6 or newer. 1279 * Also the write enable register moved at that point. 1280 */ 1281 return; 1282 } else { 1283 /* Enable FWH write to identify FWH. */ 1284 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1285 LPCIB_PCI_BIOS_CNTL); 1286 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1287 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1288 } 1289 1290 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1291 1292 /* restore previous write enable setting */ 1293 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1294 LPCIB_PCI_BIOS_CNTL, pr); 1295 } 1296 1297 static int 1298 lpcib_fwh_unconfigure(device_t self, int flags) 1299 { 1300 struct lpcib_softc *sc = device_private(self); 1301 int rc; 1302 1303 if (sc->sc_fwhbus != NULL && 1304 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1305 return rc; 1306 1307 return 0; 1308 } 1309 #endif 1310
Indexes created Wed Oct 01 15:09:59 GMT 2025