ichlpcib.c revision 1.43.6.2
1 /* $NetBSD: ichlpcib.c,v 1.43.6.2 2015/06/06 14:40:04 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems), 38 * the gpio interface, hpet timer, hardware random number generator, 39 * and the power management timer. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.43.6.2 2015/06/06 14:40:04 skrll Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/sysctl.h> 50 #include <sys/timetc.h> 51 #include <sys/gpio.h> 52 #include <sys/bus.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcidevs.h> 57 58 #include <dev/gpio/gpiovar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include <arch/x86/pci/tco.h> 67 68 #include "pcibvar.h" 69 #include "gpio.h" 70 #include "fwhrng.h" 71 72 #define LPCIB_GPIO_NPINS 64 73 74 struct lpcib_softc { 75 /* we call pcibattach() which assumes this starts like this: */ 76 struct pcib_softc sc_pcib; 77 78 struct pci_attach_args sc_pa; 79 int sc_has_rcba; 80 int sc_has_ich5_hpet; 81 82 /* RCBA */ 83 bus_space_tag_t sc_rcbat; 84 bus_space_handle_t sc_rcbah; 85 pcireg_t sc_rcba_reg; 86 87 /* Power management variables. */ 88 bus_space_tag_t sc_iot; 89 bus_space_handle_t sc_ioh; 90 bus_size_t sc_iosize; 91 92 /* HPET variables. */ 93 uint32_t sc_hpet_reg; 94 95 #if NGPIO > 0 96 device_t sc_gpiobus; 97 kmutex_t sc_gpio_mtx; 98 bus_space_tag_t sc_gpio_iot; 99 bus_space_handle_t sc_gpio_ioh; 100 bus_size_t sc_gpio_ios; 101 struct gpio_chipset_tag sc_gpio_gc; 102 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 103 #endif 104 105 #if NFWHRNG > 0 106 device_t sc_fwhbus; 107 #endif 108 109 /* Speedstep */ 110 pcireg_t sc_pmcon_orig; 111 112 /* Power management */ 113 pcireg_t sc_pirq[2]; 114 pcireg_t sc_pmcon; 115 pcireg_t sc_fwhsel2; 116 117 /* Child devices */ 118 device_t sc_tco; 119 device_t sc_hpetbus; 120 acpipmtimer_t sc_pmtimer; 121 pcireg_t sc_acpi_cntl; 122 123 struct sysctllog *sc_log; 124 }; 125 126 static int lpcibmatch(device_t, cfdata_t, void *); 127 static void lpcibattach(device_t, device_t, void *); 128 static int lpcibdetach(device_t, int); 129 static void lpcibchilddet(device_t, device_t); 130 static int lpcibrescan(device_t, const char *, const int *); 131 static bool lpcib_suspend(device_t, const pmf_qual_t *); 132 static bool lpcib_resume(device_t, const pmf_qual_t *); 133 static bool lpcib_shutdown(device_t, int); 134 135 static void pmtimer_configure(device_t); 136 static int pmtimer_unconfigure(device_t, int); 137 138 static void tcotimer_configure(device_t); 139 static int tcotimer_unconfigure(device_t, int); 140 141 static void speedstep_configure(device_t); 142 static void speedstep_unconfigure(device_t); 143 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 144 145 static void lpcib_hpet_configure(device_t); 146 static int lpcib_hpet_unconfigure(device_t, int); 147 148 #if NGPIO > 0 149 static void lpcib_gpio_configure(device_t); 150 static int lpcib_gpio_unconfigure(device_t, int); 151 static int lpcib_gpio_pin_read(void *, int); 152 static void lpcib_gpio_pin_write(void *, int, int); 153 static void lpcib_gpio_pin_ctl(void *, int, int); 154 #endif 155 156 #if NFWHRNG > 0 157 static void lpcib_fwh_configure(device_t); 158 static int lpcib_fwh_unconfigure(device_t, int); 159 #endif 160 161 struct lpcib_softc *speedstep_cookie; /* XXX */ 162 163 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 164 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 165 166 static struct lpcib_device { 167 pcireg_t vendor, product; 168 int has_rcba; 169 int has_ich5_hpet; 170 } lpcib_devices[] = { 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 172 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z68_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H97_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z97_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X99_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X99_LPC_2, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE5G_M_LPC_4, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE5G_M_LPC_7, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 264 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_LPC, 1, 0 }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCL_LPC, 1, 0 }, 269 #if 0 270 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 273 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 274 #endif 275 276 { 0, 0, 0, 0 }, 277 }; 278 279 /* 280 * Autoconf callbacks. 281 */ 282 static int 283 lpcibmatch(device_t parent, cfdata_t match, void *aux) 284 { 285 struct pci_attach_args *pa = aux; 286 struct lpcib_device *lpcib_dev; 287 288 /* We are ISA bridge, of course */ 289 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 290 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 291 return 0; 292 293 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 294 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 295 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 296 return 10; 297 } 298 299 return 0; 300 } 301 302 static void 303 lpcibattach(device_t parent, device_t self, void *aux) 304 { 305 struct pci_attach_args *pa = aux; 306 struct lpcib_softc *sc = device_private(self); 307 struct lpcib_device *lpcib_dev; 308 pcireg_t pmbase; 309 310 sc->sc_pa = *pa; 311 312 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 313 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 314 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 315 continue; 316 sc->sc_has_rcba = lpcib_dev->has_rcba; 317 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 318 break; 319 } 320 321 pcibattach(parent, self, aux); 322 323 /* 324 * Part of our I/O registers are used as ACPI PM regs. 325 * Since our ACPI subsystem accesses the I/O space directly so far, 326 * we do not have to bother bus_space I/O map confliction. 327 * 328 * The PMBASE register is alike PCI BAR but not completely compatible 329 * with it. The PMBASE define the base address and the type but 330 * not describe the size. The value of the register may be lower 331 * than LPCIB_PCI_PM_SIZE. It makes impossible to use 332 * pci_mapreg_submap() because the function does range check. 333 */ 334 sc->sc_iot = pa->pa_iot; 335 pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE); 336 if (bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(pmbase), 337 LPCIB_PCI_PM_SIZE, 0, &sc->sc_ioh) != 0) { 338 aprint_error_dev(self, 339 "can't map power management i/o space\n"); 340 return; 341 } 342 343 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 344 LPCIB_PCI_GEN_PMCON_1); 345 346 /* For ICH6 and later, always enable RCBA */ 347 if (sc->sc_has_rcba) { 348 pcireg_t rcba; 349 350 sc->sc_rcbat = sc->sc_pa.pa_memt; 351 352 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 353 LPCIB_RCBA); 354 if ((rcba & LPCIB_RCBA_EN) == 0) { 355 aprint_error_dev(self, "RCBA is not enabled\n"); 356 return; 357 } 358 rcba &= ~LPCIB_RCBA_EN; 359 360 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 361 &sc->sc_rcbah)) { 362 aprint_error_dev(self, "RCBA could not be mapped\n"); 363 return; 364 } 365 } 366 367 /* Set up the power management timer. */ 368 pmtimer_configure(self); 369 370 /* Set up the TCO (watchdog). */ 371 tcotimer_configure(self); 372 373 /* Set up SpeedStep. */ 374 speedstep_configure(self); 375 376 /* Set up HPET. */ 377 lpcib_hpet_configure(self); 378 379 #if NGPIO > 0 380 /* Set up GPIO */ 381 lpcib_gpio_configure(self); 382 #endif 383 384 #if NFWHRNG > 0 385 lpcib_fwh_configure(self); 386 #endif 387 388 /* Install power handler */ 389 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 390 lpcib_shutdown)) 391 aprint_error_dev(self, "couldn't establish power handler\n"); 392 } 393 394 static void 395 lpcibchilddet(device_t self, device_t child) 396 { 397 struct lpcib_softc *sc = device_private(self); 398 uint32_t val; 399 400 #if NFWHRNG > 0 401 if (sc->sc_fwhbus == child) { 402 sc->sc_fwhbus = NULL; 403 return; 404 } 405 #endif 406 #if NGPIO > 0 407 if (sc->sc_gpiobus == child) { 408 sc->sc_gpiobus = NULL; 409 return; 410 } 411 #endif 412 if (sc->sc_tco == child) { 413 sc->sc_tco = NULL; 414 return; 415 } 416 417 if (sc->sc_hpetbus != child) { 418 pcibchilddet(self, child); 419 return; 420 } 421 sc->sc_hpetbus = NULL; 422 if (sc->sc_has_ich5_hpet) { 423 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 424 LPCIB_PCI_GEN_CNTL); 425 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 426 case LPCIB_ICH5_HPTC_0000: 427 case LPCIB_ICH5_HPTC_1000: 428 case LPCIB_ICH5_HPTC_2000: 429 case LPCIB_ICH5_HPTC_3000: 430 break; 431 default: 432 return; 433 } 434 val &= ~LPCIB_ICH5_HPTC_EN; 435 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 436 LPCIB_PCI_GEN_CNTL, val); 437 } else if (sc->sc_has_rcba) { 438 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 439 LPCIB_RCBA_HPTC); 440 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 441 case LPCIB_RCBA_HPTC_0000: 442 case LPCIB_RCBA_HPTC_1000: 443 case LPCIB_RCBA_HPTC_2000: 444 case LPCIB_RCBA_HPTC_3000: 445 break; 446 default: 447 return; 448 } 449 val &= ~LPCIB_RCBA_HPTC_EN; 450 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 451 val); 452 } 453 } 454 455 static int 456 lpcibrescan(device_t self, const char *ifattr, const int *locators) 457 { 458 struct lpcib_softc *sc = device_private(self); 459 460 if(ifattr_match(ifattr, "tcoichbus") && sc->sc_tco == NULL) 461 tcotimer_configure(self); 462 463 #if NFWHRNG > 0 464 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 465 lpcib_fwh_configure(self); 466 #endif 467 468 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 469 lpcib_hpet_configure(self); 470 471 #if NGPIO > 0 472 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 473 lpcib_gpio_configure(self); 474 #endif 475 476 return pcibrescan(self, ifattr, locators); 477 } 478 479 static int 480 lpcibdetach(device_t self, int flags) 481 { 482 struct lpcib_softc *sc = device_private(self); 483 int rc; 484 485 pmf_device_deregister(self); 486 487 #if NFWHRNG > 0 488 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 489 return rc; 490 #endif 491 492 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 493 return rc; 494 495 #if NGPIO > 0 496 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 497 return rc; 498 #endif 499 500 /* Set up SpeedStep. */ 501 speedstep_unconfigure(self); 502 503 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 504 return rc; 505 506 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 507 return rc; 508 509 if (sc->sc_has_rcba) 510 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 511 512 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 513 514 return pcibdetach(self, flags); 515 } 516 517 static bool 518 lpcib_shutdown(device_t dv, int howto) 519 { 520 struct lpcib_softc *sc = device_private(dv); 521 522 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 523 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 524 525 return true; 526 } 527 528 static bool 529 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 530 { 531 struct lpcib_softc *sc = device_private(dv); 532 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 533 pcitag_t tag = sc->sc_pcib.sc_tag; 534 535 /* capture PIRQ routing control registers */ 536 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 537 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 538 539 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 540 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 541 542 if (sc->sc_has_rcba) { 543 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 544 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 545 LPCIB_RCBA_HPTC); 546 } else if (sc->sc_has_ich5_hpet) { 547 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 548 } 549 550 return true; 551 } 552 553 static bool 554 lpcib_resume(device_t dv, const pmf_qual_t *qual) 555 { 556 struct lpcib_softc *sc = device_private(dv); 557 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 558 pcitag_t tag = sc->sc_pcib.sc_tag; 559 560 /* restore PIRQ routing control registers */ 561 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 562 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 563 564 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 565 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 566 567 if (sc->sc_has_rcba) { 568 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 569 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 570 sc->sc_hpet_reg); 571 } else if (sc->sc_has_ich5_hpet) { 572 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 573 } 574 575 return true; 576 } 577 578 /* 579 * Initialize the power management timer. 580 */ 581 static void 582 pmtimer_configure(device_t self) 583 { 584 struct lpcib_softc *sc = device_private(self); 585 pcireg_t control; 586 587 /* 588 * Check if power management I/O space is enabled and enable the ACPI_EN 589 * bit if it's disabled. 590 */ 591 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 592 LPCIB_PCI_ACPI_CNTL); 593 sc->sc_acpi_cntl = control; 594 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 595 control |= LPCIB_PCI_ACPI_CNTL_EN; 596 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 597 LPCIB_PCI_ACPI_CNTL, control); 598 } 599 600 /* Attach our PM timer with the generic acpipmtimer function */ 601 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 602 LPCIB_PM1_TMR, 0); 603 } 604 605 static int 606 pmtimer_unconfigure(device_t self, int flags) 607 { 608 struct lpcib_softc *sc = device_private(self); 609 int rc; 610 611 if (sc->sc_pmtimer != NULL && 612 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 613 return rc; 614 615 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 616 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 617 618 return 0; 619 } 620 621 /* 622 * Configure the watchdog timer. 623 */ 624 static void 625 tcotimer_configure(device_t self) 626 { 627 struct lpcib_softc *sc = device_private(self); 628 struct lpcib_tco_attach_args arg; 629 630 arg.ta_iot = sc->sc_iot; 631 arg.ta_ioh = sc->sc_ioh; 632 arg.ta_rcbat = sc->sc_rcbat; 633 arg.ta_rcbah = sc->sc_rcbah; 634 arg.ta_has_rcba = sc->sc_has_rcba; 635 arg.ta_pcib = &(sc->sc_pcib); 636 637 sc->sc_tco = config_found_ia(self, "tcoichbus", &arg, NULL); 638 } 639 640 static int 641 tcotimer_unconfigure(device_t self, int flags) 642 { 643 struct lpcib_softc *sc = device_private(self); 644 int rc; 645 646 if (sc->sc_tco != NULL && 647 (rc = config_detach(sc->sc_tco, flags)) != 0) 648 return rc; 649 650 return 0; 651 } 652 653 654 /* 655 * Intel ICH SpeedStep support. 656 */ 657 #define SS_READ(sc, reg) \ 658 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 659 #define SS_WRITE(sc, reg, val) \ 660 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 661 662 /* 663 * Linux driver says that SpeedStep on older chipsets cause 664 * lockups on Dell Inspiron 8000 and 8100. 665 * It should also not be enabled on systems with the 82855GM 666 * Hub, which typically have an EST-enabled CPU. 667 */ 668 static int 669 speedstep_bad_hb_check(const struct pci_attach_args *pa) 670 { 671 672 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 673 PCI_REVISION(pa->pa_class) < 5) 674 return 1; 675 676 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 677 return 1; 678 679 return 0; 680 } 681 682 static void 683 speedstep_configure(device_t self) 684 { 685 struct lpcib_softc *sc = device_private(self); 686 const struct sysctlnode *node, *ssnode; 687 int rv; 688 689 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 690 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 691 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 692 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 693 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 694 pcireg_t pmcon; 695 696 /* Enable SpeedStep if it isn't already enabled. */ 697 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 698 LPCIB_PCI_GEN_PMCON_1); 699 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 700 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 701 LPCIB_PCI_GEN_PMCON_1, 702 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 703 704 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 705 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 706 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 707 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 708 goto err; 709 710 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 711 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 712 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 713 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 714 CTL_EOL)) != 0) 715 goto err; 716 717 /* XXX save the sc for IO tag/handle */ 718 speedstep_cookie = sc; 719 aprint_verbose_dev(self, "SpeedStep enabled\n"); 720 } 721 722 return; 723 724 err: 725 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 726 } 727 728 static void 729 speedstep_unconfigure(device_t self) 730 { 731 struct lpcib_softc *sc = device_private(self); 732 733 sysctl_teardown(&sc->sc_log); 734 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 735 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 736 737 speedstep_cookie = NULL; 738 } 739 740 /* 741 * get/set the SpeedStep state: 0 == low power, 1 == high power. 742 */ 743 static int 744 speedstep_sysctl_helper(SYSCTLFN_ARGS) 745 { 746 struct sysctlnode node; 747 struct lpcib_softc *sc = speedstep_cookie; 748 uint8_t state, state2; 749 int ostate, nstate, s, error = 0; 750 751 /* 752 * We do the dance with spl's to avoid being at high ipl during 753 * sysctl_lookup() which can both copyin and copyout. 754 */ 755 s = splserial(); 756 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 757 splx(s); 758 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 759 ostate = 1; 760 else 761 ostate = 0; 762 nstate = ostate; 763 764 node = *rnode; 765 node.sysctl_data = &nstate; 766 767 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 768 if (error || newp == NULL) 769 goto out; 770 771 /* Only two states are available */ 772 if (nstate != 0 && nstate != 1) { 773 error = EINVAL; 774 goto out; 775 } 776 777 s = splserial(); 778 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 779 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 780 ostate = 1; 781 else 782 ostate = 0; 783 784 if (ostate != nstate) { 785 uint8_t cntl; 786 787 if (nstate == 0) 788 state2 |= LPCIB_PM_SS_STATE_LOW; 789 else 790 state2 &= ~LPCIB_PM_SS_STATE_LOW; 791 792 /* 793 * Must disable bus master arbitration during the change. 794 */ 795 cntl = SS_READ(sc, LPCIB_PM_CTRL); 796 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 797 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 798 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 799 } 800 splx(s); 801 out: 802 return error; 803 } 804 805 static void 806 lpcib_hpet_configure(device_t self) 807 { 808 struct lpcib_softc *sc = device_private(self); 809 struct lpcib_hpet_attach_args arg; 810 uint32_t hpet_reg, val; 811 812 if (sc->sc_has_ich5_hpet) { 813 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 814 LPCIB_PCI_GEN_CNTL); 815 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 816 case LPCIB_ICH5_HPTC_0000: 817 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 818 break; 819 case LPCIB_ICH5_HPTC_1000: 820 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 821 break; 822 case LPCIB_ICH5_HPTC_2000: 823 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 824 break; 825 case LPCIB_ICH5_HPTC_3000: 826 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 827 break; 828 default: 829 return; 830 } 831 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 832 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 833 LPCIB_PCI_GEN_CNTL, val); 834 } else if (sc->sc_has_rcba) { 835 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 836 LPCIB_RCBA_HPTC); 837 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 838 case LPCIB_RCBA_HPTC_0000: 839 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 840 break; 841 case LPCIB_RCBA_HPTC_1000: 842 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 843 break; 844 case LPCIB_RCBA_HPTC_2000: 845 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 846 break; 847 case LPCIB_RCBA_HPTC_3000: 848 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 849 break; 850 default: 851 return; 852 } 853 val |= LPCIB_RCBA_HPTC_EN; 854 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 855 val); 856 } else { 857 /* No HPET here */ 858 return; 859 } 860 861 arg.hpet_mem_t = sc->sc_pa.pa_memt; 862 arg.hpet_reg = hpet_reg; 863 864 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 865 } 866 867 static int 868 lpcib_hpet_unconfigure(device_t self, int flags) 869 { 870 struct lpcib_softc *sc = device_private(self); 871 int rc; 872 873 if (sc->sc_hpetbus != NULL && 874 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 875 return rc; 876 877 return 0; 878 } 879 880 #if NGPIO > 0 881 static void 882 lpcib_gpio_configure(device_t self) 883 { 884 struct lpcib_softc *sc = device_private(self); 885 struct gpiobus_attach_args gba; 886 pcireg_t gpio_cntl; 887 uint32_t use, io, bit; 888 int pin, shift, base_reg, cntl_reg, reg; 889 int rv; 890 891 /* this implies ICH >= 6, and thus different mapreg */ 892 if (sc->sc_has_rcba) { 893 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 894 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 895 } else { 896 base_reg = LPCIB_PCI_GPIO_BASE; 897 cntl_reg = LPCIB_PCI_GPIO_CNTL; 898 } 899 900 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 901 cntl_reg); 902 903 /* Is GPIO enabled? */ 904 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 905 return; 906 /* 907 * The GPIO_BASE register is alike PCI BAR but not completely 908 * compatible with it. The PMBASE define the base address and the type 909 * but not describe the size. The value of the register may be lower 910 * than LPCIB_PCI_GPIO_SIZE. It makes impossible to use 911 * pci_mapreg_submap() because the function does range check. 912 */ 913 sc->sc_gpio_iot = sc->sc_pa.pa_iot; 914 reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg); 915 rv = bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(reg), 916 LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_ioh); 917 if (rv != 0) { 918 aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv); 919 return; 920 } 921 922 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 923 924 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 925 sc->sc_gpio_pins[pin].pin_num = pin; 926 927 /* Read initial state */ 928 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 929 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 930 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 931 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 932 shift = pin % 32; 933 bit = __BIT(shift); 934 935 if ((use & bit) != 0) { 936 sc->sc_gpio_pins[pin].pin_caps = 937 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 938 if (pin < 32) 939 sc->sc_gpio_pins[pin].pin_caps |= 940 GPIO_PIN_PULSATE; 941 if ((io & bit) != 0) 942 sc->sc_gpio_pins[pin].pin_flags = 943 GPIO_PIN_INPUT; 944 else 945 sc->sc_gpio_pins[pin].pin_flags = 946 GPIO_PIN_OUTPUT; 947 } else 948 sc->sc_gpio_pins[pin].pin_caps = 0; 949 950 if (lpcib_gpio_pin_read(sc, pin) == 0) 951 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 952 else 953 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 954 955 } 956 957 /* Create controller tag */ 958 sc->sc_gpio_gc.gp_cookie = sc; 959 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 960 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 961 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 962 963 memset(&gba, 0, sizeof(gba)); 964 965 gba.gba_gc = &sc->sc_gpio_gc; 966 gba.gba_pins = sc->sc_gpio_pins; 967 gba.gba_npins = LPCIB_GPIO_NPINS; 968 969 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 970 } 971 972 static int 973 lpcib_gpio_unconfigure(device_t self, int flags) 974 { 975 struct lpcib_softc *sc = device_private(self); 976 int rc; 977 978 if (sc->sc_gpiobus != NULL && 979 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 980 return rc; 981 982 mutex_destroy(&sc->sc_gpio_mtx); 983 984 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 985 986 return 0; 987 } 988 989 static int 990 lpcib_gpio_pin_read(void *arg, int pin) 991 { 992 struct lpcib_softc *sc = arg; 993 uint32_t data; 994 int reg, shift; 995 996 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 997 shift = pin % 32; 998 999 mutex_enter(&sc->sc_gpio_mtx); 1000 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1001 mutex_exit(&sc->sc_gpio_mtx); 1002 1003 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1004 } 1005 1006 static void 1007 lpcib_gpio_pin_write(void *arg, int pin, int value) 1008 { 1009 struct lpcib_softc *sc = arg; 1010 uint32_t data; 1011 int reg, shift; 1012 1013 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1014 shift = pin % 32; 1015 1016 mutex_enter(&sc->sc_gpio_mtx); 1017 1018 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1019 1020 if(value) 1021 data |= __BIT(shift); 1022 else 1023 data &= ~__BIT(shift); 1024 1025 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1026 1027 mutex_exit(&sc->sc_gpio_mtx); 1028 } 1029 1030 static void 1031 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1032 { 1033 struct lpcib_softc *sc = arg; 1034 uint32_t data; 1035 int reg, shift; 1036 1037 shift = pin % 32; 1038 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1039 1040 mutex_enter(&sc->sc_gpio_mtx); 1041 1042 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1043 1044 if (flags & GPIO_PIN_OUTPUT) 1045 data &= ~__BIT(shift); 1046 1047 if (flags & GPIO_PIN_INPUT) 1048 data |= __BIT(shift); 1049 1050 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1051 1052 1053 if (pin < 32) { 1054 reg = LPCIB_GPIO_GPO_BLINK; 1055 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1056 1057 if (flags & GPIO_PIN_PULSATE) 1058 data |= __BIT(shift); 1059 else 1060 data &= ~__BIT(shift); 1061 1062 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1063 } 1064 1065 mutex_exit(&sc->sc_gpio_mtx); 1066 } 1067 #endif 1068 1069 #if NFWHRNG > 0 1070 static void 1071 lpcib_fwh_configure(device_t self) 1072 { 1073 struct lpcib_softc *sc; 1074 pcireg_t pr; 1075 1076 sc = device_private(self); 1077 1078 if (sc->sc_has_rcba) { 1079 /* 1080 * Very unlikely to find a 82802 on a ICH6 or newer. 1081 * Also the write enable register moved at that point. 1082 */ 1083 return; 1084 } else { 1085 /* Enable FWH write to identify FWH. */ 1086 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1087 LPCIB_PCI_BIOS_CNTL); 1088 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1089 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1090 } 1091 1092 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1093 1094 /* restore previous write enable setting */ 1095 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1096 LPCIB_PCI_BIOS_CNTL, pr); 1097 } 1098 1099 static int 1100 lpcib_fwh_unconfigure(device_t self, int flags) 1101 { 1102 struct lpcib_softc *sc = device_private(self); 1103 int rc; 1104 1105 if (sc->sc_fwhbus != NULL && 1106 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1107 return rc; 1108 1109 return 0; 1110 } 1111 #endif 1112
Indexes created Wed Oct 01 18:09:54 GMT 2025