ichlpcib.c revision 1.45
1 /* $NetBSD: ichlpcib.c,v 1.45 2014/12/26 05:09:03 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.45 2014/12/26 05:09:03 msaitoh Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z68_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 264 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_LPC, 1, 0 }, 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCL_LPC, 1, 0 }, 267 #if 0 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 270 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 272 #endif 273 274 { 0, 0, 0, 0 }, 275 }; 276 277 /* 278 * Autoconf callbacks. 279 */ 280 static int 281 lpcibmatch(device_t parent, cfdata_t match, void *aux) 282 { 283 struct pci_attach_args *pa = aux; 284 struct lpcib_device *lpcib_dev; 285 286 /* We are ISA bridge, of course */ 287 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 288 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 289 return 0; 290 291 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 292 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 293 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 294 return 10; 295 } 296 297 return 0; 298 } 299 300 static void 301 lpcibattach(device_t parent, device_t self, void *aux) 302 { 303 struct pci_attach_args *pa = aux; 304 struct lpcib_softc *sc = device_private(self); 305 struct lpcib_device *lpcib_dev; 306 307 sc->sc_pa = *pa; 308 309 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 310 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 311 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 312 continue; 313 sc->sc_has_rcba = lpcib_dev->has_rcba; 314 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 315 break; 316 } 317 318 pcibattach(parent, self, aux); 319 320 /* 321 * Part of our I/O registers are used as ACPI PM regs. 322 * Since our ACPI subsystem accesses the I/O space directly so far, 323 * we do not have to bother bus_space I/O map confliction. 324 * 325 * The PMBASE register is alike PCI BAR but not completely compatible 326 * with it. The PMBASE define the base address and the type but 327 * not describe the size. 328 */ 329 if (pci_mapreg_submap(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 330 LPCIB_PCI_PM_SIZE, 0, &sc->sc_iot, &sc->sc_ioh, NULL, 331 &sc->sc_iosize)) { 332 aprint_error_dev(self, "can't map power management i/o space\n"); 333 return; 334 } 335 336 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 337 LPCIB_PCI_GEN_PMCON_1); 338 339 /* For ICH6 and later, always enable RCBA */ 340 if (sc->sc_has_rcba) { 341 pcireg_t rcba; 342 343 sc->sc_rcbat = sc->sc_pa.pa_memt; 344 345 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 346 LPCIB_RCBA); 347 if ((rcba & LPCIB_RCBA_EN) == 0) { 348 aprint_error_dev(self, "RCBA is not enabled\n"); 349 return; 350 } 351 rcba &= ~LPCIB_RCBA_EN; 352 353 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 354 &sc->sc_rcbah)) { 355 aprint_error_dev(self, "RCBA could not be mapped\n"); 356 return; 357 } 358 } 359 360 /* Set up the power management timer. */ 361 pmtimer_configure(self); 362 363 /* Set up the TCO (watchdog). */ 364 tcotimer_configure(self); 365 366 /* Set up SpeedStep. */ 367 speedstep_configure(self); 368 369 /* Set up HPET. */ 370 lpcib_hpet_configure(self); 371 372 #if NGPIO > 0 373 /* Set up GPIO */ 374 lpcib_gpio_configure(self); 375 #endif 376 377 #if NFWHRNG > 0 378 lpcib_fwh_configure(self); 379 #endif 380 381 /* Install power handler */ 382 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 383 lpcib_shutdown)) 384 aprint_error_dev(self, "couldn't establish power handler\n"); 385 } 386 387 static void 388 lpcibchilddet(device_t self, device_t child) 389 { 390 struct lpcib_softc *sc = device_private(self); 391 uint32_t val; 392 393 #if NFWHRNG > 0 394 if (sc->sc_fwhbus == child) { 395 sc->sc_fwhbus = NULL; 396 return; 397 } 398 #endif 399 #if NGPIO > 0 400 if (sc->sc_gpiobus == child) { 401 sc->sc_gpiobus = NULL; 402 return; 403 } 404 #endif 405 if (sc->sc_hpetbus != child) { 406 pcibchilddet(self, child); 407 return; 408 } 409 sc->sc_hpetbus = NULL; 410 if (sc->sc_has_ich5_hpet) { 411 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 412 LPCIB_PCI_GEN_CNTL); 413 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 414 case LPCIB_ICH5_HPTC_0000: 415 case LPCIB_ICH5_HPTC_1000: 416 case LPCIB_ICH5_HPTC_2000: 417 case LPCIB_ICH5_HPTC_3000: 418 break; 419 default: 420 return; 421 } 422 val &= ~LPCIB_ICH5_HPTC_EN; 423 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 424 LPCIB_PCI_GEN_CNTL, val); 425 } else if (sc->sc_has_rcba) { 426 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 427 LPCIB_RCBA_HPTC); 428 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 429 case LPCIB_RCBA_HPTC_0000: 430 case LPCIB_RCBA_HPTC_1000: 431 case LPCIB_RCBA_HPTC_2000: 432 case LPCIB_RCBA_HPTC_3000: 433 break; 434 default: 435 return; 436 } 437 val &= ~LPCIB_RCBA_HPTC_EN; 438 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 439 val); 440 } 441 } 442 443 static int 444 lpcibrescan(device_t self, const char *ifattr, const int *locators) 445 { 446 struct lpcib_softc *sc = device_private(self); 447 448 #if NFWHRNG > 0 449 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 450 lpcib_fwh_configure(self); 451 #endif 452 453 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 454 lpcib_hpet_configure(self); 455 456 #if NGPIO > 0 457 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 458 lpcib_gpio_configure(self); 459 #endif 460 461 return pcibrescan(self, ifattr, locators); 462 } 463 464 static int 465 lpcibdetach(device_t self, int flags) 466 { 467 struct lpcib_softc *sc = device_private(self); 468 int rc; 469 470 pmf_device_deregister(self); 471 472 #if NFWHRNG > 0 473 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 474 return rc; 475 #endif 476 477 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 478 return rc; 479 480 #if NGPIO > 0 481 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 482 return rc; 483 #endif 484 485 /* Set up SpeedStep. */ 486 speedstep_unconfigure(self); 487 488 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 489 return rc; 490 491 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 492 return rc; 493 494 if (sc->sc_has_rcba) 495 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 496 497 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 498 499 return pcibdetach(self, flags); 500 } 501 502 static bool 503 lpcib_shutdown(device_t dv, int howto) 504 { 505 struct lpcib_softc *sc = device_private(dv); 506 507 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 508 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 509 510 return true; 511 } 512 513 static bool 514 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 515 { 516 struct lpcib_softc *sc = device_private(dv); 517 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 518 pcitag_t tag = sc->sc_pcib.sc_tag; 519 520 /* capture PIRQ routing control registers */ 521 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 522 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 523 524 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 525 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 526 527 if (sc->sc_has_rcba) { 528 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 529 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 530 LPCIB_RCBA_HPTC); 531 } else if (sc->sc_has_ich5_hpet) { 532 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 533 } 534 535 return true; 536 } 537 538 static bool 539 lpcib_resume(device_t dv, const pmf_qual_t *qual) 540 { 541 struct lpcib_softc *sc = device_private(dv); 542 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 543 pcitag_t tag = sc->sc_pcib.sc_tag; 544 545 /* restore PIRQ routing control registers */ 546 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 547 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 548 549 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 550 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 551 552 if (sc->sc_has_rcba) { 553 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 554 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 555 sc->sc_hpet_reg); 556 } else if (sc->sc_has_ich5_hpet) { 557 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 558 } 559 560 return true; 561 } 562 563 /* 564 * Initialize the power management timer. 565 */ 566 static void 567 pmtimer_configure(device_t self) 568 { 569 struct lpcib_softc *sc = device_private(self); 570 pcireg_t control; 571 572 /* 573 * Check if power management I/O space is enabled and enable the ACPI_EN 574 * bit if it's disabled. 575 */ 576 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 577 LPCIB_PCI_ACPI_CNTL); 578 sc->sc_acpi_cntl = control; 579 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 580 control |= LPCIB_PCI_ACPI_CNTL_EN; 581 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 582 LPCIB_PCI_ACPI_CNTL, control); 583 } 584 585 /* Attach our PM timer with the generic acpipmtimer function */ 586 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 587 LPCIB_PM1_TMR, 0); 588 } 589 590 static int 591 pmtimer_unconfigure(device_t self, int flags) 592 { 593 struct lpcib_softc *sc = device_private(self); 594 int rc; 595 596 if (sc->sc_pmtimer != NULL && 597 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 598 return rc; 599 600 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 601 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 602 603 return 0; 604 } 605 606 /* 607 * Initialize the watchdog timer. 608 */ 609 static void 610 tcotimer_configure(device_t self) 611 { 612 struct lpcib_softc *sc = device_private(self); 613 uint32_t ioreg; 614 unsigned int period; 615 616 /* Explicitly stop the TCO timer. */ 617 tcotimer_stop(sc); 618 619 /* 620 * Enable TCO timeout SMI only if the hardware reset does not 621 * work. We don't know what the SMBIOS does. 622 */ 623 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 624 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 625 626 /* 627 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 628 * in the SMI_EN register is the last chance. 629 */ 630 if (tcotimer_disable_noreboot(self)) { 631 ioreg |= LPCIB_SMI_EN_TCO_EN; 632 } 633 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 634 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 635 } 636 637 /* Reset the watchdog status registers. */ 638 tcotimer_status_reset(sc); 639 640 /* 641 * Register the driver with the sysmon watchdog framework. 642 */ 643 sc->sc_smw.smw_name = device_xname(self); 644 sc->sc_smw.smw_cookie = sc; 645 sc->sc_smw.smw_setmode = tcotimer_setmode; 646 sc->sc_smw.smw_tickle = tcotimer_tickle; 647 if (sc->sc_has_rcba) 648 period = LPCIB_TCOTIMER2_MAX_TICK; 649 else 650 period = LPCIB_TCOTIMER_MAX_TICK; 651 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 652 653 if (sysmon_wdog_register(&sc->sc_smw)) { 654 aprint_error_dev(self, "unable to register TCO timer" 655 "as a sysmon watchdog device.\n"); 656 return; 657 } 658 659 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 660 } 661 662 static int 663 tcotimer_unconfigure(device_t self, int flags) 664 { 665 struct lpcib_softc *sc = device_private(self); 666 int rc; 667 668 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 669 if (rc == ERESTART) 670 rc = EINTR; 671 return rc; 672 } 673 674 /* Explicitly stop the TCO timer. */ 675 tcotimer_stop(sc); 676 677 /* XXX Set No Reboot? */ 678 679 return 0; 680 } 681 682 683 /* 684 * Sysmon watchdog callbacks. 685 */ 686 static int 687 tcotimer_setmode(struct sysmon_wdog *smw) 688 { 689 struct lpcib_softc *sc = smw->smw_cookie; 690 unsigned int period; 691 uint16_t ich6period = 0; 692 uint8_t ich5period = 0; 693 694 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 695 /* Stop the TCO timer. */ 696 tcotimer_stop(sc); 697 } else { 698 /* 699 * ICH6 or newer are limited to 2s min and 613s max. 700 * ICH5 or older are limited to 4s min and 39s max. 701 */ 702 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 703 if (sc->sc_has_rcba) { 704 if (period < LPCIB_TCOTIMER2_MIN_TICK || 705 period > LPCIB_TCOTIMER2_MAX_TICK) 706 return EINVAL; 707 } else { 708 if (period < LPCIB_TCOTIMER_MIN_TICK || 709 period > LPCIB_TCOTIMER_MAX_TICK) 710 return EINVAL; 711 } 712 713 /* Stop the TCO timer, */ 714 tcotimer_stop(sc); 715 716 /* set the timeout, */ 717 if (sc->sc_has_rcba) { 718 /* ICH6 or newer */ 719 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 720 LPCIB_TCO_TMR2); 721 ich6period &= 0xfc00; 722 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 723 LPCIB_TCO_TMR2, ich6period | period); 724 } else { 725 /* ICH5 or older */ 726 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 727 LPCIB_TCO_TMR); 728 ich5period &= 0xc0; 729 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 730 LPCIB_TCO_TMR, ich5period | period); 731 } 732 733 /* and start/reload the timer. */ 734 tcotimer_start(sc); 735 tcotimer_tickle(smw); 736 } 737 738 return 0; 739 } 740 741 static int 742 tcotimer_tickle(struct sysmon_wdog *smw) 743 { 744 struct lpcib_softc *sc = smw->smw_cookie; 745 746 /* any value is allowed */ 747 if (sc->sc_has_rcba) 748 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 749 else 750 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 751 752 return 0; 753 } 754 755 static void 756 tcotimer_stop(struct lpcib_softc *sc) 757 { 758 uint16_t ioreg; 759 760 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 761 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 762 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 763 } 764 765 static void 766 tcotimer_start(struct lpcib_softc *sc) 767 { 768 uint16_t ioreg; 769 770 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 771 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 772 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 773 } 774 775 static void 776 tcotimer_status_reset(struct lpcib_softc *sc) 777 { 778 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 779 LPCIB_TCO1_STS_TIMEOUT); 780 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 781 LPCIB_TCO2_STS_BOOT_STS); 782 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 783 LPCIB_TCO2_STS_SECONDS_TO_STS); 784 } 785 786 /* 787 * Clear the No Reboot (NR) bit, this enables reboots when the timer 788 * reaches the timeout for the second time. 789 */ 790 static int 791 tcotimer_disable_noreboot(device_t self) 792 { 793 struct lpcib_softc *sc = device_private(self); 794 795 if (sc->sc_has_rcba) { 796 uint32_t status; 797 798 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 799 LPCIB_GCS_OFFSET); 800 status &= ~LPCIB_GCS_NO_REBOOT; 801 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 802 LPCIB_GCS_OFFSET, status); 803 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 804 LPCIB_GCS_OFFSET); 805 if (status & LPCIB_GCS_NO_REBOOT) 806 goto error; 807 } else { 808 pcireg_t pcireg; 809 810 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 811 LPCIB_PCI_GEN_STA); 812 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 813 /* TCO timeout reset is disabled; try to enable it */ 814 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 815 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 816 LPCIB_PCI_GEN_STA, pcireg); 817 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 818 goto error; 819 } 820 } 821 822 return 0; 823 error: 824 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 825 "hope SMBIOS properly handles it.\n"); 826 return EINVAL; 827 } 828 829 830 /* 831 * Intel ICH SpeedStep support. 832 */ 833 #define SS_READ(sc, reg) \ 834 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 835 #define SS_WRITE(sc, reg, val) \ 836 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 837 838 /* 839 * Linux driver says that SpeedStep on older chipsets cause 840 * lockups on Dell Inspiron 8000 and 8100. 841 * It should also not be enabled on systems with the 82855GM 842 * Hub, which typically have an EST-enabled CPU. 843 */ 844 static int 845 speedstep_bad_hb_check(const struct pci_attach_args *pa) 846 { 847 848 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 849 PCI_REVISION(pa->pa_class) < 5) 850 return 1; 851 852 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 853 return 1; 854 855 return 0; 856 } 857 858 static void 859 speedstep_configure(device_t self) 860 { 861 struct lpcib_softc *sc = device_private(self); 862 const struct sysctlnode *node, *ssnode; 863 int rv; 864 865 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 866 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 867 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 868 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 869 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 870 pcireg_t pmcon; 871 872 /* Enable SpeedStep if it isn't already enabled. */ 873 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 874 LPCIB_PCI_GEN_PMCON_1); 875 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 876 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 877 LPCIB_PCI_GEN_PMCON_1, 878 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 879 880 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 881 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 882 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 883 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 884 goto err; 885 886 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 887 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 888 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 889 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 890 CTL_EOL)) != 0) 891 goto err; 892 893 /* XXX save the sc for IO tag/handle */ 894 speedstep_cookie = sc; 895 aprint_verbose_dev(self, "SpeedStep enabled\n"); 896 } 897 898 return; 899 900 err: 901 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 902 } 903 904 static void 905 speedstep_unconfigure(device_t self) 906 { 907 struct lpcib_softc *sc = device_private(self); 908 909 sysctl_teardown(&sc->sc_log); 910 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 911 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 912 913 speedstep_cookie = NULL; 914 } 915 916 /* 917 * get/set the SpeedStep state: 0 == low power, 1 == high power. 918 */ 919 static int 920 speedstep_sysctl_helper(SYSCTLFN_ARGS) 921 { 922 struct sysctlnode node; 923 struct lpcib_softc *sc = speedstep_cookie; 924 uint8_t state, state2; 925 int ostate, nstate, s, error = 0; 926 927 /* 928 * We do the dance with spl's to avoid being at high ipl during 929 * sysctl_lookup() which can both copyin and copyout. 930 */ 931 s = splserial(); 932 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 933 splx(s); 934 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 935 ostate = 1; 936 else 937 ostate = 0; 938 nstate = ostate; 939 940 node = *rnode; 941 node.sysctl_data = &nstate; 942 943 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 944 if (error || newp == NULL) 945 goto out; 946 947 /* Only two states are available */ 948 if (nstate != 0 && nstate != 1) { 949 error = EINVAL; 950 goto out; 951 } 952 953 s = splserial(); 954 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 955 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 956 ostate = 1; 957 else 958 ostate = 0; 959 960 if (ostate != nstate) { 961 uint8_t cntl; 962 963 if (nstate == 0) 964 state2 |= LPCIB_PM_SS_STATE_LOW; 965 else 966 state2 &= ~LPCIB_PM_SS_STATE_LOW; 967 968 /* 969 * Must disable bus master arbitration during the change. 970 */ 971 cntl = SS_READ(sc, LPCIB_PM_CTRL); 972 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 973 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 974 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 975 } 976 splx(s); 977 out: 978 return error; 979 } 980 981 static void 982 lpcib_hpet_configure(device_t self) 983 { 984 struct lpcib_softc *sc = device_private(self); 985 struct lpcib_hpet_attach_args arg; 986 uint32_t hpet_reg, val; 987 988 if (sc->sc_has_ich5_hpet) { 989 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 990 LPCIB_PCI_GEN_CNTL); 991 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 992 case LPCIB_ICH5_HPTC_0000: 993 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 994 break; 995 case LPCIB_ICH5_HPTC_1000: 996 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 997 break; 998 case LPCIB_ICH5_HPTC_2000: 999 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 1000 break; 1001 case LPCIB_ICH5_HPTC_3000: 1002 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 1003 break; 1004 default: 1005 return; 1006 } 1007 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 1008 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1009 LPCIB_PCI_GEN_CNTL, val); 1010 } else if (sc->sc_has_rcba) { 1011 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 1012 LPCIB_RCBA_HPTC); 1013 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 1014 case LPCIB_RCBA_HPTC_0000: 1015 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 1016 break; 1017 case LPCIB_RCBA_HPTC_1000: 1018 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 1019 break; 1020 case LPCIB_RCBA_HPTC_2000: 1021 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1022 break; 1023 case LPCIB_RCBA_HPTC_3000: 1024 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1025 break; 1026 default: 1027 return; 1028 } 1029 val |= LPCIB_RCBA_HPTC_EN; 1030 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1031 val); 1032 } else { 1033 /* No HPET here */ 1034 return; 1035 } 1036 1037 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1038 arg.hpet_reg = hpet_reg; 1039 1040 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1041 } 1042 1043 static int 1044 lpcib_hpet_unconfigure(device_t self, int flags) 1045 { 1046 struct lpcib_softc *sc = device_private(self); 1047 int rc; 1048 1049 if (sc->sc_hpetbus != NULL && 1050 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1051 return rc; 1052 1053 return 0; 1054 } 1055 1056 #if NGPIO > 0 1057 static void 1058 lpcib_gpio_configure(device_t self) 1059 { 1060 struct lpcib_softc *sc = device_private(self); 1061 struct gpiobus_attach_args gba; 1062 pcireg_t gpio_cntl; 1063 uint32_t use, io, bit; 1064 int pin, shift, base_reg, cntl_reg, reg; 1065 int rv; 1066 1067 /* this implies ICH >= 6, and thus different mapreg */ 1068 if (sc->sc_has_rcba) { 1069 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1070 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1071 } else { 1072 base_reg = LPCIB_PCI_GPIO_BASE; 1073 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1074 } 1075 1076 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1077 cntl_reg); 1078 1079 /* Is GPIO enabled? */ 1080 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1081 return; 1082 /* 1083 * The GPIO_BASE register is alike PCI BAR but not completely 1084 * compatible with it. The PMBASE define the base address and the type 1085 * but not describe the size. 1086 */ 1087 rv = pci_mapreg_submap(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0, 1088 LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_iot, &sc->sc_gpio_ioh, 1089 NULL, &sc->sc_gpio_ios); 1090 if (rv != 0) { 1091 aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv); 1092 return; 1093 } 1094 1095 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1096 1097 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1098 sc->sc_gpio_pins[pin].pin_num = pin; 1099 1100 /* Read initial state */ 1101 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1102 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1103 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1104 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1105 shift = pin % 32; 1106 bit = __BIT(shift); 1107 1108 if ((use & bit) != 0) { 1109 sc->sc_gpio_pins[pin].pin_caps = 1110 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1111 if (pin < 32) 1112 sc->sc_gpio_pins[pin].pin_caps |= 1113 GPIO_PIN_PULSATE; 1114 if ((io & bit) != 0) 1115 sc->sc_gpio_pins[pin].pin_flags = 1116 GPIO_PIN_INPUT; 1117 else 1118 sc->sc_gpio_pins[pin].pin_flags = 1119 GPIO_PIN_OUTPUT; 1120 } else 1121 sc->sc_gpio_pins[pin].pin_caps = 0; 1122 1123 if (lpcib_gpio_pin_read(sc, pin) == 0) 1124 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1125 else 1126 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1127 1128 } 1129 1130 /* Create controller tag */ 1131 sc->sc_gpio_gc.gp_cookie = sc; 1132 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1133 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1134 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1135 1136 memset(&gba, 0, sizeof(gba)); 1137 1138 gba.gba_gc = &sc->sc_gpio_gc; 1139 gba.gba_pins = sc->sc_gpio_pins; 1140 gba.gba_npins = LPCIB_GPIO_NPINS; 1141 1142 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1143 } 1144 1145 static int 1146 lpcib_gpio_unconfigure(device_t self, int flags) 1147 { 1148 struct lpcib_softc *sc = device_private(self); 1149 int rc; 1150 1151 if (sc->sc_gpiobus != NULL && 1152 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1153 return rc; 1154 1155 mutex_destroy(&sc->sc_gpio_mtx); 1156 1157 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1158 1159 return 0; 1160 } 1161 1162 static int 1163 lpcib_gpio_pin_read(void *arg, int pin) 1164 { 1165 struct lpcib_softc *sc = arg; 1166 uint32_t data; 1167 int reg, shift; 1168 1169 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1170 shift = pin % 32; 1171 1172 mutex_enter(&sc->sc_gpio_mtx); 1173 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1174 mutex_exit(&sc->sc_gpio_mtx); 1175 1176 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1177 } 1178 1179 static void 1180 lpcib_gpio_pin_write(void *arg, int pin, int value) 1181 { 1182 struct lpcib_softc *sc = arg; 1183 uint32_t data; 1184 int reg, shift; 1185 1186 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1187 shift = pin % 32; 1188 1189 mutex_enter(&sc->sc_gpio_mtx); 1190 1191 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1192 1193 if(value) 1194 data |= __BIT(shift); 1195 else 1196 data &= ~__BIT(shift); 1197 1198 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1199 1200 mutex_exit(&sc->sc_gpio_mtx); 1201 } 1202 1203 static void 1204 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1205 { 1206 struct lpcib_softc *sc = arg; 1207 uint32_t data; 1208 int reg, shift; 1209 1210 shift = pin % 32; 1211 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1212 1213 mutex_enter(&sc->sc_gpio_mtx); 1214 1215 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1216 1217 if (flags & GPIO_PIN_OUTPUT) 1218 data &= ~__BIT(shift); 1219 1220 if (flags & GPIO_PIN_INPUT) 1221 data |= __BIT(shift); 1222 1223 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1224 1225 1226 if (pin < 32) { 1227 reg = LPCIB_GPIO_GPO_BLINK; 1228 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1229 1230 if (flags & GPIO_PIN_PULSATE) 1231 data |= __BIT(shift); 1232 else 1233 data &= ~__BIT(shift); 1234 1235 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1236 } 1237 1238 mutex_exit(&sc->sc_gpio_mtx); 1239 } 1240 #endif 1241 1242 #if NFWHRNG > 0 1243 static void 1244 lpcib_fwh_configure(device_t self) 1245 { 1246 struct lpcib_softc *sc; 1247 pcireg_t pr; 1248 1249 sc = device_private(self); 1250 1251 if (sc->sc_has_rcba) { 1252 /* 1253 * Very unlikely to find a 82802 on a ICH6 or newer. 1254 * Also the write enable register moved at that point. 1255 */ 1256 return; 1257 } else { 1258 /* Enable FWH write to identify FWH. */ 1259 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1260 LPCIB_PCI_BIOS_CNTL); 1261 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1262 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1263 } 1264 1265 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1266 1267 /* restore previous write enable setting */ 1268 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1269 LPCIB_PCI_BIOS_CNTL, pr); 1270 } 1271 1272 static int 1273 lpcib_fwh_unconfigure(device_t self, int flags) 1274 { 1275 struct lpcib_softc *sc = device_private(self); 1276 int rc; 1277 1278 if (sc->sc_fwhbus != NULL && 1279 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1280 return rc; 1281 1282 return 0; 1283 } 1284 #endif 1285
Indexes created Tue Sep 30 10:09:55 GMT 2025