ichlpcib.c revision 1.46
1 /* $NetBSD: ichlpcib.c,v 1.46 2015/01/13 08:57:02 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.46 2015/01/13 08:57:02 msaitoh Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z68_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 264 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_LPC, 1, 0 }, 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCL_LPC, 1, 0 }, 267 #if 0 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 270 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 272 #endif 273 274 { 0, 0, 0, 0 }, 275 }; 276 277 /* 278 * Autoconf callbacks. 279 */ 280 static int 281 lpcibmatch(device_t parent, cfdata_t match, void *aux) 282 { 283 struct pci_attach_args *pa = aux; 284 struct lpcib_device *lpcib_dev; 285 286 /* We are ISA bridge, of course */ 287 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 288 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 289 return 0; 290 291 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 292 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 293 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 294 return 10; 295 } 296 297 return 0; 298 } 299 300 static void 301 lpcibattach(device_t parent, device_t self, void *aux) 302 { 303 struct pci_attach_args *pa = aux; 304 struct lpcib_softc *sc = device_private(self); 305 struct lpcib_device *lpcib_dev; 306 pcireg_t pmbase; 307 308 sc->sc_pa = *pa; 309 310 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 311 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 312 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 313 continue; 314 sc->sc_has_rcba = lpcib_dev->has_rcba; 315 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 316 break; 317 } 318 319 pcibattach(parent, self, aux); 320 321 /* 322 * Part of our I/O registers are used as ACPI PM regs. 323 * Since our ACPI subsystem accesses the I/O space directly so far, 324 * we do not have to bother bus_space I/O map confliction. 325 * 326 * The PMBASE register is alike PCI BAR but not completely compatible 327 * with it. The PMBASE define the base address and the type but 328 * not describe the size. The value of the register may be lower 329 * than LPCIB_PCI_PM_SIZE. It makes impossible to use 330 * pci_mapreg_submap() because the function does range check. 331 */ 332 sc->sc_iot = pa->pa_iot; 333 pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE); 334 if (bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(pmbase), 335 LPCIB_PCI_PM_SIZE, 0, &sc->sc_ioh) != 0) { 336 aprint_error_dev(self, 337 "can't map power management i/o space\n"); 338 return; 339 } 340 341 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 342 LPCIB_PCI_GEN_PMCON_1); 343 344 /* For ICH6 and later, always enable RCBA */ 345 if (sc->sc_has_rcba) { 346 pcireg_t rcba; 347 348 sc->sc_rcbat = sc->sc_pa.pa_memt; 349 350 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 351 LPCIB_RCBA); 352 if ((rcba & LPCIB_RCBA_EN) == 0) { 353 aprint_error_dev(self, "RCBA is not enabled\n"); 354 return; 355 } 356 rcba &= ~LPCIB_RCBA_EN; 357 358 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 359 &sc->sc_rcbah)) { 360 aprint_error_dev(self, "RCBA could not be mapped\n"); 361 return; 362 } 363 } 364 365 /* Set up the power management timer. */ 366 pmtimer_configure(self); 367 368 /* Set up the TCO (watchdog). */ 369 tcotimer_configure(self); 370 371 /* Set up SpeedStep. */ 372 speedstep_configure(self); 373 374 /* Set up HPET. */ 375 lpcib_hpet_configure(self); 376 377 #if NGPIO > 0 378 /* Set up GPIO */ 379 lpcib_gpio_configure(self); 380 #endif 381 382 #if NFWHRNG > 0 383 lpcib_fwh_configure(self); 384 #endif 385 386 /* Install power handler */ 387 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 388 lpcib_shutdown)) 389 aprint_error_dev(self, "couldn't establish power handler\n"); 390 } 391 392 static void 393 lpcibchilddet(device_t self, device_t child) 394 { 395 struct lpcib_softc *sc = device_private(self); 396 uint32_t val; 397 398 #if NFWHRNG > 0 399 if (sc->sc_fwhbus == child) { 400 sc->sc_fwhbus = NULL; 401 return; 402 } 403 #endif 404 #if NGPIO > 0 405 if (sc->sc_gpiobus == child) { 406 sc->sc_gpiobus = NULL; 407 return; 408 } 409 #endif 410 if (sc->sc_hpetbus != child) { 411 pcibchilddet(self, child); 412 return; 413 } 414 sc->sc_hpetbus = NULL; 415 if (sc->sc_has_ich5_hpet) { 416 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 417 LPCIB_PCI_GEN_CNTL); 418 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 419 case LPCIB_ICH5_HPTC_0000: 420 case LPCIB_ICH5_HPTC_1000: 421 case LPCIB_ICH5_HPTC_2000: 422 case LPCIB_ICH5_HPTC_3000: 423 break; 424 default: 425 return; 426 } 427 val &= ~LPCIB_ICH5_HPTC_EN; 428 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 429 LPCIB_PCI_GEN_CNTL, val); 430 } else if (sc->sc_has_rcba) { 431 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 432 LPCIB_RCBA_HPTC); 433 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 434 case LPCIB_RCBA_HPTC_0000: 435 case LPCIB_RCBA_HPTC_1000: 436 case LPCIB_RCBA_HPTC_2000: 437 case LPCIB_RCBA_HPTC_3000: 438 break; 439 default: 440 return; 441 } 442 val &= ~LPCIB_RCBA_HPTC_EN; 443 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 444 val); 445 } 446 } 447 448 static int 449 lpcibrescan(device_t self, const char *ifattr, const int *locators) 450 { 451 struct lpcib_softc *sc = device_private(self); 452 453 #if NFWHRNG > 0 454 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 455 lpcib_fwh_configure(self); 456 #endif 457 458 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 459 lpcib_hpet_configure(self); 460 461 #if NGPIO > 0 462 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 463 lpcib_gpio_configure(self); 464 #endif 465 466 return pcibrescan(self, ifattr, locators); 467 } 468 469 static int 470 lpcibdetach(device_t self, int flags) 471 { 472 struct lpcib_softc *sc = device_private(self); 473 int rc; 474 475 pmf_device_deregister(self); 476 477 #if NFWHRNG > 0 478 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 479 return rc; 480 #endif 481 482 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 483 return rc; 484 485 #if NGPIO > 0 486 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 487 return rc; 488 #endif 489 490 /* Set up SpeedStep. */ 491 speedstep_unconfigure(self); 492 493 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 494 return rc; 495 496 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 497 return rc; 498 499 if (sc->sc_has_rcba) 500 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 501 502 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 503 504 return pcibdetach(self, flags); 505 } 506 507 static bool 508 lpcib_shutdown(device_t dv, int howto) 509 { 510 struct lpcib_softc *sc = device_private(dv); 511 512 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 513 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 514 515 return true; 516 } 517 518 static bool 519 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 520 { 521 struct lpcib_softc *sc = device_private(dv); 522 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 523 pcitag_t tag = sc->sc_pcib.sc_tag; 524 525 /* capture PIRQ routing control registers */ 526 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 527 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 528 529 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 530 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 531 532 if (sc->sc_has_rcba) { 533 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 534 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 535 LPCIB_RCBA_HPTC); 536 } else if (sc->sc_has_ich5_hpet) { 537 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 538 } 539 540 return true; 541 } 542 543 static bool 544 lpcib_resume(device_t dv, const pmf_qual_t *qual) 545 { 546 struct lpcib_softc *sc = device_private(dv); 547 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 548 pcitag_t tag = sc->sc_pcib.sc_tag; 549 550 /* restore PIRQ routing control registers */ 551 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 552 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 553 554 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 555 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 556 557 if (sc->sc_has_rcba) { 558 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 559 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 560 sc->sc_hpet_reg); 561 } else if (sc->sc_has_ich5_hpet) { 562 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 563 } 564 565 return true; 566 } 567 568 /* 569 * Initialize the power management timer. 570 */ 571 static void 572 pmtimer_configure(device_t self) 573 { 574 struct lpcib_softc *sc = device_private(self); 575 pcireg_t control; 576 577 /* 578 * Check if power management I/O space is enabled and enable the ACPI_EN 579 * bit if it's disabled. 580 */ 581 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 582 LPCIB_PCI_ACPI_CNTL); 583 sc->sc_acpi_cntl = control; 584 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 585 control |= LPCIB_PCI_ACPI_CNTL_EN; 586 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 587 LPCIB_PCI_ACPI_CNTL, control); 588 } 589 590 /* Attach our PM timer with the generic acpipmtimer function */ 591 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 592 LPCIB_PM1_TMR, 0); 593 } 594 595 static int 596 pmtimer_unconfigure(device_t self, int flags) 597 { 598 struct lpcib_softc *sc = device_private(self); 599 int rc; 600 601 if (sc->sc_pmtimer != NULL && 602 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 603 return rc; 604 605 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 606 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 607 608 return 0; 609 } 610 611 /* 612 * Initialize the watchdog timer. 613 */ 614 static void 615 tcotimer_configure(device_t self) 616 { 617 struct lpcib_softc *sc = device_private(self); 618 uint32_t ioreg; 619 unsigned int period; 620 621 /* Explicitly stop the TCO timer. */ 622 tcotimer_stop(sc); 623 624 /* 625 * Enable TCO timeout SMI only if the hardware reset does not 626 * work. We don't know what the SMBIOS does. 627 */ 628 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 629 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 630 631 /* 632 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 633 * in the SMI_EN register is the last chance. 634 */ 635 if (tcotimer_disable_noreboot(self)) { 636 ioreg |= LPCIB_SMI_EN_TCO_EN; 637 } 638 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 639 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 640 } 641 642 /* Reset the watchdog status registers. */ 643 tcotimer_status_reset(sc); 644 645 /* 646 * Register the driver with the sysmon watchdog framework. 647 */ 648 sc->sc_smw.smw_name = device_xname(self); 649 sc->sc_smw.smw_cookie = sc; 650 sc->sc_smw.smw_setmode = tcotimer_setmode; 651 sc->sc_smw.smw_tickle = tcotimer_tickle; 652 if (sc->sc_has_rcba) 653 period = LPCIB_TCOTIMER2_MAX_TICK; 654 else 655 period = LPCIB_TCOTIMER_MAX_TICK; 656 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 657 658 if (sysmon_wdog_register(&sc->sc_smw)) { 659 aprint_error_dev(self, "unable to register TCO timer" 660 "as a sysmon watchdog device.\n"); 661 return; 662 } 663 664 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 665 } 666 667 static int 668 tcotimer_unconfigure(device_t self, int flags) 669 { 670 struct lpcib_softc *sc = device_private(self); 671 int rc; 672 673 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 674 if (rc == ERESTART) 675 rc = EINTR; 676 return rc; 677 } 678 679 /* Explicitly stop the TCO timer. */ 680 tcotimer_stop(sc); 681 682 /* XXX Set No Reboot? */ 683 684 return 0; 685 } 686 687 688 /* 689 * Sysmon watchdog callbacks. 690 */ 691 static int 692 tcotimer_setmode(struct sysmon_wdog *smw) 693 { 694 struct lpcib_softc *sc = smw->smw_cookie; 695 unsigned int period; 696 uint16_t ich6period = 0; 697 uint8_t ich5period = 0; 698 699 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 700 /* Stop the TCO timer. */ 701 tcotimer_stop(sc); 702 } else { 703 /* 704 * ICH6 or newer are limited to 2s min and 613s max. 705 * ICH5 or older are limited to 4s min and 39s max. 706 */ 707 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 708 if (sc->sc_has_rcba) { 709 if (period < LPCIB_TCOTIMER2_MIN_TICK || 710 period > LPCIB_TCOTIMER2_MAX_TICK) 711 return EINVAL; 712 } else { 713 if (period < LPCIB_TCOTIMER_MIN_TICK || 714 period > LPCIB_TCOTIMER_MAX_TICK) 715 return EINVAL; 716 } 717 718 /* Stop the TCO timer, */ 719 tcotimer_stop(sc); 720 721 /* set the timeout, */ 722 if (sc->sc_has_rcba) { 723 /* ICH6 or newer */ 724 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 725 LPCIB_TCO_TMR2); 726 ich6period &= 0xfc00; 727 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 728 LPCIB_TCO_TMR2, ich6period | period); 729 } else { 730 /* ICH5 or older */ 731 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 732 LPCIB_TCO_TMR); 733 ich5period &= 0xc0; 734 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 735 LPCIB_TCO_TMR, ich5period | period); 736 } 737 738 /* and start/reload the timer. */ 739 tcotimer_start(sc); 740 tcotimer_tickle(smw); 741 } 742 743 return 0; 744 } 745 746 static int 747 tcotimer_tickle(struct sysmon_wdog *smw) 748 { 749 struct lpcib_softc *sc = smw->smw_cookie; 750 751 /* any value is allowed */ 752 if (sc->sc_has_rcba) 753 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 754 else 755 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 756 757 return 0; 758 } 759 760 static void 761 tcotimer_stop(struct lpcib_softc *sc) 762 { 763 uint16_t ioreg; 764 765 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 766 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 767 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 768 } 769 770 static void 771 tcotimer_start(struct lpcib_softc *sc) 772 { 773 uint16_t ioreg; 774 775 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 776 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 777 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 778 } 779 780 static void 781 tcotimer_status_reset(struct lpcib_softc *sc) 782 { 783 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 784 LPCIB_TCO1_STS_TIMEOUT); 785 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 786 LPCIB_TCO2_STS_BOOT_STS); 787 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 788 LPCIB_TCO2_STS_SECONDS_TO_STS); 789 } 790 791 /* 792 * Clear the No Reboot (NR) bit, this enables reboots when the timer 793 * reaches the timeout for the second time. 794 */ 795 static int 796 tcotimer_disable_noreboot(device_t self) 797 { 798 struct lpcib_softc *sc = device_private(self); 799 800 if (sc->sc_has_rcba) { 801 uint32_t status; 802 803 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 804 LPCIB_GCS_OFFSET); 805 status &= ~LPCIB_GCS_NO_REBOOT; 806 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 807 LPCIB_GCS_OFFSET, status); 808 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 809 LPCIB_GCS_OFFSET); 810 if (status & LPCIB_GCS_NO_REBOOT) 811 goto error; 812 } else { 813 pcireg_t pcireg; 814 815 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 816 LPCIB_PCI_GEN_STA); 817 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 818 /* TCO timeout reset is disabled; try to enable it */ 819 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 820 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 821 LPCIB_PCI_GEN_STA, pcireg); 822 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 823 goto error; 824 } 825 } 826 827 return 0; 828 error: 829 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 830 "hope SMBIOS properly handles it.\n"); 831 return EINVAL; 832 } 833 834 835 /* 836 * Intel ICH SpeedStep support. 837 */ 838 #define SS_READ(sc, reg) \ 839 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 840 #define SS_WRITE(sc, reg, val) \ 841 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 842 843 /* 844 * Linux driver says that SpeedStep on older chipsets cause 845 * lockups on Dell Inspiron 8000 and 8100. 846 * It should also not be enabled on systems with the 82855GM 847 * Hub, which typically have an EST-enabled CPU. 848 */ 849 static int 850 speedstep_bad_hb_check(const struct pci_attach_args *pa) 851 { 852 853 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 854 PCI_REVISION(pa->pa_class) < 5) 855 return 1; 856 857 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 858 return 1; 859 860 return 0; 861 } 862 863 static void 864 speedstep_configure(device_t self) 865 { 866 struct lpcib_softc *sc = device_private(self); 867 const struct sysctlnode *node, *ssnode; 868 int rv; 869 870 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 871 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 872 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 873 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 874 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 875 pcireg_t pmcon; 876 877 /* Enable SpeedStep if it isn't already enabled. */ 878 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 879 LPCIB_PCI_GEN_PMCON_1); 880 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 881 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 882 LPCIB_PCI_GEN_PMCON_1, 883 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 884 885 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 886 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 887 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 888 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 889 goto err; 890 891 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 892 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 893 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 894 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 895 CTL_EOL)) != 0) 896 goto err; 897 898 /* XXX save the sc for IO tag/handle */ 899 speedstep_cookie = sc; 900 aprint_verbose_dev(self, "SpeedStep enabled\n"); 901 } 902 903 return; 904 905 err: 906 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 907 } 908 909 static void 910 speedstep_unconfigure(device_t self) 911 { 912 struct lpcib_softc *sc = device_private(self); 913 914 sysctl_teardown(&sc->sc_log); 915 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 916 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 917 918 speedstep_cookie = NULL; 919 } 920 921 /* 922 * get/set the SpeedStep state: 0 == low power, 1 == high power. 923 */ 924 static int 925 speedstep_sysctl_helper(SYSCTLFN_ARGS) 926 { 927 struct sysctlnode node; 928 struct lpcib_softc *sc = speedstep_cookie; 929 uint8_t state, state2; 930 int ostate, nstate, s, error = 0; 931 932 /* 933 * We do the dance with spl's to avoid being at high ipl during 934 * sysctl_lookup() which can both copyin and copyout. 935 */ 936 s = splserial(); 937 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 938 splx(s); 939 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 940 ostate = 1; 941 else 942 ostate = 0; 943 nstate = ostate; 944 945 node = *rnode; 946 node.sysctl_data = &nstate; 947 948 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 949 if (error || newp == NULL) 950 goto out; 951 952 /* Only two states are available */ 953 if (nstate != 0 && nstate != 1) { 954 error = EINVAL; 955 goto out; 956 } 957 958 s = splserial(); 959 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 960 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 961 ostate = 1; 962 else 963 ostate = 0; 964 965 if (ostate != nstate) { 966 uint8_t cntl; 967 968 if (nstate == 0) 969 state2 |= LPCIB_PM_SS_STATE_LOW; 970 else 971 state2 &= ~LPCIB_PM_SS_STATE_LOW; 972 973 /* 974 * Must disable bus master arbitration during the change. 975 */ 976 cntl = SS_READ(sc, LPCIB_PM_CTRL); 977 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 978 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 979 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 980 } 981 splx(s); 982 out: 983 return error; 984 } 985 986 static void 987 lpcib_hpet_configure(device_t self) 988 { 989 struct lpcib_softc *sc = device_private(self); 990 struct lpcib_hpet_attach_args arg; 991 uint32_t hpet_reg, val; 992 993 if (sc->sc_has_ich5_hpet) { 994 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 995 LPCIB_PCI_GEN_CNTL); 996 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 997 case LPCIB_ICH5_HPTC_0000: 998 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 999 break; 1000 case LPCIB_ICH5_HPTC_1000: 1001 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 1002 break; 1003 case LPCIB_ICH5_HPTC_2000: 1004 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 1005 break; 1006 case LPCIB_ICH5_HPTC_3000: 1007 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 1008 break; 1009 default: 1010 return; 1011 } 1012 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 1013 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1014 LPCIB_PCI_GEN_CNTL, val); 1015 } else if (sc->sc_has_rcba) { 1016 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 1017 LPCIB_RCBA_HPTC); 1018 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 1019 case LPCIB_RCBA_HPTC_0000: 1020 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 1021 break; 1022 case LPCIB_RCBA_HPTC_1000: 1023 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 1024 break; 1025 case LPCIB_RCBA_HPTC_2000: 1026 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1027 break; 1028 case LPCIB_RCBA_HPTC_3000: 1029 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1030 break; 1031 default: 1032 return; 1033 } 1034 val |= LPCIB_RCBA_HPTC_EN; 1035 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1036 val); 1037 } else { 1038 /* No HPET here */ 1039 return; 1040 } 1041 1042 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1043 arg.hpet_reg = hpet_reg; 1044 1045 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1046 } 1047 1048 static int 1049 lpcib_hpet_unconfigure(device_t self, int flags) 1050 { 1051 struct lpcib_softc *sc = device_private(self); 1052 int rc; 1053 1054 if (sc->sc_hpetbus != NULL && 1055 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1056 return rc; 1057 1058 return 0; 1059 } 1060 1061 #if NGPIO > 0 1062 static void 1063 lpcib_gpio_configure(device_t self) 1064 { 1065 struct lpcib_softc *sc = device_private(self); 1066 struct gpiobus_attach_args gba; 1067 pcireg_t gpio_cntl; 1068 uint32_t use, io, bit; 1069 int pin, shift, base_reg, cntl_reg, reg; 1070 int rv; 1071 1072 /* this implies ICH >= 6, and thus different mapreg */ 1073 if (sc->sc_has_rcba) { 1074 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1075 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1076 } else { 1077 base_reg = LPCIB_PCI_GPIO_BASE; 1078 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1079 } 1080 1081 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1082 cntl_reg); 1083 1084 /* Is GPIO enabled? */ 1085 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1086 return; 1087 /* 1088 * The GPIO_BASE register is alike PCI BAR but not completely 1089 * compatible with it. The PMBASE define the base address and the type 1090 * but not describe the size. The value of the register may be lower 1091 * than LPCIB_PCI_GPIO_SIZE. It makes impossible to use 1092 * pci_mapreg_submap() because the function does range check. 1093 */ 1094 sc->sc_gpio_iot = sc->sc_pa.pa_iot; 1095 reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg); 1096 rv = bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(reg), 1097 LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_ioh); 1098 if (rv != 0) { 1099 aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv); 1100 return; 1101 } 1102 1103 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1104 1105 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1106 sc->sc_gpio_pins[pin].pin_num = pin; 1107 1108 /* Read initial state */ 1109 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1110 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1111 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1112 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1113 shift = pin % 32; 1114 bit = __BIT(shift); 1115 1116 if ((use & bit) != 0) { 1117 sc->sc_gpio_pins[pin].pin_caps = 1118 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1119 if (pin < 32) 1120 sc->sc_gpio_pins[pin].pin_caps |= 1121 GPIO_PIN_PULSATE; 1122 if ((io & bit) != 0) 1123 sc->sc_gpio_pins[pin].pin_flags = 1124 GPIO_PIN_INPUT; 1125 else 1126 sc->sc_gpio_pins[pin].pin_flags = 1127 GPIO_PIN_OUTPUT; 1128 } else 1129 sc->sc_gpio_pins[pin].pin_caps = 0; 1130 1131 if (lpcib_gpio_pin_read(sc, pin) == 0) 1132 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1133 else 1134 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1135 1136 } 1137 1138 /* Create controller tag */ 1139 sc->sc_gpio_gc.gp_cookie = sc; 1140 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1141 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1142 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1143 1144 memset(&gba, 0, sizeof(gba)); 1145 1146 gba.gba_gc = &sc->sc_gpio_gc; 1147 gba.gba_pins = sc->sc_gpio_pins; 1148 gba.gba_npins = LPCIB_GPIO_NPINS; 1149 1150 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1151 } 1152 1153 static int 1154 lpcib_gpio_unconfigure(device_t self, int flags) 1155 { 1156 struct lpcib_softc *sc = device_private(self); 1157 int rc; 1158 1159 if (sc->sc_gpiobus != NULL && 1160 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1161 return rc; 1162 1163 mutex_destroy(&sc->sc_gpio_mtx); 1164 1165 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1166 1167 return 0; 1168 } 1169 1170 static int 1171 lpcib_gpio_pin_read(void *arg, int pin) 1172 { 1173 struct lpcib_softc *sc = arg; 1174 uint32_t data; 1175 int reg, shift; 1176 1177 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1178 shift = pin % 32; 1179 1180 mutex_enter(&sc->sc_gpio_mtx); 1181 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1182 mutex_exit(&sc->sc_gpio_mtx); 1183 1184 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1185 } 1186 1187 static void 1188 lpcib_gpio_pin_write(void *arg, int pin, int value) 1189 { 1190 struct lpcib_softc *sc = arg; 1191 uint32_t data; 1192 int reg, shift; 1193 1194 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1195 shift = pin % 32; 1196 1197 mutex_enter(&sc->sc_gpio_mtx); 1198 1199 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1200 1201 if(value) 1202 data |= __BIT(shift); 1203 else 1204 data &= ~__BIT(shift); 1205 1206 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1207 1208 mutex_exit(&sc->sc_gpio_mtx); 1209 } 1210 1211 static void 1212 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1213 { 1214 struct lpcib_softc *sc = arg; 1215 uint32_t data; 1216 int reg, shift; 1217 1218 shift = pin % 32; 1219 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1220 1221 mutex_enter(&sc->sc_gpio_mtx); 1222 1223 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1224 1225 if (flags & GPIO_PIN_OUTPUT) 1226 data &= ~__BIT(shift); 1227 1228 if (flags & GPIO_PIN_INPUT) 1229 data |= __BIT(shift); 1230 1231 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1232 1233 1234 if (pin < 32) { 1235 reg = LPCIB_GPIO_GPO_BLINK; 1236 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1237 1238 if (flags & GPIO_PIN_PULSATE) 1239 data |= __BIT(shift); 1240 else 1241 data &= ~__BIT(shift); 1242 1243 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1244 } 1245 1246 mutex_exit(&sc->sc_gpio_mtx); 1247 } 1248 #endif 1249 1250 #if NFWHRNG > 0 1251 static void 1252 lpcib_fwh_configure(device_t self) 1253 { 1254 struct lpcib_softc *sc; 1255 pcireg_t pr; 1256 1257 sc = device_private(self); 1258 1259 if (sc->sc_has_rcba) { 1260 /* 1261 * Very unlikely to find a 82802 on a ICH6 or newer. 1262 * Also the write enable register moved at that point. 1263 */ 1264 return; 1265 } else { 1266 /* Enable FWH write to identify FWH. */ 1267 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1268 LPCIB_PCI_BIOS_CNTL); 1269 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1270 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1271 } 1272 1273 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1274 1275 /* restore previous write enable setting */ 1276 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1277 LPCIB_PCI_BIOS_CNTL, pr); 1278 } 1279 1280 static int 1281 lpcib_fwh_unconfigure(device_t self, int flags) 1282 { 1283 struct lpcib_softc *sc = device_private(self); 1284 int rc; 1285 1286 if (sc->sc_fwhbus != NULL && 1287 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1288 return rc; 1289 1290 return 0; 1291 } 1292 #endif 1293
Indexes created Tue Sep 30 10:09:55 GMT 2025