ichlpcib.c revision 1.48
1 /* $NetBSD: ichlpcib.c,v 1.48 2015/03/20 12:01:32 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems) 38 * and the power management timer. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.48 2015/03/20 12:01:32 msaitoh Exp $"); 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/sysctl.h> 49 #include <sys/timetc.h> 50 #include <sys/gpio.h> 51 #include <sys/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/gpio/gpiovar.h> 58 #include <dev/sysmon/sysmonvar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include "pcibvar.h" 67 #include "gpio.h" 68 #include "fwhrng.h" 69 70 #define LPCIB_GPIO_NPINS 64 71 72 struct lpcib_softc { 73 /* we call pcibattach() which assumes this starts like this: */ 74 struct pcib_softc sc_pcib; 75 76 struct pci_attach_args sc_pa; 77 int sc_has_rcba; 78 int sc_has_ich5_hpet; 79 80 /* RCBA */ 81 bus_space_tag_t sc_rcbat; 82 bus_space_handle_t sc_rcbah; 83 pcireg_t sc_rcba_reg; 84 85 /* Watchdog variables. */ 86 struct sysmon_wdog sc_smw; 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 bus_size_t sc_iosize; 90 91 /* HPET variables. */ 92 uint32_t sc_hpet_reg; 93 94 #if NGPIO > 0 95 device_t sc_gpiobus; 96 kmutex_t sc_gpio_mtx; 97 bus_space_tag_t sc_gpio_iot; 98 bus_space_handle_t sc_gpio_ioh; 99 bus_size_t sc_gpio_ios; 100 struct gpio_chipset_tag sc_gpio_gc; 101 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 102 #endif 103 104 #if NFWHRNG > 0 105 device_t sc_fwhbus; 106 #endif 107 108 /* Speedstep */ 109 pcireg_t sc_pmcon_orig; 110 111 /* Power management */ 112 pcireg_t sc_pirq[2]; 113 pcireg_t sc_pmcon; 114 pcireg_t sc_fwhsel2; 115 116 /* Child devices */ 117 device_t sc_hpetbus; 118 acpipmtimer_t sc_pmtimer; 119 pcireg_t sc_acpi_cntl; 120 121 struct sysctllog *sc_log; 122 }; 123 124 static int lpcibmatch(device_t, cfdata_t, void *); 125 static void lpcibattach(device_t, device_t, void *); 126 static int lpcibdetach(device_t, int); 127 static void lpcibchilddet(device_t, device_t); 128 static int lpcibrescan(device_t, const char *, const int *); 129 static bool lpcib_suspend(device_t, const pmf_qual_t *); 130 static bool lpcib_resume(device_t, const pmf_qual_t *); 131 static bool lpcib_shutdown(device_t, int); 132 133 static void pmtimer_configure(device_t); 134 static int pmtimer_unconfigure(device_t, int); 135 136 static void tcotimer_configure(device_t); 137 static int tcotimer_unconfigure(device_t, int); 138 static int tcotimer_setmode(struct sysmon_wdog *); 139 static int tcotimer_tickle(struct sysmon_wdog *); 140 static void tcotimer_stop(struct lpcib_softc *); 141 static void tcotimer_start(struct lpcib_softc *); 142 static void tcotimer_status_reset(struct lpcib_softc *); 143 static int tcotimer_disable_noreboot(device_t); 144 145 static void speedstep_configure(device_t); 146 static void speedstep_unconfigure(device_t); 147 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 148 149 static void lpcib_hpet_configure(device_t); 150 static int lpcib_hpet_unconfigure(device_t, int); 151 152 #if NGPIO > 0 153 static void lpcib_gpio_configure(device_t); 154 static int lpcib_gpio_unconfigure(device_t, int); 155 static int lpcib_gpio_pin_read(void *, int); 156 static void lpcib_gpio_pin_write(void *, int, int); 157 static void lpcib_gpio_pin_ctl(void *, int, int); 158 #endif 159 160 #if NFWHRNG > 0 161 static void lpcib_fwh_configure(device_t); 162 static int lpcib_fwh_unconfigure(device_t, int); 163 #endif 164 165 struct lpcib_softc *speedstep_cookie; /* XXX */ 166 167 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 168 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 169 170 static struct lpcib_device { 171 pcireg_t vendor, product; 172 int has_rcba; 173 int has_ich5_hpet; 174 } lpcib_devices[] = { 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z68_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H97_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z97_LPC, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X99_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X99_LPC_2, 1, 0 }, 264 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_LPC, 1, 0 }, 270 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCL_LPC, 1, 0 }, 271 #if 0 272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 273 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 274 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 276 #endif 277 278 { 0, 0, 0, 0 }, 279 }; 280 281 /* 282 * Autoconf callbacks. 283 */ 284 static int 285 lpcibmatch(device_t parent, cfdata_t match, void *aux) 286 { 287 struct pci_attach_args *pa = aux; 288 struct lpcib_device *lpcib_dev; 289 290 /* We are ISA bridge, of course */ 291 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 292 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 293 return 0; 294 295 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 296 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 297 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 298 return 10; 299 } 300 301 return 0; 302 } 303 304 static void 305 lpcibattach(device_t parent, device_t self, void *aux) 306 { 307 struct pci_attach_args *pa = aux; 308 struct lpcib_softc *sc = device_private(self); 309 struct lpcib_device *lpcib_dev; 310 pcireg_t pmbase; 311 312 sc->sc_pa = *pa; 313 314 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 315 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 316 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 317 continue; 318 sc->sc_has_rcba = lpcib_dev->has_rcba; 319 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 320 break; 321 } 322 323 pcibattach(parent, self, aux); 324 325 /* 326 * Part of our I/O registers are used as ACPI PM regs. 327 * Since our ACPI subsystem accesses the I/O space directly so far, 328 * we do not have to bother bus_space I/O map confliction. 329 * 330 * The PMBASE register is alike PCI BAR but not completely compatible 331 * with it. The PMBASE define the base address and the type but 332 * not describe the size. The value of the register may be lower 333 * than LPCIB_PCI_PM_SIZE. It makes impossible to use 334 * pci_mapreg_submap() because the function does range check. 335 */ 336 sc->sc_iot = pa->pa_iot; 337 pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE); 338 if (bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(pmbase), 339 LPCIB_PCI_PM_SIZE, 0, &sc->sc_ioh) != 0) { 340 aprint_error_dev(self, 341 "can't map power management i/o space\n"); 342 return; 343 } 344 345 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 346 LPCIB_PCI_GEN_PMCON_1); 347 348 /* For ICH6 and later, always enable RCBA */ 349 if (sc->sc_has_rcba) { 350 pcireg_t rcba; 351 352 sc->sc_rcbat = sc->sc_pa.pa_memt; 353 354 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 355 LPCIB_RCBA); 356 if ((rcba & LPCIB_RCBA_EN) == 0) { 357 aprint_error_dev(self, "RCBA is not enabled\n"); 358 return; 359 } 360 rcba &= ~LPCIB_RCBA_EN; 361 362 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 363 &sc->sc_rcbah)) { 364 aprint_error_dev(self, "RCBA could not be mapped\n"); 365 return; 366 } 367 } 368 369 /* Set up the power management timer. */ 370 pmtimer_configure(self); 371 372 /* Set up the TCO (watchdog). */ 373 tcotimer_configure(self); 374 375 /* Set up SpeedStep. */ 376 speedstep_configure(self); 377 378 /* Set up HPET. */ 379 lpcib_hpet_configure(self); 380 381 #if NGPIO > 0 382 /* Set up GPIO */ 383 lpcib_gpio_configure(self); 384 #endif 385 386 #if NFWHRNG > 0 387 lpcib_fwh_configure(self); 388 #endif 389 390 /* Install power handler */ 391 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 392 lpcib_shutdown)) 393 aprint_error_dev(self, "couldn't establish power handler\n"); 394 } 395 396 static void 397 lpcibchilddet(device_t self, device_t child) 398 { 399 struct lpcib_softc *sc = device_private(self); 400 uint32_t val; 401 402 #if NFWHRNG > 0 403 if (sc->sc_fwhbus == child) { 404 sc->sc_fwhbus = NULL; 405 return; 406 } 407 #endif 408 #if NGPIO > 0 409 if (sc->sc_gpiobus == child) { 410 sc->sc_gpiobus = NULL; 411 return; 412 } 413 #endif 414 if (sc->sc_hpetbus != child) { 415 pcibchilddet(self, child); 416 return; 417 } 418 sc->sc_hpetbus = NULL; 419 if (sc->sc_has_ich5_hpet) { 420 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 421 LPCIB_PCI_GEN_CNTL); 422 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 423 case LPCIB_ICH5_HPTC_0000: 424 case LPCIB_ICH5_HPTC_1000: 425 case LPCIB_ICH5_HPTC_2000: 426 case LPCIB_ICH5_HPTC_3000: 427 break; 428 default: 429 return; 430 } 431 val &= ~LPCIB_ICH5_HPTC_EN; 432 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 433 LPCIB_PCI_GEN_CNTL, val); 434 } else if (sc->sc_has_rcba) { 435 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 436 LPCIB_RCBA_HPTC); 437 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 438 case LPCIB_RCBA_HPTC_0000: 439 case LPCIB_RCBA_HPTC_1000: 440 case LPCIB_RCBA_HPTC_2000: 441 case LPCIB_RCBA_HPTC_3000: 442 break; 443 default: 444 return; 445 } 446 val &= ~LPCIB_RCBA_HPTC_EN; 447 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 448 val); 449 } 450 } 451 452 static int 453 lpcibrescan(device_t self, const char *ifattr, const int *locators) 454 { 455 struct lpcib_softc *sc = device_private(self); 456 457 #if NFWHRNG > 0 458 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 459 lpcib_fwh_configure(self); 460 #endif 461 462 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 463 lpcib_hpet_configure(self); 464 465 #if NGPIO > 0 466 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 467 lpcib_gpio_configure(self); 468 #endif 469 470 return pcibrescan(self, ifattr, locators); 471 } 472 473 static int 474 lpcibdetach(device_t self, int flags) 475 { 476 struct lpcib_softc *sc = device_private(self); 477 int rc; 478 479 pmf_device_deregister(self); 480 481 #if NFWHRNG > 0 482 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 483 return rc; 484 #endif 485 486 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 487 return rc; 488 489 #if NGPIO > 0 490 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 491 return rc; 492 #endif 493 494 /* Set up SpeedStep. */ 495 speedstep_unconfigure(self); 496 497 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 498 return rc; 499 500 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 501 return rc; 502 503 if (sc->sc_has_rcba) 504 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 505 506 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 507 508 return pcibdetach(self, flags); 509 } 510 511 static bool 512 lpcib_shutdown(device_t dv, int howto) 513 { 514 struct lpcib_softc *sc = device_private(dv); 515 516 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 517 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 518 519 return true; 520 } 521 522 static bool 523 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 524 { 525 struct lpcib_softc *sc = device_private(dv); 526 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 527 pcitag_t tag = sc->sc_pcib.sc_tag; 528 529 /* capture PIRQ routing control registers */ 530 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 531 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 532 533 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 534 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 535 536 if (sc->sc_has_rcba) { 537 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 538 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 539 LPCIB_RCBA_HPTC); 540 } else if (sc->sc_has_ich5_hpet) { 541 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 542 } 543 544 return true; 545 } 546 547 static bool 548 lpcib_resume(device_t dv, const pmf_qual_t *qual) 549 { 550 struct lpcib_softc *sc = device_private(dv); 551 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 552 pcitag_t tag = sc->sc_pcib.sc_tag; 553 554 /* restore PIRQ routing control registers */ 555 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 556 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 557 558 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 559 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 560 561 if (sc->sc_has_rcba) { 562 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 563 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 564 sc->sc_hpet_reg); 565 } else if (sc->sc_has_ich5_hpet) { 566 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 567 } 568 569 return true; 570 } 571 572 /* 573 * Initialize the power management timer. 574 */ 575 static void 576 pmtimer_configure(device_t self) 577 { 578 struct lpcib_softc *sc = device_private(self); 579 pcireg_t control; 580 581 /* 582 * Check if power management I/O space is enabled and enable the ACPI_EN 583 * bit if it's disabled. 584 */ 585 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 586 LPCIB_PCI_ACPI_CNTL); 587 sc->sc_acpi_cntl = control; 588 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 589 control |= LPCIB_PCI_ACPI_CNTL_EN; 590 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 591 LPCIB_PCI_ACPI_CNTL, control); 592 } 593 594 /* Attach our PM timer with the generic acpipmtimer function */ 595 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, 596 LPCIB_PM1_TMR, 0); 597 } 598 599 static int 600 pmtimer_unconfigure(device_t self, int flags) 601 { 602 struct lpcib_softc *sc = device_private(self); 603 int rc; 604 605 if (sc->sc_pmtimer != NULL && 606 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 607 return rc; 608 609 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 610 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 611 612 return 0; 613 } 614 615 /* 616 * Initialize the watchdog timer. 617 */ 618 static void 619 tcotimer_configure(device_t self) 620 { 621 struct lpcib_softc *sc = device_private(self); 622 uint32_t ioreg; 623 unsigned int period; 624 625 /* Explicitly stop the TCO timer. */ 626 tcotimer_stop(sc); 627 628 /* 629 * Enable TCO timeout SMI only if the hardware reset does not 630 * work. We don't know what the SMBIOS does. 631 */ 632 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 633 ioreg &= ~LPCIB_SMI_EN_TCO_EN; 634 635 /* 636 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 637 * in the SMI_EN register is the last chance. 638 */ 639 if (tcotimer_disable_noreboot(self)) { 640 ioreg |= LPCIB_SMI_EN_TCO_EN; 641 } 642 if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { 643 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 644 } 645 646 /* Reset the watchdog status registers. */ 647 tcotimer_status_reset(sc); 648 649 /* 650 * Register the driver with the sysmon watchdog framework. 651 */ 652 sc->sc_smw.smw_name = device_xname(self); 653 sc->sc_smw.smw_cookie = sc; 654 sc->sc_smw.smw_setmode = tcotimer_setmode; 655 sc->sc_smw.smw_tickle = tcotimer_tickle; 656 if (sc->sc_has_rcba) 657 period = LPCIB_TCOTIMER2_MAX_TICK; 658 else 659 period = LPCIB_TCOTIMER_MAX_TICK; 660 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 661 662 if (sysmon_wdog_register(&sc->sc_smw)) { 663 aprint_error_dev(self, "unable to register TCO timer" 664 "as a sysmon watchdog device.\n"); 665 return; 666 } 667 668 aprint_verbose_dev(self, "TCO (watchdog) timer configured.\n"); 669 } 670 671 static int 672 tcotimer_unconfigure(device_t self, int flags) 673 { 674 struct lpcib_softc *sc = device_private(self); 675 int rc; 676 677 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 678 if (rc == ERESTART) 679 rc = EINTR; 680 return rc; 681 } 682 683 /* Explicitly stop the TCO timer. */ 684 tcotimer_stop(sc); 685 686 /* XXX Set No Reboot? */ 687 688 return 0; 689 } 690 691 692 /* 693 * Sysmon watchdog callbacks. 694 */ 695 static int 696 tcotimer_setmode(struct sysmon_wdog *smw) 697 { 698 struct lpcib_softc *sc = smw->smw_cookie; 699 unsigned int period; 700 uint16_t ich6period = 0; 701 uint8_t ich5period = 0; 702 703 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 704 /* Stop the TCO timer. */ 705 tcotimer_stop(sc); 706 } else { 707 /* 708 * ICH6 or newer are limited to 2s min and 613s max. 709 * ICH5 or older are limited to 4s min and 39s max. 710 */ 711 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 712 if (sc->sc_has_rcba) { 713 if (period < LPCIB_TCOTIMER2_MIN_TICK || 714 period > LPCIB_TCOTIMER2_MAX_TICK) 715 return EINVAL; 716 } else { 717 if (period < LPCIB_TCOTIMER_MIN_TICK || 718 period > LPCIB_TCOTIMER_MAX_TICK) 719 return EINVAL; 720 } 721 722 /* Stop the TCO timer, */ 723 tcotimer_stop(sc); 724 725 /* set the timeout, */ 726 if (sc->sc_has_rcba) { 727 /* ICH6 or newer */ 728 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 729 LPCIB_TCO_TMR2); 730 ich6period &= 0xfc00; 731 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 732 LPCIB_TCO_TMR2, ich6period | period); 733 } else { 734 /* ICH5 or older */ 735 ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 736 LPCIB_TCO_TMR); 737 ich5period &= 0xc0; 738 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 739 LPCIB_TCO_TMR, ich5period | period); 740 } 741 742 /* and start/reload the timer. */ 743 tcotimer_start(sc); 744 tcotimer_tickle(smw); 745 } 746 747 return 0; 748 } 749 750 static int 751 tcotimer_tickle(struct sysmon_wdog *smw) 752 { 753 struct lpcib_softc *sc = smw->smw_cookie; 754 755 /* any value is allowed */ 756 if (sc->sc_has_rcba) 757 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 758 else 759 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 760 761 return 0; 762 } 763 764 static void 765 tcotimer_stop(struct lpcib_softc *sc) 766 { 767 uint16_t ioreg; 768 769 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 770 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 771 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 772 } 773 774 static void 775 tcotimer_start(struct lpcib_softc *sc) 776 { 777 uint16_t ioreg; 778 779 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 780 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 781 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 782 } 783 784 static void 785 tcotimer_status_reset(struct lpcib_softc *sc) 786 { 787 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 788 LPCIB_TCO1_STS_TIMEOUT); 789 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 790 LPCIB_TCO2_STS_BOOT_STS); 791 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 792 LPCIB_TCO2_STS_SECONDS_TO_STS); 793 } 794 795 /* 796 * Clear the No Reboot (NR) bit, this enables reboots when the timer 797 * reaches the timeout for the second time. 798 */ 799 static int 800 tcotimer_disable_noreboot(device_t self) 801 { 802 struct lpcib_softc *sc = device_private(self); 803 804 if (sc->sc_has_rcba) { 805 uint32_t status; 806 807 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 808 LPCIB_GCS_OFFSET); 809 status &= ~LPCIB_GCS_NO_REBOOT; 810 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, 811 LPCIB_GCS_OFFSET, status); 812 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 813 LPCIB_GCS_OFFSET); 814 if (status & LPCIB_GCS_NO_REBOOT) 815 goto error; 816 } else { 817 pcireg_t pcireg; 818 819 pcireg = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 820 LPCIB_PCI_GEN_STA); 821 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 822 /* TCO timeout reset is disabled; try to enable it */ 823 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 824 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 825 LPCIB_PCI_GEN_STA, pcireg); 826 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 827 goto error; 828 } 829 } 830 831 return 0; 832 error: 833 aprint_error_dev(self, "TCO timer reboot disabled by hardware; " 834 "hope SMBIOS properly handles it.\n"); 835 return EINVAL; 836 } 837 838 839 /* 840 * Intel ICH SpeedStep support. 841 */ 842 #define SS_READ(sc, reg) \ 843 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 844 #define SS_WRITE(sc, reg, val) \ 845 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 846 847 /* 848 * Linux driver says that SpeedStep on older chipsets cause 849 * lockups on Dell Inspiron 8000 and 8100. 850 * It should also not be enabled on systems with the 82855GM 851 * Hub, which typically have an EST-enabled CPU. 852 */ 853 static int 854 speedstep_bad_hb_check(const struct pci_attach_args *pa) 855 { 856 857 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 858 PCI_REVISION(pa->pa_class) < 5) 859 return 1; 860 861 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 862 return 1; 863 864 return 0; 865 } 866 867 static void 868 speedstep_configure(device_t self) 869 { 870 struct lpcib_softc *sc = device_private(self); 871 const struct sysctlnode *node, *ssnode; 872 int rv; 873 874 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 875 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 876 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 877 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 878 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 879 pcireg_t pmcon; 880 881 /* Enable SpeedStep if it isn't already enabled. */ 882 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 883 LPCIB_PCI_GEN_PMCON_1); 884 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 885 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 886 LPCIB_PCI_GEN_PMCON_1, 887 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 888 889 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 890 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 891 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 892 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 893 goto err; 894 895 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 896 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 897 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 898 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 899 CTL_EOL)) != 0) 900 goto err; 901 902 /* XXX save the sc for IO tag/handle */ 903 speedstep_cookie = sc; 904 aprint_verbose_dev(self, "SpeedStep enabled\n"); 905 } 906 907 return; 908 909 err: 910 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 911 } 912 913 static void 914 speedstep_unconfigure(device_t self) 915 { 916 struct lpcib_softc *sc = device_private(self); 917 918 sysctl_teardown(&sc->sc_log); 919 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 920 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 921 922 speedstep_cookie = NULL; 923 } 924 925 /* 926 * get/set the SpeedStep state: 0 == low power, 1 == high power. 927 */ 928 static int 929 speedstep_sysctl_helper(SYSCTLFN_ARGS) 930 { 931 struct sysctlnode node; 932 struct lpcib_softc *sc = speedstep_cookie; 933 uint8_t state, state2; 934 int ostate, nstate, s, error = 0; 935 936 /* 937 * We do the dance with spl's to avoid being at high ipl during 938 * sysctl_lookup() which can both copyin and copyout. 939 */ 940 s = splserial(); 941 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 942 splx(s); 943 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 944 ostate = 1; 945 else 946 ostate = 0; 947 nstate = ostate; 948 949 node = *rnode; 950 node.sysctl_data = &nstate; 951 952 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 953 if (error || newp == NULL) 954 goto out; 955 956 /* Only two states are available */ 957 if (nstate != 0 && nstate != 1) { 958 error = EINVAL; 959 goto out; 960 } 961 962 s = splserial(); 963 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 964 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 965 ostate = 1; 966 else 967 ostate = 0; 968 969 if (ostate != nstate) { 970 uint8_t cntl; 971 972 if (nstate == 0) 973 state2 |= LPCIB_PM_SS_STATE_LOW; 974 else 975 state2 &= ~LPCIB_PM_SS_STATE_LOW; 976 977 /* 978 * Must disable bus master arbitration during the change. 979 */ 980 cntl = SS_READ(sc, LPCIB_PM_CTRL); 981 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 982 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 983 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 984 } 985 splx(s); 986 out: 987 return error; 988 } 989 990 static void 991 lpcib_hpet_configure(device_t self) 992 { 993 struct lpcib_softc *sc = device_private(self); 994 struct lpcib_hpet_attach_args arg; 995 uint32_t hpet_reg, val; 996 997 if (sc->sc_has_ich5_hpet) { 998 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 999 LPCIB_PCI_GEN_CNTL); 1000 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 1001 case LPCIB_ICH5_HPTC_0000: 1002 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 1003 break; 1004 case LPCIB_ICH5_HPTC_1000: 1005 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 1006 break; 1007 case LPCIB_ICH5_HPTC_2000: 1008 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 1009 break; 1010 case LPCIB_ICH5_HPTC_3000: 1011 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 1012 break; 1013 default: 1014 return; 1015 } 1016 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 1017 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1018 LPCIB_PCI_GEN_CNTL, val); 1019 } else if (sc->sc_has_rcba) { 1020 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 1021 LPCIB_RCBA_HPTC); 1022 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 1023 case LPCIB_RCBA_HPTC_0000: 1024 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 1025 break; 1026 case LPCIB_RCBA_HPTC_1000: 1027 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 1028 break; 1029 case LPCIB_RCBA_HPTC_2000: 1030 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 1031 break; 1032 case LPCIB_RCBA_HPTC_3000: 1033 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 1034 break; 1035 default: 1036 return; 1037 } 1038 val |= LPCIB_RCBA_HPTC_EN; 1039 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 1040 val); 1041 } else { 1042 /* No HPET here */ 1043 return; 1044 } 1045 1046 arg.hpet_mem_t = sc->sc_pa.pa_memt; 1047 arg.hpet_reg = hpet_reg; 1048 1049 sc->sc_hpetbus = config_found_ia(self, "hpetichbus", &arg, NULL); 1050 } 1051 1052 static int 1053 lpcib_hpet_unconfigure(device_t self, int flags) 1054 { 1055 struct lpcib_softc *sc = device_private(self); 1056 int rc; 1057 1058 if (sc->sc_hpetbus != NULL && 1059 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 1060 return rc; 1061 1062 return 0; 1063 } 1064 1065 #if NGPIO > 0 1066 static void 1067 lpcib_gpio_configure(device_t self) 1068 { 1069 struct lpcib_softc *sc = device_private(self); 1070 struct gpiobus_attach_args gba; 1071 pcireg_t gpio_cntl; 1072 uint32_t use, io, bit; 1073 int pin, shift, base_reg, cntl_reg, reg; 1074 int rv; 1075 1076 /* this implies ICH >= 6, and thus different mapreg */ 1077 if (sc->sc_has_rcba) { 1078 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 1079 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 1080 } else { 1081 base_reg = LPCIB_PCI_GPIO_BASE; 1082 cntl_reg = LPCIB_PCI_GPIO_CNTL; 1083 } 1084 1085 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1086 cntl_reg); 1087 1088 /* Is GPIO enabled? */ 1089 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 1090 return; 1091 /* 1092 * The GPIO_BASE register is alike PCI BAR but not completely 1093 * compatible with it. The PMBASE define the base address and the type 1094 * but not describe the size. The value of the register may be lower 1095 * than LPCIB_PCI_GPIO_SIZE. It makes impossible to use 1096 * pci_mapreg_submap() because the function does range check. 1097 */ 1098 sc->sc_gpio_iot = sc->sc_pa.pa_iot; 1099 reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg); 1100 rv = bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(reg), 1101 LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_ioh); 1102 if (rv != 0) { 1103 aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv); 1104 return; 1105 } 1106 1107 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 1108 1109 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 1110 sc->sc_gpio_pins[pin].pin_num = pin; 1111 1112 /* Read initial state */ 1113 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 1114 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1115 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 1116 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 1117 shift = pin % 32; 1118 bit = __BIT(shift); 1119 1120 if ((use & bit) != 0) { 1121 sc->sc_gpio_pins[pin].pin_caps = 1122 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 1123 if (pin < 32) 1124 sc->sc_gpio_pins[pin].pin_caps |= 1125 GPIO_PIN_PULSATE; 1126 if ((io & bit) != 0) 1127 sc->sc_gpio_pins[pin].pin_flags = 1128 GPIO_PIN_INPUT; 1129 else 1130 sc->sc_gpio_pins[pin].pin_flags = 1131 GPIO_PIN_OUTPUT; 1132 } else 1133 sc->sc_gpio_pins[pin].pin_caps = 0; 1134 1135 if (lpcib_gpio_pin_read(sc, pin) == 0) 1136 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1137 else 1138 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1139 1140 } 1141 1142 /* Create controller tag */ 1143 sc->sc_gpio_gc.gp_cookie = sc; 1144 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 1145 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 1146 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 1147 1148 memset(&gba, 0, sizeof(gba)); 1149 1150 gba.gba_gc = &sc->sc_gpio_gc; 1151 gba.gba_pins = sc->sc_gpio_pins; 1152 gba.gba_npins = LPCIB_GPIO_NPINS; 1153 1154 sc->sc_gpiobus = config_found_ia(self, "gpiobus", &gba, gpiobus_print); 1155 } 1156 1157 static int 1158 lpcib_gpio_unconfigure(device_t self, int flags) 1159 { 1160 struct lpcib_softc *sc = device_private(self); 1161 int rc; 1162 1163 if (sc->sc_gpiobus != NULL && 1164 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1165 return rc; 1166 1167 mutex_destroy(&sc->sc_gpio_mtx); 1168 1169 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1170 1171 return 0; 1172 } 1173 1174 static int 1175 lpcib_gpio_pin_read(void *arg, int pin) 1176 { 1177 struct lpcib_softc *sc = arg; 1178 uint32_t data; 1179 int reg, shift; 1180 1181 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1182 shift = pin % 32; 1183 1184 mutex_enter(&sc->sc_gpio_mtx); 1185 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1186 mutex_exit(&sc->sc_gpio_mtx); 1187 1188 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1189 } 1190 1191 static void 1192 lpcib_gpio_pin_write(void *arg, int pin, int value) 1193 { 1194 struct lpcib_softc *sc = arg; 1195 uint32_t data; 1196 int reg, shift; 1197 1198 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1199 shift = pin % 32; 1200 1201 mutex_enter(&sc->sc_gpio_mtx); 1202 1203 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1204 1205 if(value) 1206 data |= __BIT(shift); 1207 else 1208 data &= ~__BIT(shift); 1209 1210 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1211 1212 mutex_exit(&sc->sc_gpio_mtx); 1213 } 1214 1215 static void 1216 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1217 { 1218 struct lpcib_softc *sc = arg; 1219 uint32_t data; 1220 int reg, shift; 1221 1222 shift = pin % 32; 1223 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1224 1225 mutex_enter(&sc->sc_gpio_mtx); 1226 1227 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1228 1229 if (flags & GPIO_PIN_OUTPUT) 1230 data &= ~__BIT(shift); 1231 1232 if (flags & GPIO_PIN_INPUT) 1233 data |= __BIT(shift); 1234 1235 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1236 1237 1238 if (pin < 32) { 1239 reg = LPCIB_GPIO_GPO_BLINK; 1240 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1241 1242 if (flags & GPIO_PIN_PULSATE) 1243 data |= __BIT(shift); 1244 else 1245 data &= ~__BIT(shift); 1246 1247 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1248 } 1249 1250 mutex_exit(&sc->sc_gpio_mtx); 1251 } 1252 #endif 1253 1254 #if NFWHRNG > 0 1255 static void 1256 lpcib_fwh_configure(device_t self) 1257 { 1258 struct lpcib_softc *sc; 1259 pcireg_t pr; 1260 1261 sc = device_private(self); 1262 1263 if (sc->sc_has_rcba) { 1264 /* 1265 * Very unlikely to find a 82802 on a ICH6 or newer. 1266 * Also the write enable register moved at that point. 1267 */ 1268 return; 1269 } else { 1270 /* Enable FWH write to identify FWH. */ 1271 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1272 LPCIB_PCI_BIOS_CNTL); 1273 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1274 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1275 } 1276 1277 sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); 1278 1279 /* restore previous write enable setting */ 1280 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1281 LPCIB_PCI_BIOS_CNTL, pr); 1282 } 1283 1284 static int 1285 lpcib_fwh_unconfigure(device_t self, int flags) 1286 { 1287 struct lpcib_softc *sc = device_private(self); 1288 int rc; 1289 1290 if (sc->sc_fwhbus != NULL && 1291 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1292 return rc; 1293 1294 return 0; 1295 } 1296 #endif 1297
Indexes created Tue Sep 30 11:09:46 GMT 2025