ichlpcib.c revision 1.6
1 /* $NetBSD: ichlpcib.c,v 1.6 2007/12/09 20:27:49 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 41 * 42 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 43 * some power management and monitoring functions. 44 * Currently we support the watchdog timer, SpeedStep (on some systems) 45 * and the power management timer. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.6 2007/12/09 20:27:49 jmcneill Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/sysctl.h> 56 #include <sys/timetc.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/sysmon/sysmonvar.h> 64 65 #include <dev/ic/acpipmtimer.h> 66 #include <dev/ic/i82801lpcreg.h> 67 #include <dev/ic/hpetreg.h> 68 #include <dev/ic/hpetvar.h> 69 70 #include "hpet.h" 71 72 struct lpcib_softc { 73 /* Device object. */ 74 struct device sc_dev; 75 76 pci_chipset_tag_t sc_pc; 77 pcitag_t sc_pcitag; 78 79 struct pci_attach_args sc_pa; 80 int sc_has_rcba; 81 int sc_has_ich5_hpet; 82 83 /* RCBA */ 84 bus_space_tag_t sc_rcbat; 85 bus_space_handle_t sc_rcbah; 86 pcireg_t sc_rcba_reg; 87 88 /* Watchdog variables. */ 89 struct sysmon_wdog sc_smw; 90 bus_space_tag_t sc_iot; 91 bus_space_handle_t sc_ioh; 92 93 #if NHPET > 0 94 /* HPET variables. */ 95 uint32_t sc_hpet_reg; 96 #endif 97 98 /* Power management */ 99 pcireg_t sc_pirq[8]; 100 pcireg_t sc_pmcon; 101 pcireg_t sc_fwhsel2; 102 }; 103 104 static int lpcibmatch(struct device *, struct cfdata *, void *); 105 static void lpcibattach(struct device *, struct device *, void *); 106 static bool lpcib_suspend(device_t); 107 static bool lpcib_resume(device_t); 108 109 static void pmtimer_configure(struct lpcib_softc *); 110 111 static void tcotimer_configure(struct lpcib_softc *); 112 static int tcotimer_setmode(struct sysmon_wdog *); 113 static int tcotimer_tickle(struct sysmon_wdog *); 114 static void tcotimer_stop(struct lpcib_softc *); 115 static void tcotimer_start(struct lpcib_softc *); 116 static void tcotimer_status_reset(struct lpcib_softc *); 117 static int tcotimer_disable_noreboot(struct lpcib_softc *); 118 119 static void speedstep_configure(struct lpcib_softc *); 120 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 121 122 #if NHPET > 0 123 static void lpcib_hpet_configure(struct lpcib_softc *); 124 #endif 125 126 struct lpcib_softc *speedstep_cookie; /* XXX */ 127 128 /* Defined in arch/.../pci/pcib.c. */ 129 extern void pcibattach(struct device *, struct device *, void *); 130 131 CFATTACH_DECL(ichlpcib, sizeof(struct lpcib_softc), 132 lpcibmatch, lpcibattach, NULL, NULL); 133 134 static struct lpcib_device { 135 pcireg_t vendor, product; 136 int has_rcba; 137 int has_ich5_hpet; 138 } lpcib_devices[] = { 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 161 { 0, 0, 0, 0 }, 162 }; 163 164 /* 165 * Autoconf callbacks. 166 */ 167 static int 168 lpcibmatch(struct device *parent, struct cfdata *match, void *aux) 169 { 170 struct pci_attach_args *pa = aux; 171 struct lpcib_device *lpcib_dev; 172 173 /* We are ISA bridge, of course */ 174 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 175 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 176 return 0; 177 178 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 179 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 180 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 181 return 10; 182 } 183 184 return 0; 185 } 186 187 static void 188 lpcibattach(struct device *parent, struct device *self, void *aux) 189 { 190 struct pci_attach_args *pa = aux; 191 struct lpcib_softc *sc = device_private(self); 192 struct lpcib_device *lpcib_dev; 193 194 sc->sc_pc = pa->pa_pc; 195 sc->sc_pcitag = pa->pa_tag; 196 sc->sc_pa = *pa; 197 198 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 199 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 200 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 201 continue; 202 sc->sc_has_rcba = lpcib_dev->has_rcba; 203 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 204 break; 205 } 206 207 pcibattach(parent, self, aux); 208 209 /* 210 * Part of our I/O registers are used as ACPI PM regs. 211 * Since our ACPI subsystem accesses the I/O space directly so far, 212 * we do not have to bother bus_space I/O map confliction. 213 */ 214 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 215 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 216 aprint_error("%s: can't map power management i/o space", 217 sc->sc_dev.dv_xname); 218 return; 219 } 220 221 /* For ICH6 and later, always enable RCBA */ 222 if (sc->sc_has_rcba) { 223 pcireg_t rcba; 224 225 sc->sc_rcbat = sc->sc_pa.pa_memt; 226 227 rcba = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_RCBA); 228 if ((rcba & LPCIB_RCBA_EN) == 0) { 229 aprint_error("%s: RCBA is not enabled", 230 sc->sc_dev.dv_xname); 231 return; 232 } 233 rcba &= ~LPCIB_RCBA_EN; 234 235 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 236 &sc->sc_rcbah)) { 237 aprint_error("%s: RCBA could not be mapped", 238 sc->sc_dev.dv_xname); 239 return; 240 } 241 } 242 243 /* Set up the power management timer. */ 244 pmtimer_configure(sc); 245 246 /* Set up the TCO (watchdog). */ 247 tcotimer_configure(sc); 248 249 /* Set up SpeedStep. */ 250 speedstep_configure(sc); 251 252 #if NHPET > 0 253 /* Set up HPET. */ 254 lpcib_hpet_configure(sc); 255 #endif 256 257 /* Install power handler */ 258 if (!pmf_device_register(self, lpcib_suspend, lpcib_resume)) 259 aprint_error_dev(self, "couldn't establish power handler\n"); 260 } 261 262 static bool 263 lpcib_suspend(device_t dv) 264 { 265 struct lpcib_softc *sc = device_private(dv); 266 pci_chipset_tag_t pc = sc->sc_pc; 267 pcitag_t tag = sc->sc_pcitag; 268 269 /* capture PIRQ routing control registers */ 270 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 271 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQB_ROUT); 272 sc->sc_pirq[2] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQC_ROUT); 273 sc->sc_pirq[3] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQD_ROUT); 274 sc->sc_pirq[4] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 275 sc->sc_pirq[5] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQF_ROUT); 276 sc->sc_pirq[6] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQG_ROUT); 277 sc->sc_pirq[7] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQH_ROUT); 278 279 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 280 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 281 282 if (sc->sc_has_rcba) { 283 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 284 #if NHPET > 0 285 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 286 LPCIB_RCBA_HPTC); 287 #endif 288 } else if (sc->sc_has_ich5_hpet) { 289 #if NHPET > 0 290 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 291 #endif 292 } 293 294 return true; 295 } 296 297 static bool 298 lpcib_resume(device_t dv) 299 { 300 struct lpcib_softc *sc = device_private(dv); 301 pci_chipset_tag_t pc = sc->sc_pc; 302 pcitag_t tag = sc->sc_pcitag; 303 304 /* restore PIRQ routing control registers */ 305 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 306 pci_conf_write(pc, tag, LPCIB_PCI_PIRQB_ROUT, sc->sc_pirq[1]); 307 pci_conf_write(pc, tag, LPCIB_PCI_PIRQC_ROUT, sc->sc_pirq[2]); 308 pci_conf_write(pc, tag, LPCIB_PCI_PIRQD_ROUT, sc->sc_pirq[3]); 309 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[4]); 310 pci_conf_write(pc, tag, LPCIB_PCI_PIRQF_ROUT, sc->sc_pirq[5]); 311 pci_conf_write(pc, tag, LPCIB_PCI_PIRQG_ROUT, sc->sc_pirq[6]); 312 pci_conf_write(pc, tag, LPCIB_PCI_PIRQH_ROUT, sc->sc_pirq[7]); 313 314 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 315 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 316 317 if (sc->sc_has_rcba) { 318 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 319 #if NHPET > 0 320 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 321 sc->sc_hpet_reg); 322 #endif 323 } else if (sc->sc_has_ich5_hpet) { 324 #if NHPET > 0 325 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 326 #endif 327 } 328 329 return true; 330 } 331 332 /* 333 * Initialize the power management timer. 334 */ 335 static void 336 pmtimer_configure(struct lpcib_softc *sc) 337 { 338 pcireg_t control; 339 340 /* 341 * Check if power management I/O space is enabled and enable the ACPI_EN 342 * bit if it's disabled. 343 */ 344 control = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL); 345 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 346 control |= LPCIB_PCI_ACPI_CNTL_EN; 347 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL, 348 control); 349 } 350 351 /* Attach our PM timer with the generic acpipmtimer function */ 352 acpipmtimer_attach(&sc->sc_dev, sc->sc_iot, sc->sc_ioh, 353 LPCIB_PM1_TMR, 0); 354 } 355 356 /* 357 * Initialize the watchdog timer. 358 */ 359 static void 360 tcotimer_configure(struct lpcib_softc *sc) 361 { 362 uint32_t ioreg; 363 unsigned int period; 364 365 /* 366 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 367 * in the SMI_EN register is the last chance. 368 */ 369 if (tcotimer_disable_noreboot(sc)) { 370 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 371 ioreg |= LPCIB_SMI_EN_TCO_EN; 372 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 373 } 374 375 /* Reset the watchdog status registers. */ 376 tcotimer_status_reset(sc); 377 378 /* Explicitly stop the TCO timer. */ 379 tcotimer_stop(sc); 380 381 /* 382 * Register the driver with the sysmon watchdog framework. 383 */ 384 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 385 sc->sc_smw.smw_cookie = sc; 386 sc->sc_smw.smw_setmode = tcotimer_setmode; 387 sc->sc_smw.smw_tickle = tcotimer_tickle; 388 if (sc->sc_has_rcba) 389 period = LPCIB_TCOTIMER2_MAX_TICK; 390 else 391 period = LPCIB_TCOTIMER_MAX_TICK; 392 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 393 394 if (sysmon_wdog_register(&sc->sc_smw)) { 395 aprint_error("%s: unable to register TCO timer" 396 "as a sysmon watchdog device.\n", 397 sc->sc_dev.dv_xname); 398 return; 399 } 400 401 aprint_verbose("%s: TCO (watchdog) timer configured.\n", 402 sc->sc_dev.dv_xname); 403 } 404 405 /* 406 * Sysmon watchdog callbacks. 407 */ 408 static int 409 tcotimer_setmode(struct sysmon_wdog *smw) 410 { 411 struct lpcib_softc *sc = smw->smw_cookie; 412 unsigned int period; 413 uint16_t ich6period = 0; 414 415 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 416 /* Stop the TCO timer. */ 417 tcotimer_stop(sc); 418 } else { 419 /* 420 * ICH6 or newer are limited to 2s min and 613s max. 421 * ICH5 or older are limited to 4s min and 39s max. 422 */ 423 if (sc->sc_has_rcba) { 424 if (smw->smw_period < LPCIB_TCOTIMER2_MIN_TICK || 425 smw->smw_period > LPCIB_TCOTIMER2_MAX_TICK) 426 return EINVAL; 427 } else { 428 if (smw->smw_period < LPCIB_TCOTIMER_MIN_TICK || 429 smw->smw_period > LPCIB_TCOTIMER_MAX_TICK) 430 return EINVAL; 431 } 432 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 433 434 /* Stop the TCO timer, */ 435 tcotimer_stop(sc); 436 437 /* set the timeout, */ 438 if (sc->sc_has_rcba) { 439 /* ICH6 or newer */ 440 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 441 LPCIB_TCO_TMR2); 442 ich6period &= 0xfc00; 443 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 444 LPCIB_TCO_TMR2, ich6period | period); 445 } else { 446 /* ICH5 or older */ 447 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 448 LPCIB_TCO_TMR); 449 period &= 0xc0; 450 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 451 LPCIB_TCO_TMR, period); 452 } 453 454 /* and start/reload the timer. */ 455 tcotimer_start(sc); 456 tcotimer_tickle(smw); 457 } 458 459 return 0; 460 } 461 462 static int 463 tcotimer_tickle(struct sysmon_wdog *smw) 464 { 465 struct lpcib_softc *sc = smw->smw_cookie; 466 467 /* any value is allowed */ 468 if (sc->sc_has_rcba) 469 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 470 else 471 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 472 473 return 0; 474 } 475 476 static void 477 tcotimer_stop(struct lpcib_softc *sc) 478 { 479 uint16_t ioreg; 480 481 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 482 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 483 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 484 } 485 486 static void 487 tcotimer_start(struct lpcib_softc *sc) 488 { 489 uint16_t ioreg; 490 491 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 492 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 493 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 494 } 495 496 static void 497 tcotimer_status_reset(struct lpcib_softc *sc) 498 { 499 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 500 LPCIB_TCO1_STS_TIMEOUT); 501 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 502 LPCIB_TCO2_STS_BOOT_STS); 503 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 504 LPCIB_TCO2_STS_SECONDS_TO_STS); 505 } 506 507 /* 508 * Clear the No Reboot (NR) bit, this enables reboots when the timer 509 * reaches the timeout for the second time. 510 */ 511 static int 512 tcotimer_disable_noreboot(struct lpcib_softc *sc) 513 { 514 515 if (sc->sc_has_rcba) { 516 uint32_t status; 517 518 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET); 519 status &= ~LPCIB_GCS_NO_REBOOT; 520 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET, status); 521 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET); 522 if (status & LPCIB_GCS_NO_REBOOT) 523 goto error; 524 } else { 525 pcireg_t pcireg; 526 527 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 528 LPCIB_PCI_GEN_STA); 529 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 530 /* TCO timeout reset is disabled; try to enable it */ 531 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 532 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 533 LPCIB_PCI_GEN_STA, pcireg); 534 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 535 goto error; 536 } 537 } 538 539 return 0; 540 error: 541 aprint_error("%s: TCO timer reboot disabled by hardware; " 542 "hope SMBIOS properly handles it.\n", sc->sc_dev.dv_xname); 543 return EINVAL; 544 } 545 546 547 /* 548 * Intel ICH SpeedStep support. 549 */ 550 #define SS_READ(sc, reg) \ 551 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 552 #define SS_WRITE(sc, reg, val) \ 553 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 554 555 /* 556 * Linux driver says that SpeedStep on older chipsets cause 557 * lockups on Dell Inspiron 8000 and 8100. 558 */ 559 static int 560 speedstep_bad_hb_check(struct pci_attach_args *pa) 561 { 562 563 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 564 PCI_REVISION(pa->pa_class) < 5) 565 return 1; 566 567 return 0; 568 } 569 570 static void 571 speedstep_configure(struct lpcib_softc *sc) 572 { 573 const struct sysctlnode *node, *ssnode; 574 int rv; 575 576 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 577 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 578 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 579 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 580 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 581 uint8_t pmcon; 582 583 /* Enable SpeedStep if it isn't already enabled. */ 584 pmcon = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 585 LPCIB_PCI_GEN_PMCON_1); 586 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 587 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 588 LPCIB_PCI_GEN_PMCON_1, 589 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 590 591 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 592 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 593 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 594 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 595 goto err; 596 597 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 598 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 599 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 600 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 601 CTL_EOL)) != 0) 602 goto err; 603 604 /* XXX save the sc for IO tag/handle */ 605 speedstep_cookie = sc; 606 aprint_verbose("%s: SpeedStep enabled\n", sc->sc_dev.dv_xname); 607 } 608 609 return; 610 611 err: 612 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 613 } 614 615 /* 616 * get/set the SpeedStep state: 0 == low power, 1 == high power. 617 */ 618 static int 619 speedstep_sysctl_helper(SYSCTLFN_ARGS) 620 { 621 struct sysctlnode node; 622 struct lpcib_softc *sc = speedstep_cookie; 623 uint8_t state, state2; 624 int ostate, nstate, s, error = 0; 625 626 /* 627 * We do the dance with spl's to avoid being at high ipl during 628 * sysctl_lookup() which can both copyin and copyout. 629 */ 630 s = splserial(); 631 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 632 splx(s); 633 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 634 ostate = 1; 635 else 636 ostate = 0; 637 nstate = ostate; 638 639 node = *rnode; 640 node.sysctl_data = &nstate; 641 642 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 643 if (error || newp == NULL) 644 goto out; 645 646 /* Only two states are available */ 647 if (nstate != 0 && nstate != 1) { 648 error = EINVAL; 649 goto out; 650 } 651 652 s = splserial(); 653 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 654 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 655 ostate = 1; 656 else 657 ostate = 0; 658 659 if (ostate != nstate) { 660 uint8_t cntl; 661 662 if (nstate == 0) 663 state2 |= LPCIB_PM_SS_STATE_LOW; 664 else 665 state2 &= ~LPCIB_PM_SS_STATE_LOW; 666 667 /* 668 * Must disable bus master arbitration during the change. 669 */ 670 cntl = SS_READ(sc, LPCIB_PM_CTRL); 671 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 672 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 673 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 674 } 675 splx(s); 676 out: 677 return error; 678 } 679 680 #if NHPET > 0 681 struct lpcib_hpet_attach_arg { 682 bus_space_tag_t hpet_mem_t; 683 uint32_t hpet_reg; 684 }; 685 686 static int 687 lpcib_hpet_match(device_t parent, struct cfdata *match, void *aux) 688 { 689 struct lpcib_hpet_attach_arg *arg = aux; 690 bus_space_tag_t tag; 691 bus_space_handle_t handle; 692 693 tag = arg->hpet_mem_t; 694 695 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 696 aprint_verbose("%s: HPET window not mapped, skipping\n", 697 parent->dv_xname); 698 return 0; 699 } 700 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 701 702 return 1; 703 } 704 705 static void 706 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 707 { 708 struct hpet_softc *sc = device_private(self); 709 struct lpcib_hpet_attach_arg *arg = aux; 710 711 aprint_naive("\n"); 712 aprint_normal("\n"); 713 714 sc->sc_memt = arg->hpet_mem_t; 715 716 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 717 &sc->sc_memh)) { 718 aprint_error("%s: HPET memory window could not be mapped", 719 sc->sc_dev.dv_xname); 720 return; 721 } 722 723 hpet_attach_subr(sc); 724 } 725 726 CFATTACH_DECL(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 727 lpcib_hpet_attach, NULL, NULL); 728 729 static void 730 lpcib_hpet_configure(struct lpcib_softc *sc) 731 { 732 struct lpcib_hpet_attach_arg arg; 733 uint32_t hpet_reg, val; 734 735 if (sc->sc_has_ich5_hpet) { 736 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_GEN_CNTL); 737 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 738 case LPCIB_ICH5_HPTC_0000: 739 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 740 break; 741 case LPCIB_ICH5_HPTC_1000: 742 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 743 break; 744 case LPCIB_ICH5_HPTC_2000: 745 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 746 break; 747 case LPCIB_ICH5_HPTC_3000: 748 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 749 break; 750 default: 751 return; 752 } 753 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 754 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_GEN_CNTL, val); 755 } else if (sc->sc_has_rcba) { 756 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 757 LPCIB_RCBA_HPTC); 758 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 759 case LPCIB_RCBA_HPTC_0000: 760 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 761 break; 762 case LPCIB_RCBA_HPTC_1000: 763 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 764 break; 765 case LPCIB_RCBA_HPTC_2000: 766 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 767 break; 768 case LPCIB_RCBA_HPTC_3000: 769 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 770 break; 771 default: 772 return; 773 } 774 val |= LPCIB_RCBA_HPTC_EN; 775 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 776 val); 777 } else { 778 /* No HPET here */ 779 return; 780 } 781 782 arg.hpet_mem_t = sc->sc_pa.pa_memt; 783 arg.hpet_reg = hpet_reg; 784 785 config_found_ia((struct device *)sc, "hpetichbus", &arg, NULL); 786 } 787 #endif 788
Indexes created Tue Sep 30 17:09:57 GMT 2025