ichlpcib.c revision 1.60
1 /* $NetBSD: ichlpcib.c,v 1.60 2023/05/09 23:10:11 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 34 * 35 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 36 * some power management and monitoring functions. 37 * Currently we support the watchdog timer, SpeedStep (on some systems), 38 * the gpio interface, hpet timer, hardware random number generator, 39 * and the power management timer. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.60 2023/05/09 23:10:11 riastradh Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/sysctl.h> 50 #include <sys/timetc.h> 51 #include <sys/gpio.h> 52 #include <sys/bus.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcidevs.h> 57 58 #include <dev/gpio/gpiovar.h> 59 60 #include <dev/ic/acpipmtimer.h> 61 #include <dev/ic/i82801lpcreg.h> 62 #include <dev/ic/i82801lpcvar.h> 63 #include <dev/ic/hpetreg.h> 64 #include <dev/ic/hpetvar.h> 65 66 #include <arch/x86/pci/tco.h> 67 68 #include "pcibvar.h" 69 #include "gpio.h" 70 #include "fwhrng.h" 71 72 #define LPCIB_GPIO_NPINS 64 73 74 struct lpcib_softc { 75 /* we call pcibattach() which assumes this starts like this: */ 76 struct pcib_softc sc_pcib; 77 78 struct pci_attach_args sc_pa; 79 int sc_has_rcba; 80 int sc_has_ich5_hpet; 81 82 /* RCBA */ 83 bus_space_tag_t sc_rcbat; 84 bus_space_handle_t sc_rcbah; 85 pcireg_t sc_rcba_reg; 86 87 /* Power management variables. */ 88 bus_space_tag_t sc_pmt; 89 bus_space_handle_t sc_pmh; 90 bus_size_t sc_iosize; 91 92 /* TCO variables. */ 93 bus_space_tag_t sc_tcot; 94 bus_space_handle_t sc_tcoh; 95 bus_size_t sc_tcosz; 96 97 /* HPET variables. */ 98 uint32_t sc_hpet_reg; 99 100 #if NGPIO > 0 101 device_t sc_gpiobus; 102 kmutex_t sc_gpio_mtx; 103 bus_space_tag_t sc_gpio_iot; 104 bus_space_handle_t sc_gpio_ioh; 105 bus_size_t sc_gpio_ios; 106 struct gpio_chipset_tag sc_gpio_gc; 107 gpio_pin_t sc_gpio_pins[LPCIB_GPIO_NPINS]; 108 #endif 109 110 #if NFWHRNG > 0 111 device_t sc_fwhbus; 112 #endif 113 114 /* Speedstep */ 115 pcireg_t sc_pmcon_orig; 116 117 /* Power management */ 118 pcireg_t sc_pirq[2]; 119 pcireg_t sc_pmcon; 120 pcireg_t sc_fwhsel2; 121 122 /* Child devices */ 123 device_t sc_tco; 124 device_t sc_hpetbus; 125 acpipmtimer_t sc_pmtimer; 126 pcireg_t sc_acpi_cntl; 127 128 struct sysctllog *sc_log; 129 }; 130 131 static int lpcibmatch(device_t, cfdata_t, void *); 132 static void lpcibattach(device_t, device_t, void *); 133 static int lpcibdetach(device_t, int); 134 static void lpcibchilddet(device_t, device_t); 135 static int lpcibrescan(device_t, const char *, const int *); 136 static bool lpcib_suspend(device_t, const pmf_qual_t *); 137 static bool lpcib_resume(device_t, const pmf_qual_t *); 138 static bool lpcib_shutdown(device_t, int); 139 140 static void pmtimer_configure(device_t); 141 static int pmtimer_unconfigure(device_t, int); 142 143 static void tcotimer_configure(device_t); 144 static int tcotimer_unconfigure(device_t, int); 145 146 static void speedstep_configure(device_t); 147 static void speedstep_unconfigure(device_t); 148 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 149 150 static void lpcib_hpet_configure(device_t); 151 static int lpcib_hpet_unconfigure(device_t, int); 152 153 #if NGPIO > 0 154 static void lpcib_gpio_configure(device_t); 155 static int lpcib_gpio_unconfigure(device_t, int); 156 static int lpcib_gpio_pin_read(void *, int); 157 static void lpcib_gpio_pin_write(void *, int, int); 158 static void lpcib_gpio_pin_ctl(void *, int, int); 159 #endif 160 161 #if NFWHRNG > 0 162 static void lpcib_fwh_configure(device_t); 163 static int lpcib_fwh_unconfigure(device_t, int); 164 #endif 165 166 struct lpcib_softc *speedstep_cookie; /* XXX */ 167 168 CFATTACH_DECL2_NEW(ichlpcib, sizeof(struct lpcib_softc), 169 lpcibmatch, lpcibattach, lpcibdetach, NULL, lpcibrescan, lpcibchilddet); 170 171 static const struct lpcib_device { 172 pcireg_t vendor, product; 173 int has_rcba; 174 int has_ich5_hpet; 175 } lpcib_devices[] = { 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_LPC, 1, 0 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3420_LPC, 1, 0 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3450_LPC, 1, 0 }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 1, 0 }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_63XXESB_LPC, 1, 0 }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 0, 0 }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 0, 0 }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 0, 1 }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 1, 0 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IM_LPC, 1, 0 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IEM_LPC, 1, 0 }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_LPC, 1, 0 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JDO_LPC, 1, 0 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIB_LPC, 1, 0 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JIR_LPC, 1, 0 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C202_LPC, 1, 0 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C204_LPC, 1, 0 }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C206_LPC, 1, 0 }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C216_LPC, 1, 0 }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM10_LPC, 1, 0 }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H55_LPC, 1, 0 }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H57_LPC, 1, 0 }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM55_LPC, 1, 0 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM57_LPC, 1, 0 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P55_LPC, 1, 0 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PM55_LPC, 1, 0 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q57_LPC, 1, 0 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM57_LPC, 1, 0 }, 225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS57_LPC, 1, 0 }, 226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B65_LPC, 1, 0 }, 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H61_LPC, 1, 0 }, 228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H67_LPC, 1, 0 }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM65_LPC, 1, 0 }, 230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM67_LPC, 1, 0 }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_P67_LPC, 1, 0 }, 232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q65_LPC, 1, 0 }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q67_LPC, 1, 0 }, 234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM67_LPC, 1, 0 }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QS67_LPC, 1, 0 }, 236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_UM67_LPC, 1, 0 }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z68_LPC, 1, 0 }, 238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B75_LPC, 1, 0 }, 239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H77_LPC, 1, 0 }, 240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM70_LPC, 1, 0 }, 241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM75_LPC, 1, 0 }, 242 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM76_LPC, 1, 0 }, 243 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_HM77_LPC, 1, 0 }, 244 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QM77_LPC, 1, 0 }, 245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_QS77_LPC, 1, 0 }, 246 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MOBILE_UM77_LPC, 1, 0 }, 247 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_NM70_LPC, 1, 0 }, 248 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q75_LPC, 1, 0 }, 249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q77_LPC, 1, 0 }, 250 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z75_LPC, 1, 0 }, 251 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z77_LPC, 1, 0 }, 252 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z87_LPC, 1, 0 }, 253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z85_LPC, 1, 0 }, 254 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM86_LPC, 1, 0 }, 255 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H87_LPC, 1, 0 }, 256 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HM87_LPC, 1, 0 }, 257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q85_LPC, 1, 0 }, 258 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Q87_LPC, 1, 0 }, 259 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_QM87_LPC, 1, 0 }, 260 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_B85_LPC, 1, 0 }, 261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H97_LPC, 1, 0 }, 262 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_Z97_LPC, 1, 0 }, 263 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X99_LPC, 1, 0 }, 264 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X99_LPC_2, 1, 0 }, 265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE5G_M_LPC_4, 1, 0 }, 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE5G_M_LPC_7, 1, 0 }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C222_LPC, 1, 0 }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C224_LPC, 1, 0 }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C226_LPC, 1, 0 }, 270 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_H81_LPC, 1, 0 }, 271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_LPC, 1, 0 }, 272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_LPC, 1, 0 }, 273 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCL_LPC, 1, 0 }, 274 #if 0 275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_1, 1, 0 }, 276 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_2, 1, 0 }, 277 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_3, 1, 0 }, 278 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_PCU_4, 1, 0 }, 279 #endif 280 281 { 0, 0, 0, 0 }, 282 }; 283 284 /* 285 * Allow user to enable GPIO functionality if they really need it. The 286 * vast majority of systems with an ICH should not expose GPIO to the 287 * kernel or user. In at least one instance the gpio_resume() handler 288 * on ICH GPIO was found to sabotage S3 suspend/resume. 289 */ 290 int ichlpcib_gpio_disable = 1; 291 292 /* 293 * Autoconf callbacks. 294 */ 295 static int 296 lpcibmatch(device_t parent, cfdata_t match, void *aux) 297 { 298 struct pci_attach_args *pa = aux; 299 const struct lpcib_device *lpcib_dev; 300 301 /* We are ISA bridge, of course */ 302 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 303 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 304 return 0; 305 306 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 307 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 308 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 309 return 10; 310 } 311 312 return 0; 313 } 314 315 static void 316 lpcibattach(device_t parent, device_t self, void *aux) 317 { 318 struct pci_attach_args *pa = aux; 319 struct lpcib_softc *sc = device_private(self); 320 const struct lpcib_device *lpcib_dev; 321 pcireg_t pmbase; 322 323 sc->sc_pa = *pa; 324 325 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 326 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 327 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 328 continue; 329 sc->sc_has_rcba = lpcib_dev->has_rcba; 330 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 331 break; 332 } 333 334 pcibattach(parent, self, aux); 335 336 /* 337 * Part of our I/O registers are used as ACPI PM regs. 338 * Since our ACPI subsystem accesses the I/O space directly so far, 339 * we do not have to bother bus_space I/O map confliction. 340 * 341 * The PMBASE register is alike PCI BAR but not completely compatible 342 * with it. The PMBASE define the base address and the type but 343 * not describe the size. The value of the register may be lower 344 * than LPCIB_PCI_PM_SIZE. It makes impossible to use 345 * pci_mapreg_submap() because the function does range check. 346 */ 347 sc->sc_pmt = pa->pa_iot; 348 pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE); 349 if (bus_space_map(sc->sc_pmt, PCI_MAPREG_IO_ADDR(pmbase), 350 LPCIB_PCI_PM_SIZE, 0, &sc->sc_pmh) != 0) { 351 aprint_error_dev(self, 352 "can't map power management i/o space\n"); 353 return; 354 } 355 356 if (bus_space_subregion(sc->sc_pmt, sc->sc_pmh, PMC_TCO_BASE, 357 TCO_REGSIZE, &sc->sc_tcoh)) { 358 aprint_error_dev(self, "can't map TCO space\n"); 359 } else { 360 sc->sc_tcot = sc->sc_pmt; 361 } 362 363 sc->sc_pmcon_orig = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 364 LPCIB_PCI_GEN_PMCON_1); 365 366 /* For ICH6 and later, always enable RCBA */ 367 if (sc->sc_has_rcba) { 368 pcireg_t rcba; 369 370 sc->sc_rcbat = sc->sc_pa.pa_memt; 371 372 rcba = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 373 LPCIB_RCBA); 374 if ((rcba & LPCIB_RCBA_EN) == 0) { 375 aprint_error_dev(self, "RCBA is not enabled\n"); 376 return; 377 } 378 rcba &= ~LPCIB_RCBA_EN; 379 380 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 381 &sc->sc_rcbah)) { 382 aprint_error_dev(self, "RCBA could not be mapped\n"); 383 return; 384 } 385 } 386 387 /* Set up the power management timer. */ 388 pmtimer_configure(self); 389 390 /* Set up the TCO (watchdog). */ 391 tcotimer_configure(self); 392 393 /* Set up SpeedStep. */ 394 speedstep_configure(self); 395 396 /* Set up HPET. */ 397 lpcib_hpet_configure(self); 398 399 #if NGPIO > 0 400 /* Set up GPIO */ 401 lpcib_gpio_configure(self); 402 #endif 403 404 #if NFWHRNG > 0 405 lpcib_fwh_configure(self); 406 #endif 407 408 /* Install power handler */ 409 if (!pmf_device_register1(self, lpcib_suspend, lpcib_resume, 410 lpcib_shutdown)) 411 aprint_error_dev(self, "couldn't establish power handler\n"); 412 } 413 414 static void 415 lpcibchilddet(device_t self, device_t child) 416 { 417 struct lpcib_softc *sc = device_private(self); 418 uint32_t val; 419 420 #if NFWHRNG > 0 421 if (sc->sc_fwhbus == child) { 422 sc->sc_fwhbus = NULL; 423 return; 424 } 425 #endif 426 #if NGPIO > 0 427 if (sc->sc_gpiobus == child) { 428 sc->sc_gpiobus = NULL; 429 return; 430 } 431 #endif 432 if (sc->sc_tco == child) { 433 sc->sc_tco = NULL; 434 return; 435 } 436 437 if (sc->sc_hpetbus != child) { 438 pcibchilddet(self, child); 439 return; 440 } 441 sc->sc_hpetbus = NULL; 442 if (sc->sc_has_ich5_hpet) { 443 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 444 LPCIB_PCI_GEN_CNTL); 445 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 446 case LPCIB_ICH5_HPTC_0000: 447 case LPCIB_ICH5_HPTC_1000: 448 case LPCIB_ICH5_HPTC_2000: 449 case LPCIB_ICH5_HPTC_3000: 450 break; 451 default: 452 return; 453 } 454 val &= ~LPCIB_ICH5_HPTC_EN; 455 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 456 LPCIB_PCI_GEN_CNTL, val); 457 } else if (sc->sc_has_rcba) { 458 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 459 LPCIB_RCBA_HPTC); 460 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 461 case LPCIB_RCBA_HPTC_0000: 462 case LPCIB_RCBA_HPTC_1000: 463 case LPCIB_RCBA_HPTC_2000: 464 case LPCIB_RCBA_HPTC_3000: 465 break; 466 default: 467 return; 468 } 469 val &= ~LPCIB_RCBA_HPTC_EN; 470 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 471 val); 472 } 473 } 474 475 static int 476 lpcibrescan(device_t self, const char *ifattr, const int *locators) 477 { 478 struct lpcib_softc *sc = device_private(self); 479 480 if (ifattr_match(ifattr, "tcoichbus") && sc->sc_tco == NULL) 481 tcotimer_configure(self); 482 483 #if NFWHRNG > 0 484 if (ifattr_match(ifattr, "fwhichbus") && sc->sc_fwhbus == NULL) 485 lpcib_fwh_configure(self); 486 #endif 487 488 if (ifattr_match(ifattr, "hpetichbus") && sc->sc_hpetbus == NULL) 489 lpcib_hpet_configure(self); 490 491 #if NGPIO > 0 492 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpiobus == NULL) 493 lpcib_gpio_configure(self); 494 #endif 495 496 return pcibrescan(self, ifattr, locators); 497 } 498 499 static int 500 lpcibdetach(device_t self, int flags) 501 { 502 struct lpcib_softc *sc = device_private(self); 503 int rc; 504 505 pmf_device_deregister(self); 506 507 #if NFWHRNG > 0 508 if ((rc = lpcib_fwh_unconfigure(self, flags)) != 0) 509 return rc; 510 #endif 511 512 if ((rc = lpcib_hpet_unconfigure(self, flags)) != 0) 513 return rc; 514 515 #if NGPIO > 0 516 if ((rc = lpcib_gpio_unconfigure(self, flags)) != 0) 517 return rc; 518 #endif 519 520 /* Set up SpeedStep. */ 521 speedstep_unconfigure(self); 522 523 if ((rc = tcotimer_unconfigure(self, flags)) != 0) 524 return rc; 525 526 if ((rc = pmtimer_unconfigure(self, flags)) != 0) 527 return rc; 528 529 if (sc->sc_has_rcba) 530 bus_space_unmap(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_SIZE); 531 532 bus_space_unmap(sc->sc_pmt, sc->sc_pmh, sc->sc_iosize); 533 534 return pcibdetach(self, flags); 535 } 536 537 static bool 538 lpcib_shutdown(device_t dv, int howto) 539 { 540 struct lpcib_softc *sc = device_private(dv); 541 542 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 543 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 544 545 return true; 546 } 547 548 static bool 549 lpcib_suspend(device_t dv, const pmf_qual_t *qual) 550 { 551 struct lpcib_softc *sc = device_private(dv); 552 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 553 pcitag_t tag = sc->sc_pcib.sc_tag; 554 555 /* capture PIRQ routing control registers */ 556 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 557 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 558 559 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 560 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 561 562 if (sc->sc_has_rcba) { 563 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 564 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 565 LPCIB_RCBA_HPTC); 566 } else if (sc->sc_has_ich5_hpet) { 567 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 568 } 569 570 return true; 571 } 572 573 static bool 574 lpcib_resume(device_t dv, const pmf_qual_t *qual) 575 { 576 struct lpcib_softc *sc = device_private(dv); 577 pci_chipset_tag_t pc = sc->sc_pcib.sc_pc; 578 pcitag_t tag = sc->sc_pcib.sc_tag; 579 580 /* restore PIRQ routing control registers */ 581 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 582 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 583 584 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 585 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 586 587 if (sc->sc_has_rcba) { 588 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 589 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 590 sc->sc_hpet_reg); 591 } else if (sc->sc_has_ich5_hpet) { 592 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 593 } 594 595 return true; 596 } 597 598 /* 599 * Initialize the power management timer. 600 */ 601 static void 602 pmtimer_configure(device_t self) 603 { 604 struct lpcib_softc *sc = device_private(self); 605 pcireg_t control; 606 607 /* 608 * Check if power management I/O space is enabled and enable the ACPI_EN 609 * bit if it's disabled. 610 */ 611 control = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 612 LPCIB_PCI_ACPI_CNTL); 613 sc->sc_acpi_cntl = control; 614 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 615 control |= LPCIB_PCI_ACPI_CNTL_EN; 616 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 617 LPCIB_PCI_ACPI_CNTL, control); 618 } 619 620 /* Attach our PM timer with the generic acpipmtimer function */ 621 sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_pmt, sc->sc_pmh, 622 PMC_PM1_TMR, 0); 623 } 624 625 static int 626 pmtimer_unconfigure(device_t self, int flags) 627 { 628 struct lpcib_softc *sc = device_private(self); 629 int rc; 630 631 if (sc->sc_pmtimer != NULL && 632 (rc = acpipmtimer_detach(sc->sc_pmtimer, flags)) != 0) 633 return rc; 634 635 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 636 LPCIB_PCI_ACPI_CNTL, sc->sc_acpi_cntl); 637 638 return 0; 639 } 640 641 /* 642 * Configure the watchdog timer. 643 */ 644 static void 645 tcotimer_configure(device_t self) 646 { 647 struct lpcib_softc *sc = device_private(self); 648 struct tco_attach_args arg; 649 650 if (sc->sc_has_rcba) 651 arg.ta_version = TCO_VERSION_RCBA; 652 else 653 arg.ta_version = TCO_VERSION_PCIB; 654 arg.ta_pmt = sc->sc_pmt; 655 arg.ta_pmh = sc->sc_pmh; 656 arg.ta_rcbat = sc->sc_rcbat; 657 arg.ta_rcbah = sc->sc_rcbah; 658 arg.ta_pcib = &sc->sc_pcib; 659 arg.ta_tcot = sc->sc_tcot; 660 arg.ta_tcoh = sc->sc_tcoh; 661 662 sc->sc_tco = config_found(self, &arg, NULL, 663 CFARGS(.iattr = "tcoichbus")); 664 } 665 666 static int 667 tcotimer_unconfigure(device_t self, int flags) 668 { 669 struct lpcib_softc *sc = device_private(self); 670 int rc; 671 672 if (sc->sc_tco != NULL && 673 (rc = config_detach(sc->sc_tco, flags)) != 0) 674 return rc; 675 676 return 0; 677 } 678 679 680 /* 681 * Intel ICH SpeedStep support. 682 */ 683 #define SS_READ(sc, reg) \ 684 bus_space_read_1((sc)->sc_pmt, (sc)->sc_pmh, (reg)) 685 #define SS_WRITE(sc, reg, val) \ 686 bus_space_write_1((sc)->sc_pmt, (sc)->sc_pmh, (reg), (val)) 687 688 /* 689 * Linux driver says that SpeedStep on older chipsets cause 690 * lockups on Dell Inspiron 8000 and 8100. 691 * It should also not be enabled on systems with the 82855GM 692 * Hub, which typically have an EST-enabled CPU. 693 */ 694 static int 695 speedstep_bad_hb_check(const struct pci_attach_args *pa) 696 { 697 698 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 699 PCI_REVISION(pa->pa_class) < 5) 700 return 1; 701 702 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82855GM_MCH) 703 return 1; 704 705 return 0; 706 } 707 708 static void 709 speedstep_configure(device_t self) 710 { 711 struct lpcib_softc *sc = device_private(self); 712 const struct sysctlnode *node, *ssnode; 713 int rv; 714 715 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 716 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC || 717 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 718 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 719 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 720 pcireg_t pmcon; 721 722 /* Enable SpeedStep if it isn't already enabled. */ 723 pmcon = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 724 LPCIB_PCI_GEN_PMCON_1); 725 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 726 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 727 LPCIB_PCI_GEN_PMCON_1, 728 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 729 730 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 731 if ((rv = sysctl_createv(&sc->sc_log, 0, NULL, &node, 732 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 733 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 734 goto err; 735 736 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 737 if ((rv = sysctl_createv(&sc->sc_log, 0, &node, &ssnode, 738 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 739 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 740 CTL_EOL)) != 0) 741 goto err; 742 743 /* XXX save the sc for IO tag/handle */ 744 speedstep_cookie = sc; 745 aprint_verbose_dev(self, "SpeedStep enabled\n"); 746 } 747 748 return; 749 750 err: 751 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 752 } 753 754 static void 755 speedstep_unconfigure(device_t self) 756 { 757 struct lpcib_softc *sc = device_private(self); 758 759 sysctl_teardown(&sc->sc_log); 760 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 761 LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon_orig); 762 763 speedstep_cookie = NULL; 764 } 765 766 /* 767 * get/set the SpeedStep state: 0 == low power, 1 == high power. 768 */ 769 static int 770 speedstep_sysctl_helper(SYSCTLFN_ARGS) 771 { 772 struct sysctlnode node; 773 struct lpcib_softc *sc = speedstep_cookie; 774 uint8_t state, state2; 775 int ostate, nstate, s, error = 0; 776 777 /* 778 * We do the dance with spl's to avoid being at high ipl during 779 * sysctl_lookup() which can both copyin and copyout. 780 */ 781 s = splserial(); 782 state = SS_READ(sc, PMC_PM_SS_CNTL); 783 splx(s); 784 if ((state & PMC_PM_SS_STATE_LOW) == 0) 785 ostate = 1; 786 else 787 ostate = 0; 788 nstate = ostate; 789 790 node = *rnode; 791 node.sysctl_data = &nstate; 792 793 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 794 if (error || newp == NULL) 795 goto out; 796 797 /* Only two states are available */ 798 if (nstate != 0 && nstate != 1) { 799 error = EINVAL; 800 goto out; 801 } 802 803 s = splserial(); 804 state2 = SS_READ(sc, PMC_PM_SS_CNTL); 805 if ((state2 & PMC_PM_SS_STATE_LOW) == 0) 806 ostate = 1; 807 else 808 ostate = 0; 809 810 if (ostate != nstate) { 811 uint8_t cntl; 812 813 if (nstate == 0) 814 state2 |= PMC_PM_SS_STATE_LOW; 815 else 816 state2 &= ~PMC_PM_SS_STATE_LOW; 817 818 /* 819 * Must disable bus master arbitration during the change. 820 */ 821 cntl = SS_READ(sc, PMC_PM_CTRL); 822 SS_WRITE(sc, PMC_PM_CTRL, cntl | PMC_PM_SS_CNTL_ARB_DIS); 823 SS_WRITE(sc, PMC_PM_SS_CNTL, state2); 824 SS_WRITE(sc, PMC_PM_CTRL, cntl); 825 } 826 splx(s); 827 out: 828 return error; 829 } 830 831 static void 832 lpcib_hpet_configure(device_t self) 833 { 834 struct lpcib_softc *sc = device_private(self); 835 struct lpcib_hpet_attach_args arg; 836 uint32_t hpet_reg, val; 837 838 if (sc->sc_has_ich5_hpet) { 839 val = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 840 LPCIB_PCI_GEN_CNTL); 841 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 842 case LPCIB_ICH5_HPTC_0000: 843 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 844 break; 845 case LPCIB_ICH5_HPTC_1000: 846 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 847 break; 848 case LPCIB_ICH5_HPTC_2000: 849 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 850 break; 851 case LPCIB_ICH5_HPTC_3000: 852 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 853 break; 854 default: 855 return; 856 } 857 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 858 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 859 LPCIB_PCI_GEN_CNTL, val); 860 } else if (sc->sc_has_rcba) { 861 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 862 LPCIB_RCBA_HPTC); 863 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 864 case LPCIB_RCBA_HPTC_0000: 865 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 866 break; 867 case LPCIB_RCBA_HPTC_1000: 868 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 869 break; 870 case LPCIB_RCBA_HPTC_2000: 871 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 872 break; 873 case LPCIB_RCBA_HPTC_3000: 874 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 875 break; 876 default: 877 return; 878 } 879 val |= LPCIB_RCBA_HPTC_EN; 880 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 881 val); 882 } else { 883 /* No HPET here */ 884 return; 885 } 886 887 arg.hpet_mem_t = sc->sc_pa.pa_memt; 888 arg.hpet_reg = hpet_reg; 889 890 sc->sc_hpetbus = config_found(self, &arg, NULL, 891 CFARGS(.iattr = "hpetichbus")); 892 } 893 894 static int 895 lpcib_hpet_unconfigure(device_t self, int flags) 896 { 897 struct lpcib_softc *sc = device_private(self); 898 int rc; 899 900 if (sc->sc_hpetbus != NULL && 901 (rc = config_detach(sc->sc_hpetbus, flags)) != 0) 902 return rc; 903 904 return 0; 905 } 906 907 #if NGPIO > 0 908 static void 909 lpcib_gpio_configure(device_t self) 910 { 911 struct lpcib_softc *sc = device_private(self); 912 struct gpiobus_attach_args gba; 913 pcireg_t gpio_cntl; 914 uint32_t use, io, bit; 915 int pin, shift, base_reg, cntl_reg, reg; 916 int rv; 917 918 if (ichlpcib_gpio_disable != 0) 919 return; 920 921 /* this implies ICH >= 6, and thus different mapreg */ 922 if (sc->sc_has_rcba) { 923 base_reg = LPCIB_PCI_GPIO_BASE_ICH6; 924 cntl_reg = LPCIB_PCI_GPIO_CNTL_ICH6; 925 } else { 926 base_reg = LPCIB_PCI_GPIO_BASE; 927 cntl_reg = LPCIB_PCI_GPIO_CNTL; 928 } 929 930 gpio_cntl = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 931 cntl_reg); 932 933 /* Is GPIO enabled? */ 934 if ((gpio_cntl & LPCIB_PCI_GPIO_CNTL_EN) == 0) 935 return; 936 /* 937 * The GPIO_BASE register is alike PCI BAR but not completely 938 * compatible with it. The PMBASE define the base address and the type 939 * but not describe the size. The value of the register may be lower 940 * than LPCIB_PCI_GPIO_SIZE. It makes impossible to use 941 * pci_mapreg_submap() because the function does range check. 942 */ 943 sc->sc_gpio_iot = sc->sc_pa.pa_iot; 944 reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg); 945 rv = bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(reg), 946 LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_ioh); 947 if (rv != 0) { 948 aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv); 949 return; 950 } 951 952 mutex_init(&sc->sc_gpio_mtx, MUTEX_DEFAULT, IPL_NONE); 953 954 for (pin = 0; pin < LPCIB_GPIO_NPINS; pin++) { 955 sc->sc_gpio_pins[pin].pin_num = pin; 956 957 /* Read initial state */ 958 reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2; 959 use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 960 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL; 961 io = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 4); 962 shift = pin % 32; 963 bit = __BIT(shift); 964 965 if ((use & bit) != 0) { 966 sc->sc_gpio_pins[pin].pin_caps = 967 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 968 if (pin < 32) 969 sc->sc_gpio_pins[pin].pin_caps |= 970 GPIO_PIN_PULSATE; 971 if ((io & bit) != 0) 972 sc->sc_gpio_pins[pin].pin_flags = 973 GPIO_PIN_INPUT; 974 else 975 sc->sc_gpio_pins[pin].pin_flags = 976 GPIO_PIN_OUTPUT; 977 } else 978 sc->sc_gpio_pins[pin].pin_caps = 0; 979 980 if (lpcib_gpio_pin_read(sc, pin) == 0) 981 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 982 else 983 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 984 985 } 986 987 /* Create controller tag */ 988 sc->sc_gpio_gc.gp_cookie = sc; 989 sc->sc_gpio_gc.gp_pin_read = lpcib_gpio_pin_read; 990 sc->sc_gpio_gc.gp_pin_write = lpcib_gpio_pin_write; 991 sc->sc_gpio_gc.gp_pin_ctl = lpcib_gpio_pin_ctl; 992 993 memset(&gba, 0, sizeof(gba)); 994 995 gba.gba_gc = &sc->sc_gpio_gc; 996 gba.gba_pins = sc->sc_gpio_pins; 997 gba.gba_npins = LPCIB_GPIO_NPINS; 998 999 sc->sc_gpiobus = config_found(self, &gba, gpiobus_print, 1000 CFARGS(.iattr = "gpiobus")); 1001 } 1002 1003 static int 1004 lpcib_gpio_unconfigure(device_t self, int flags) 1005 { 1006 struct lpcib_softc *sc = device_private(self); 1007 int rc; 1008 1009 if (sc->sc_gpiobus != NULL && 1010 (rc = config_detach(sc->sc_gpiobus, flags)) != 0) 1011 return rc; 1012 1013 mutex_destroy(&sc->sc_gpio_mtx); 1014 1015 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, sc->sc_gpio_ios); 1016 1017 return 0; 1018 } 1019 1020 static int 1021 lpcib_gpio_pin_read(void *arg, int pin) 1022 { 1023 struct lpcib_softc *sc = arg; 1024 uint32_t data; 1025 int reg, shift; 1026 1027 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1028 shift = pin % 32; 1029 1030 mutex_enter(&sc->sc_gpio_mtx); 1031 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1032 mutex_exit(&sc->sc_gpio_mtx); 1033 1034 return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW); 1035 } 1036 1037 static void 1038 lpcib_gpio_pin_write(void *arg, int pin, int value) 1039 { 1040 struct lpcib_softc *sc = arg; 1041 uint32_t data; 1042 int reg, shift; 1043 1044 reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2; 1045 shift = pin % 32; 1046 1047 mutex_enter(&sc->sc_gpio_mtx); 1048 1049 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1050 1051 if (value) 1052 data |= __BIT(shift); 1053 else 1054 data &= ~__BIT(shift); 1055 1056 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1057 1058 mutex_exit(&sc->sc_gpio_mtx); 1059 } 1060 1061 static void 1062 lpcib_gpio_pin_ctl(void *arg, int pin, int flags) 1063 { 1064 struct lpcib_softc *sc = arg; 1065 uint32_t data; 1066 int reg, shift; 1067 1068 shift = pin % 32; 1069 reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2; 1070 1071 mutex_enter(&sc->sc_gpio_mtx); 1072 1073 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1074 1075 if (flags & GPIO_PIN_OUTPUT) 1076 data &= ~__BIT(shift); 1077 1078 if (flags & GPIO_PIN_INPUT) 1079 data |= __BIT(shift); 1080 1081 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1082 1083 1084 if (pin < 32) { 1085 reg = LPCIB_GPIO_GPO_BLINK; 1086 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 1087 1088 if (flags & GPIO_PIN_PULSATE) 1089 data |= __BIT(shift); 1090 else 1091 data &= ~__BIT(shift); 1092 1093 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 1094 } 1095 1096 mutex_exit(&sc->sc_gpio_mtx); 1097 } 1098 #endif 1099 1100 #if NFWHRNG > 0 1101 static void 1102 lpcib_fwh_configure(device_t self) 1103 { 1104 struct lpcib_softc *sc; 1105 pcireg_t pr; 1106 1107 sc = device_private(self); 1108 1109 if (sc->sc_has_rcba) { 1110 /* 1111 * Very unlikely to find a 82802 on a ICH6 or newer. 1112 * Also the write enable register moved at that point. 1113 */ 1114 return; 1115 } else { 1116 /* Enable FWH write to identify FWH. */ 1117 pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1118 LPCIB_PCI_BIOS_CNTL); 1119 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1120 LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); 1121 } 1122 1123 sc->sc_fwhbus = config_found(self, NULL, NULL, 1124 CFARGS(.iattr = "fwhichbus")); 1125 1126 /* restore previous write enable setting */ 1127 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 1128 LPCIB_PCI_BIOS_CNTL, pr); 1129 } 1130 1131 static int 1132 lpcib_fwh_unconfigure(device_t self, int flags) 1133 { 1134 struct lpcib_softc *sc = device_private(self); 1135 int rc; 1136 1137 if (sc->sc_fwhbus != NULL && 1138 (rc = config_detach(sc->sc_fwhbus, flags)) != 0) 1139 return rc; 1140 1141 return 0; 1142 } 1143 #endif 1144
Indexes created Tue Sep 30 17:09:57 GMT 2025