ichlpcib.c revision 1.7
1 /* $NetBSD: ichlpcib.c,v 1.7 2008/01/15 00:24:47 drochner Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto and Matthew R. Green. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver 41 * 42 * LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has 43 * some power management and monitoring functions. 44 * Currently we support the watchdog timer, SpeedStep (on some systems) 45 * and the power management timer. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.7 2008/01/15 00:24:47 drochner Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/sysctl.h> 56 #include <sys/timetc.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/sysmon/sysmonvar.h> 64 65 #include <dev/ic/acpipmtimer.h> 66 #include <dev/ic/i82801lpcreg.h> 67 #include <dev/ic/hpetreg.h> 68 #include <dev/ic/hpetvar.h> 69 70 #include "hpet.h" 71 72 struct lpcib_softc { 73 /* Device object. */ 74 struct device sc_dev; 75 76 pci_chipset_tag_t sc_pc; 77 pcitag_t sc_pcitag; 78 79 struct pci_attach_args sc_pa; 80 int sc_has_rcba; 81 int sc_has_ich5_hpet; 82 83 /* RCBA */ 84 bus_space_tag_t sc_rcbat; 85 bus_space_handle_t sc_rcbah; 86 pcireg_t sc_rcba_reg; 87 88 /* Watchdog variables. */ 89 struct sysmon_wdog sc_smw; 90 bus_space_tag_t sc_iot; 91 bus_space_handle_t sc_ioh; 92 93 #if NHPET > 0 94 /* HPET variables. */ 95 uint32_t sc_hpet_reg; 96 #endif 97 98 /* Power management */ 99 pcireg_t sc_pirq[2]; 100 pcireg_t sc_pmcon; 101 pcireg_t sc_fwhsel2; 102 }; 103 104 static int lpcibmatch(struct device *, struct cfdata *, void *); 105 static void lpcibattach(struct device *, struct device *, void *); 106 static bool lpcib_suspend(device_t); 107 static bool lpcib_resume(device_t); 108 109 static void pmtimer_configure(struct lpcib_softc *); 110 111 static void tcotimer_configure(struct lpcib_softc *); 112 static int tcotimer_setmode(struct sysmon_wdog *); 113 static int tcotimer_tickle(struct sysmon_wdog *); 114 static void tcotimer_stop(struct lpcib_softc *); 115 static void tcotimer_start(struct lpcib_softc *); 116 static void tcotimer_status_reset(struct lpcib_softc *); 117 static int tcotimer_disable_noreboot(struct lpcib_softc *); 118 119 static void speedstep_configure(struct lpcib_softc *); 120 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 121 122 #if NHPET > 0 123 static void lpcib_hpet_configure(struct lpcib_softc *); 124 #endif 125 126 struct lpcib_softc *speedstep_cookie; /* XXX */ 127 128 /* Defined in arch/.../pci/pcib.c. */ 129 extern void pcibattach(struct device *, struct device *, void *); 130 131 CFATTACH_DECL(ichlpcib, sizeof(struct lpcib_softc), 132 lpcibmatch, lpcibattach, NULL, NULL); 133 134 static struct lpcib_device { 135 pcireg_t vendor, product; 136 int has_rcba; 137 int has_ich5_hpet; 138 } lpcib_devices[] = { 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 0, 0 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 0, 0 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 0, 0 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 0, 0 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 0, 0 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 0, 0 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 0, 0 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 0, 1 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 1, 0 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 1, 0 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 1, 0 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 1, 0 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 1, 0 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LPC, 1, 0 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HEM_LPC, 1, 0 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HH_LPC, 1, 0 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HO_LPC, 1, 0 }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801HBM_LPC, 1, 0 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 1, 0 }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 1, 0 }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 1, 0 }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 1, 0 }, 161 { 0, 0, 0, 0 }, 162 }; 163 164 /* 165 * Autoconf callbacks. 166 */ 167 static int 168 lpcibmatch(struct device *parent, struct cfdata *match, void *aux) 169 { 170 struct pci_attach_args *pa = aux; 171 struct lpcib_device *lpcib_dev; 172 173 /* We are ISA bridge, of course */ 174 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 175 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 176 return 0; 177 178 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 179 if (PCI_VENDOR(pa->pa_id) == lpcib_dev->vendor && 180 PCI_PRODUCT(pa->pa_id) == lpcib_dev->product) 181 return 10; 182 } 183 184 return 0; 185 } 186 187 static void 188 lpcibattach(struct device *parent, struct device *self, void *aux) 189 { 190 struct pci_attach_args *pa = aux; 191 struct lpcib_softc *sc = device_private(self); 192 struct lpcib_device *lpcib_dev; 193 194 sc->sc_pc = pa->pa_pc; 195 sc->sc_pcitag = pa->pa_tag; 196 sc->sc_pa = *pa; 197 198 for (lpcib_dev = lpcib_devices; lpcib_dev->vendor; ++lpcib_dev) { 199 if (PCI_VENDOR(pa->pa_id) != lpcib_dev->vendor || 200 PCI_PRODUCT(pa->pa_id) != lpcib_dev->product) 201 continue; 202 sc->sc_has_rcba = lpcib_dev->has_rcba; 203 sc->sc_has_ich5_hpet = lpcib_dev->has_ich5_hpet; 204 break; 205 } 206 207 pcibattach(parent, self, aux); 208 209 /* 210 * Part of our I/O registers are used as ACPI PM regs. 211 * Since our ACPI subsystem accesses the I/O space directly so far, 212 * we do not have to bother bus_space I/O map confliction. 213 */ 214 if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0, 215 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 216 aprint_error("%s: can't map power management i/o space", 217 sc->sc_dev.dv_xname); 218 return; 219 } 220 221 /* For ICH6 and later, always enable RCBA */ 222 if (sc->sc_has_rcba) { 223 pcireg_t rcba; 224 225 sc->sc_rcbat = sc->sc_pa.pa_memt; 226 227 rcba = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_RCBA); 228 if ((rcba & LPCIB_RCBA_EN) == 0) { 229 aprint_error("%s: RCBA is not enabled", 230 sc->sc_dev.dv_xname); 231 return; 232 } 233 rcba &= ~LPCIB_RCBA_EN; 234 235 if (bus_space_map(sc->sc_rcbat, rcba, LPCIB_RCBA_SIZE, 0, 236 &sc->sc_rcbah)) { 237 aprint_error("%s: RCBA could not be mapped", 238 sc->sc_dev.dv_xname); 239 return; 240 } 241 } 242 243 /* Set up the power management timer. */ 244 pmtimer_configure(sc); 245 246 /* Set up the TCO (watchdog). */ 247 tcotimer_configure(sc); 248 249 /* Set up SpeedStep. */ 250 speedstep_configure(sc); 251 252 #if NHPET > 0 253 /* Set up HPET. */ 254 lpcib_hpet_configure(sc); 255 #endif 256 257 /* Install power handler */ 258 if (!pmf_device_register(self, lpcib_suspend, lpcib_resume)) 259 aprint_error_dev(self, "couldn't establish power handler\n"); 260 } 261 262 static bool 263 lpcib_suspend(device_t dv) 264 { 265 struct lpcib_softc *sc = device_private(dv); 266 pci_chipset_tag_t pc = sc->sc_pc; 267 pcitag_t tag = sc->sc_pcitag; 268 269 /* capture PIRQ routing control registers */ 270 sc->sc_pirq[0] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQA_ROUT); 271 sc->sc_pirq[1] = pci_conf_read(pc, tag, LPCIB_PCI_PIRQE_ROUT); 272 273 sc->sc_pmcon = pci_conf_read(pc, tag, LPCIB_PCI_GEN_PMCON_1); 274 sc->sc_fwhsel2 = pci_conf_read(pc, tag, LPCIB_PCI_GEN_STA); 275 276 if (sc->sc_has_rcba) { 277 sc->sc_rcba_reg = pci_conf_read(pc, tag, LPCIB_RCBA); 278 #if NHPET > 0 279 sc->sc_hpet_reg = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 280 LPCIB_RCBA_HPTC); 281 #endif 282 } else if (sc->sc_has_ich5_hpet) { 283 #if NHPET > 0 284 sc->sc_hpet_reg = pci_conf_read(pc, tag, LPCIB_PCI_GEN_CNTL); 285 #endif 286 } 287 288 return true; 289 } 290 291 static bool 292 lpcib_resume(device_t dv) 293 { 294 struct lpcib_softc *sc = device_private(dv); 295 pci_chipset_tag_t pc = sc->sc_pc; 296 pcitag_t tag = sc->sc_pcitag; 297 298 /* restore PIRQ routing control registers */ 299 pci_conf_write(pc, tag, LPCIB_PCI_PIRQA_ROUT, sc->sc_pirq[0]); 300 pci_conf_write(pc, tag, LPCIB_PCI_PIRQE_ROUT, sc->sc_pirq[1]); 301 302 pci_conf_write(pc, tag, LPCIB_PCI_GEN_PMCON_1, sc->sc_pmcon); 303 pci_conf_write(pc, tag, LPCIB_PCI_GEN_STA, sc->sc_fwhsel2); 304 305 if (sc->sc_has_rcba) { 306 pci_conf_write(pc, tag, LPCIB_RCBA, sc->sc_rcba_reg); 307 #if NHPET > 0 308 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 309 sc->sc_hpet_reg); 310 #endif 311 } else if (sc->sc_has_ich5_hpet) { 312 #if NHPET > 0 313 pci_conf_write(pc, tag, LPCIB_PCI_GEN_CNTL, sc->sc_hpet_reg); 314 #endif 315 } 316 317 return true; 318 } 319 320 /* 321 * Initialize the power management timer. 322 */ 323 static void 324 pmtimer_configure(struct lpcib_softc *sc) 325 { 326 pcireg_t control; 327 328 /* 329 * Check if power management I/O space is enabled and enable the ACPI_EN 330 * bit if it's disabled. 331 */ 332 control = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL); 333 if ((control & LPCIB_PCI_ACPI_CNTL_EN) == 0) { 334 control |= LPCIB_PCI_ACPI_CNTL_EN; 335 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_ACPI_CNTL, 336 control); 337 } 338 339 /* Attach our PM timer with the generic acpipmtimer function */ 340 acpipmtimer_attach(&sc->sc_dev, sc->sc_iot, sc->sc_ioh, 341 LPCIB_PM1_TMR, 0); 342 } 343 344 /* 345 * Initialize the watchdog timer. 346 */ 347 static void 348 tcotimer_configure(struct lpcib_softc *sc) 349 { 350 uint32_t ioreg; 351 unsigned int period; 352 353 /* 354 * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit 355 * in the SMI_EN register is the last chance. 356 */ 357 if (tcotimer_disable_noreboot(sc)) { 358 ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); 359 ioreg |= LPCIB_SMI_EN_TCO_EN; 360 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); 361 } 362 363 /* Reset the watchdog status registers. */ 364 tcotimer_status_reset(sc); 365 366 /* Explicitly stop the TCO timer. */ 367 tcotimer_stop(sc); 368 369 /* 370 * Register the driver with the sysmon watchdog framework. 371 */ 372 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 373 sc->sc_smw.smw_cookie = sc; 374 sc->sc_smw.smw_setmode = tcotimer_setmode; 375 sc->sc_smw.smw_tickle = tcotimer_tickle; 376 if (sc->sc_has_rcba) 377 period = LPCIB_TCOTIMER2_MAX_TICK; 378 else 379 period = LPCIB_TCOTIMER_MAX_TICK; 380 sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(period); 381 382 if (sysmon_wdog_register(&sc->sc_smw)) { 383 aprint_error("%s: unable to register TCO timer" 384 "as a sysmon watchdog device.\n", 385 sc->sc_dev.dv_xname); 386 return; 387 } 388 389 aprint_verbose("%s: TCO (watchdog) timer configured.\n", 390 sc->sc_dev.dv_xname); 391 } 392 393 /* 394 * Sysmon watchdog callbacks. 395 */ 396 static int 397 tcotimer_setmode(struct sysmon_wdog *smw) 398 { 399 struct lpcib_softc *sc = smw->smw_cookie; 400 unsigned int period; 401 uint16_t ich6period = 0; 402 403 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 404 /* Stop the TCO timer. */ 405 tcotimer_stop(sc); 406 } else { 407 /* 408 * ICH6 or newer are limited to 2s min and 613s max. 409 * ICH5 or older are limited to 4s min and 39s max. 410 */ 411 if (sc->sc_has_rcba) { 412 if (smw->smw_period < LPCIB_TCOTIMER2_MIN_TICK || 413 smw->smw_period > LPCIB_TCOTIMER2_MAX_TICK) 414 return EINVAL; 415 } else { 416 if (smw->smw_period < LPCIB_TCOTIMER_MIN_TICK || 417 smw->smw_period > LPCIB_TCOTIMER_MAX_TICK) 418 return EINVAL; 419 } 420 period = lpcib_tcotimer_second_to_tick(smw->smw_period); 421 422 /* Stop the TCO timer, */ 423 tcotimer_stop(sc); 424 425 /* set the timeout, */ 426 if (sc->sc_has_rcba) { 427 /* ICH6 or newer */ 428 ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 429 LPCIB_TCO_TMR2); 430 ich6period &= 0xfc00; 431 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 432 LPCIB_TCO_TMR2, ich6period | period); 433 } else { 434 /* ICH5 or older */ 435 period |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, 436 LPCIB_TCO_TMR); 437 period &= 0xc0; 438 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 439 LPCIB_TCO_TMR, period); 440 } 441 442 /* and start/reload the timer. */ 443 tcotimer_start(sc); 444 tcotimer_tickle(smw); 445 } 446 447 return 0; 448 } 449 450 static int 451 tcotimer_tickle(struct sysmon_wdog *smw) 452 { 453 struct lpcib_softc *sc = smw->smw_cookie; 454 455 /* any value is allowed */ 456 if (sc->sc_has_rcba) 457 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 458 else 459 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); 460 461 return 0; 462 } 463 464 static void 465 tcotimer_stop(struct lpcib_softc *sc) 466 { 467 uint16_t ioreg; 468 469 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 470 ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; 471 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 472 } 473 474 static void 475 tcotimer_start(struct lpcib_softc *sc) 476 { 477 uint16_t ioreg; 478 479 ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); 480 ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; 481 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); 482 } 483 484 static void 485 tcotimer_status_reset(struct lpcib_softc *sc) 486 { 487 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, 488 LPCIB_TCO1_STS_TIMEOUT); 489 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 490 LPCIB_TCO2_STS_BOOT_STS); 491 bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, 492 LPCIB_TCO2_STS_SECONDS_TO_STS); 493 } 494 495 /* 496 * Clear the No Reboot (NR) bit, this enables reboots when the timer 497 * reaches the timeout for the second time. 498 */ 499 static int 500 tcotimer_disable_noreboot(struct lpcib_softc *sc) 501 { 502 503 if (sc->sc_has_rcba) { 504 uint32_t status; 505 506 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET); 507 status &= ~LPCIB_GCS_NO_REBOOT; 508 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET, status); 509 status = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_GCS_OFFSET); 510 if (status & LPCIB_GCS_NO_REBOOT) 511 goto error; 512 } else { 513 pcireg_t pcireg; 514 515 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 516 LPCIB_PCI_GEN_STA); 517 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) { 518 /* TCO timeout reset is disabled; try to enable it */ 519 pcireg &= ~LPCIB_PCI_GEN_STA_NO_REBOOT; 520 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 521 LPCIB_PCI_GEN_STA, pcireg); 522 if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) 523 goto error; 524 } 525 } 526 527 return 0; 528 error: 529 aprint_error("%s: TCO timer reboot disabled by hardware; " 530 "hope SMBIOS properly handles it.\n", sc->sc_dev.dv_xname); 531 return EINVAL; 532 } 533 534 535 /* 536 * Intel ICH SpeedStep support. 537 */ 538 #define SS_READ(sc, reg) \ 539 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)) 540 #define SS_WRITE(sc, reg, val) \ 541 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 542 543 /* 544 * Linux driver says that SpeedStep on older chipsets cause 545 * lockups on Dell Inspiron 8000 and 8100. 546 */ 547 static int 548 speedstep_bad_hb_check(struct pci_attach_args *pa) 549 { 550 551 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82815_FULL_HUB && 552 PCI_REVISION(pa->pa_class) < 5) 553 return 1; 554 555 return 0; 556 } 557 558 static void 559 speedstep_configure(struct lpcib_softc *sc) 560 { 561 const struct sysctlnode *node, *ssnode; 562 int rv; 563 564 /* Supported on ICH2-M, ICH3-M and ICH4-M. */ 565 if (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801DB_ISA || 566 PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801CAM_LPC || 567 (PCI_PRODUCT(sc->sc_pa.pa_id) == PCI_PRODUCT_INTEL_82801BAM_LPC && 568 pci_find_device(&sc->sc_pa, speedstep_bad_hb_check) == 0)) { 569 uint8_t pmcon; 570 571 /* Enable SpeedStep if it isn't already enabled. */ 572 pmcon = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 573 LPCIB_PCI_GEN_PMCON_1); 574 if ((pmcon & LPCIB_PCI_GEN_PMCON_1_SS_EN) == 0) 575 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 576 LPCIB_PCI_GEN_PMCON_1, 577 pmcon | LPCIB_PCI_GEN_PMCON_1_SS_EN); 578 579 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 580 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 581 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 582 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 583 goto err; 584 585 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 586 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 587 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 588 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 589 CTL_EOL)) != 0) 590 goto err; 591 592 /* XXX save the sc for IO tag/handle */ 593 speedstep_cookie = sc; 594 aprint_verbose("%s: SpeedStep enabled\n", sc->sc_dev.dv_xname); 595 } 596 597 return; 598 599 err: 600 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 601 } 602 603 /* 604 * get/set the SpeedStep state: 0 == low power, 1 == high power. 605 */ 606 static int 607 speedstep_sysctl_helper(SYSCTLFN_ARGS) 608 { 609 struct sysctlnode node; 610 struct lpcib_softc *sc = speedstep_cookie; 611 uint8_t state, state2; 612 int ostate, nstate, s, error = 0; 613 614 /* 615 * We do the dance with spl's to avoid being at high ipl during 616 * sysctl_lookup() which can both copyin and copyout. 617 */ 618 s = splserial(); 619 state = SS_READ(sc, LPCIB_PM_SS_CNTL); 620 splx(s); 621 if ((state & LPCIB_PM_SS_STATE_LOW) == 0) 622 ostate = 1; 623 else 624 ostate = 0; 625 nstate = ostate; 626 627 node = *rnode; 628 node.sysctl_data = &nstate; 629 630 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 631 if (error || newp == NULL) 632 goto out; 633 634 /* Only two states are available */ 635 if (nstate != 0 && nstate != 1) { 636 error = EINVAL; 637 goto out; 638 } 639 640 s = splserial(); 641 state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); 642 if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) 643 ostate = 1; 644 else 645 ostate = 0; 646 647 if (ostate != nstate) { 648 uint8_t cntl; 649 650 if (nstate == 0) 651 state2 |= LPCIB_PM_SS_STATE_LOW; 652 else 653 state2 &= ~LPCIB_PM_SS_STATE_LOW; 654 655 /* 656 * Must disable bus master arbitration during the change. 657 */ 658 cntl = SS_READ(sc, LPCIB_PM_CTRL); 659 SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); 660 SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); 661 SS_WRITE(sc, LPCIB_PM_CTRL, cntl); 662 } 663 splx(s); 664 out: 665 return error; 666 } 667 668 #if NHPET > 0 669 struct lpcib_hpet_attach_arg { 670 bus_space_tag_t hpet_mem_t; 671 uint32_t hpet_reg; 672 }; 673 674 static int 675 lpcib_hpet_match(device_t parent, struct cfdata *match, void *aux) 676 { 677 struct lpcib_hpet_attach_arg *arg = aux; 678 bus_space_tag_t tag; 679 bus_space_handle_t handle; 680 681 tag = arg->hpet_mem_t; 682 683 if (bus_space_map(tag, arg->hpet_reg, HPET_WINDOW_SIZE, 0, &handle)) { 684 aprint_verbose("%s: HPET window not mapped, skipping\n", 685 parent->dv_xname); 686 return 0; 687 } 688 bus_space_unmap(tag, handle, HPET_WINDOW_SIZE); 689 690 return 1; 691 } 692 693 static void 694 lpcib_hpet_attach(device_t parent, device_t self, void *aux) 695 { 696 struct hpet_softc *sc = device_private(self); 697 struct lpcib_hpet_attach_arg *arg = aux; 698 699 aprint_naive("\n"); 700 aprint_normal("\n"); 701 702 sc->sc_memt = arg->hpet_mem_t; 703 704 if (bus_space_map(sc->sc_memt, arg->hpet_reg, HPET_WINDOW_SIZE, 0, 705 &sc->sc_memh)) { 706 aprint_error("%s: HPET memory window could not be mapped", 707 sc->sc_dev.dv_xname); 708 return; 709 } 710 711 hpet_attach_subr(sc); 712 } 713 714 CFATTACH_DECL(ichlpcib_hpet, sizeof(struct hpet_softc), lpcib_hpet_match, 715 lpcib_hpet_attach, NULL, NULL); 716 717 static void 718 lpcib_hpet_configure(struct lpcib_softc *sc) 719 { 720 struct lpcib_hpet_attach_arg arg; 721 uint32_t hpet_reg, val; 722 723 if (sc->sc_has_ich5_hpet) { 724 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_GEN_CNTL); 725 switch (val & LPCIB_ICH5_HPTC_WIN_MASK) { 726 case LPCIB_ICH5_HPTC_0000: 727 hpet_reg = LPCIB_ICH5_HPTC_0000_BASE; 728 break; 729 case LPCIB_ICH5_HPTC_1000: 730 hpet_reg = LPCIB_ICH5_HPTC_1000_BASE; 731 break; 732 case LPCIB_ICH5_HPTC_2000: 733 hpet_reg = LPCIB_ICH5_HPTC_2000_BASE; 734 break; 735 case LPCIB_ICH5_HPTC_3000: 736 hpet_reg = LPCIB_ICH5_HPTC_3000_BASE; 737 break; 738 default: 739 return; 740 } 741 val |= sc->sc_hpet_reg | LPCIB_ICH5_HPTC_EN; 742 pci_conf_write(sc->sc_pc, sc->sc_pcitag, LPCIB_PCI_GEN_CNTL, val); 743 } else if (sc->sc_has_rcba) { 744 val = bus_space_read_4(sc->sc_rcbat, sc->sc_rcbah, 745 LPCIB_RCBA_HPTC); 746 switch (val & LPCIB_RCBA_HPTC_WIN_MASK) { 747 case LPCIB_RCBA_HPTC_0000: 748 hpet_reg = LPCIB_RCBA_HPTC_0000_BASE; 749 break; 750 case LPCIB_RCBA_HPTC_1000: 751 hpet_reg = LPCIB_RCBA_HPTC_1000_BASE; 752 break; 753 case LPCIB_RCBA_HPTC_2000: 754 hpet_reg = LPCIB_RCBA_HPTC_2000_BASE; 755 break; 756 case LPCIB_RCBA_HPTC_3000: 757 hpet_reg = LPCIB_RCBA_HPTC_3000_BASE; 758 break; 759 default: 760 return; 761 } 762 val |= LPCIB_RCBA_HPTC_EN; 763 bus_space_write_4(sc->sc_rcbat, sc->sc_rcbah, LPCIB_RCBA_HPTC, 764 val); 765 } else { 766 /* No HPET here */ 767 return; 768 } 769 770 arg.hpet_mem_t = sc->sc_pa.pa_memt; 771 arg.hpet_reg = hpet_reg; 772 773 config_found_ia((struct device *)sc, "hpetichbus", &arg, NULL); 774 } 775 #endif 776
Indexes created Tue Sep 30 17:09:57 GMT 2025