imcsmb.c revision 1.7
1 /* $NetBSD: imcsmb.c,v 1.7 2025/09/15 13:23:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 34 * 35 * Authors: Joe Kloss; Ravi Pokala (rpokala (at) freebsd.org) 36 * 37 * Copyright (c) 2017-2018 Panasas 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 59 * SUCH DAMAGE. 60 */ 61 62 /* 63 * Driver for the SMBus controllers in Intel's Integrated Memory Controllers 64 * in certain CPUs. A more detailed description of this device is present 65 * in imc.c 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: imcsmb.c,v 1.7 2025/09/15 13:23:02 thorpej Exp $"); 70 71 #include <sys/param.h> 72 #include <sys/kernel.h> 73 #include <sys/module.h> 74 #include <sys/endian.h> 75 #include <sys/errno.h> 76 #include <sys/mutex.h> 77 #include <sys/bus.h> 78 79 #include <dev/pci/pcidevs.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcireg.h> 82 83 #include <dev/i2c/i2cvar.h> 84 85 #include "imcsmb_reg.h" 86 #include "imcsmb_var.h" 87 88 /* Device methods */ 89 static int imcsmb_probe(device_t, cfdata_t, void *); 90 static void imcsmb_attach(device_t, device_t, void *); 91 static int imcsmb_detach(device_t, int flags); 92 static int imcsmb_rescan(device_t, const char *, const int *); 93 static void imcsmb_chdet(device_t, device_t); 94 95 CFATTACH_DECL3_NEW(imcsmb, sizeof(struct imcsmb_softc), 96 imcsmb_probe, imcsmb_attach, imcsmb_detach, NULL, imcsmb_rescan, 97 imcsmb_chdet, 0); 98 99 /* Bus access control methods */ 100 static int imcsmb_acquire_bus(void *cookie, int flags); 101 static void imcsmb_release_bus(void *cookie, int flags); 102 103 /* SMBus methods */ 104 static int imcsmb_exec(void *cookie, i2c_op_t, i2c_addr_t, const void *, 105 size_t, void *, size_t, int); 106 107 /** 108 * device_attach() method. Set up the softc, including getting the set of the 109 * parent imcsmb_pci's registers that we will use. Create the smbus(4) device, 110 * which any SMBus slave device drivers will connect to. Probe and attach 111 * anything which might be downstream. 112 * 113 * @author rpokala 114 * 115 * @param[in,out] dev 116 * Device being attached. 117 */ 118 119 static void 120 imcsmb_attach(device_t parent, device_t self, void *aux) 121 { 122 struct imcsmb_softc *sc = device_private(self); 123 struct imc_attach_args *imca = aux; 124 125 aprint_naive("\n"); 126 aprint_normal(": SMBus controller\n"); 127 128 /* Initialize private state */ 129 sc->sc_dev = self; 130 sc->sc_regs = imca->ia_regs; 131 sc->sc_pci_tag = imca->ia_pci_tag; 132 sc->sc_pci_chipset_tag = imca->ia_pci_chipset_tag; 133 134 if (!pmf_device_register(self, NULL, NULL)) 135 aprint_error_dev(self, "couldn't establish power handler\n"); 136 137 imcsmb_rescan(self, NULL, NULL); 138 } 139 140 static int 141 imcsmb_rescan(device_t self, const char *ifattr, const int *locs) 142 { 143 struct imcsmb_softc *sc = device_private(self); 144 145 /* Create the i2cbus child */ 146 if (sc->sc_smbus != NULL) 147 return 0; 148 149 iic_tag_init(&sc->sc_i2c_tag); 150 sc->sc_i2c_tag.ic_cookie = sc; 151 sc->sc_i2c_tag.ic_acquire_bus = imcsmb_acquire_bus; 152 sc->sc_i2c_tag.ic_release_bus = imcsmb_release_bus; 153 sc->sc_i2c_tag.ic_exec = imcsmb_exec; 154 155 sc->sc_smbus = iicbus_attach(self, &sc->sc_i2c_tag); 156 157 if (sc->sc_smbus == NULL) { 158 aprint_normal_dev(self, "no child found\n"); 159 return ENXIO; 160 } 161 162 return 0; 163 } 164 165 static void 166 imcsmb_chdet(device_t self, device_t child) 167 { 168 struct imcsmb_softc *sc = device_private(self); 169 170 if (child == sc->sc_smbus) 171 sc->sc_smbus = NULL; 172 else KASSERT(child == NULL); 173 } 174 175 /** 176 * device_detach() method. attach() didn't do any allocations, so there's 177 * nothing special needed 178 */ 179 static int 180 imcsmb_detach(device_t self, int flags) 181 { 182 struct imcsmb_softc *sc = device_private(self); 183 int error; 184 185 error = config_detach_children(self, flags); 186 if (error) 187 return error; 188 189 pmf_device_deregister(self); 190 iic_tag_fini(&sc->sc_i2c_tag); 191 return 0; 192 } 193 194 /** 195 * device_probe() method. All the actual probing was done by the imc 196 * parent, so just report success. 197 * 198 * @author Joe Kloss 199 * 200 * @param[in,out] dev 201 * Device being probed. 202 */ 203 static int 204 imcsmb_probe(device_t parent, cfdata_t match, void *aux) 205 { 206 207 return 1; 208 } 209 210 static int 211 imcsmb_acquire_bus(void *cookie, int flags) 212 { 213 struct imcsmb_softc *sc = cookie; 214 215 if (cold) 216 return 0; 217 218 imc_callback(sc, IMC_BIOS_DISABLE); 219 220 return 0; 221 } 222 223 static void 224 imcsmb_release_bus(void *cookie, int flags) 225 { 226 struct imcsmb_softc *sc = cookie; 227 228 if (cold) 229 return; 230 231 imc_callback(sc, IMC_BIOS_ENABLE); 232 } 233 234 static int 235 imcsmb_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 236 size_t cmdlen, void *buf, size_t len, int flags) 237 { 238 struct imcsmb_softc *sc = cookie; 239 int i; 240 int rc = 0; 241 uint32_t cmd_val; 242 uint32_t cntl_val; 243 uint32_t orig_cntl_val; 244 uint32_t stat_val; 245 uint16_t *word; 246 uint16_t lword; 247 uint8_t *byte; 248 uint8_t lbyte; 249 uint8_t cmd; 250 251 if ((cmdlen != 1) || (len > 2) || (len < 1)) 252 return EINVAL; 253 254 byte = (uint8_t *) buf; 255 word = (uint16_t *) buf; 256 lbyte = *byte; 257 lword = *word; 258 259 /* We modify the value of the control register; save the original, so 260 * we can restore it later 261 */ 262 orig_cntl_val = pci_conf_read(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 263 sc->sc_regs->smb_cntl); 264 265 cntl_val = orig_cntl_val; 266 267 /* 268 * Set up the SMBCNTL register 269 */ 270 271 /* [31:28] Clear the existing value of the DTI bits, then set them to 272 * the four high bits of the slave address. 273 */ 274 cntl_val &= ~IMCSMB_CNTL_DTI_MASK; 275 cntl_val |= ((uint32_t) addr & 0x78) << 25; 276 277 /* [27:27] Set the CLK_OVERRIDE bit, to enable normal operation */ 278 cntl_val |= IMCSMB_CNTL_CLK_OVERRIDE; 279 280 /* [26:26] Clear the WRITE_DISABLE bit; the datasheet says this isn't 281 * necessary, but empirically, it is. 282 */ 283 cntl_val &= ~IMCSMB_CNTL_WRITE_DISABLE_BIT; 284 285 /* [9:9] Clear the POLL_EN bit, to stop the hardware TSOD polling. */ 286 cntl_val &= ~IMCSMB_CNTL_POLL_EN; 287 288 /* 289 * Set up the SMBCMD register 290 */ 291 292 /* [31:31] Set the TRIGGER bit; when this gets written, the controller 293 * will issue the command. 294 */ 295 cmd_val = IMCSMB_CMD_TRIGGER_BIT; 296 297 /* [29:29] For word operations, set the WORD_ACCESS bit. */ 298 if (len == 2) { 299 cmd_val |= IMCSMB_CMD_WORD_ACCESS; 300 } 301 302 /* [27:27] For write operations, set the WRITE bit. */ 303 if (I2C_OP_WRITE_P(op)) { 304 cmd_val |= IMCSMB_CMD_WRITE_BIT; 305 } 306 307 /* [26:24] The three non-DTI, non-R/W bits of the slave address. */ 308 cmd_val |= (uint32_t) ((addr & 0x7) << 24); 309 310 /* [23:16] The command (offset in the case of an EEPROM, or register in 311 * the case of TSOD or NVDIMM controller). 312 */ 313 cmd = *((const uint8_t *) cmdbuf); 314 cmd_val |= (uint32_t) (cmd << 16); 315 316 /* [15:0] The data to be written for a write operation. */ 317 if (I2C_OP_WRITE_P(op)) { 318 if (len == 2) { 319 /* The datasheet says the controller uses different 320 * endianness for word operations on I2C vs SMBus! 321 * I2C: [15:8] = MSB; [7:0] = LSB 322 * SMB: [15:8] = LSB; [7:0] = MSB 323 * As a practical matter, this controller is very 324 * specifically for use with DIMMs, the SPD (and 325 * NVDIMM controllers) are only accessed as bytes, 326 * the temperature sensor is only accessed as words, and 327 * the temperature sensors are I2C. Thus, byte-swap the 328 * word. 329 */ 330 lword = htobe16(*(uint16_t *)buf); 331 } else { 332 /* For byte operations, the data goes in the LSB, and 333 * the MSB is a don't care. 334 */ 335 lword = *(uint8_t *)buf; 336 } 337 cmd_val |= lword; 338 } 339 340 /* Write the updated value to the control register first, to disable 341 * the hardware TSOD polling. 342 */ 343 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 344 sc->sc_regs->smb_cntl, cntl_val); 345 346 /* Poll on the BUSY bit in the status register until clear, or timeout. 347 * We just cleared the auto-poll bit, so we need to make sure the device 348 * is idle before issuing a command. We can safely timeout after 35 ms, 349 * as this is the maximum time the SMBus spec allows for a transaction. 350 */ 351 for (i = 4; i != 0; i--) { 352 stat_val = pci_conf_read(sc->sc_pci_chipset_tag, 353 sc->sc_pci_tag, sc->sc_regs->smb_stat); 354 if (! (stat_val & IMCSMB_STATUS_BUSY_BIT)) { 355 break; 356 } 357 delay(100); /* wait 10ms */ 358 } 359 360 if (i == 0) { 361 aprint_debug_dev(sc->sc_dev, 362 "transfer: timeout waiting for device to settle\n"); 363 } 364 365 /* Now that polling has stopped, we can write the command register. This 366 * starts the SMBus command. 367 */ 368 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 369 sc->sc_regs->smb_cmd, cmd_val); 370 371 /* Wait for WRITE_DATA_DONE/READ_DATA_VALID to be set, or timeout and 372 * fail. We wait up to 35ms. 373 */ 374 for (i = 35000; i != 0; i -= 10) 375 { 376 delay(10); 377 stat_val = pci_conf_read(sc->sc_pci_chipset_tag, 378 sc->sc_pci_tag, sc->sc_regs->smb_stat); 379 /* 380 * For a write, the bits holding the data contain the data 381 * being written. You would think that would cause the 382 * READ_DATA_VALID bit to be cleared, because the data bits 383 * no longer contain valid data from the most recent read 384 * operation. While that would be logical, that's not the 385 * case here: READ_DATA_VALID is only cleared when starting 386 * a read operation, and WRITE_DATA_DONE is only cleared 387 * when starting a write operation. 388 */ 389 if (I2C_OP_WRITE_P(op)) { 390 if (stat_val & IMCSMB_STATUS_WRITE_DATA_DONE) { 391 break; 392 } 393 } else { 394 if (stat_val & IMCSMB_STATUS_READ_DATA_VALID) { 395 break; 396 } 397 } 398 } 399 if (i == 0) { 400 rc = ETIMEDOUT; 401 aprint_debug_dev(sc->sc_dev, "transfer timeout\n"); 402 goto out; 403 } 404 405 /* It is generally the case that this bit indicates non-ACK, but it 406 * could also indicate other bus errors. There's no way to tell the 407 * difference. 408 */ 409 if (stat_val & IMCSMB_STATUS_BUS_ERROR_BIT) { 410 /* While it is not documented, empirically, SPD page-change 411 * commands (writes with DTI = 0x30) always complete with the 412 * error bit set. So, ignore it in those cases. 413 */ 414 if ((addr & 0x78) != 0x30) { 415 rc = ENODEV; 416 goto out; 417 } 418 } 419 420 /* For a read operation, copy the data out */ 421 if (I2C_OP_READ_P(op)) { 422 if (len == 2) { 423 /* The data is returned in bits [15:0]; as discussed 424 * above, byte-swap. 425 */ 426 lword = (uint16_t) (stat_val & 0xffff); 427 lword = htobe16(lword); 428 *(uint16_t *)buf = lword; 429 } else { 430 /* The data is returned in bits [7:0] */ 431 lbyte = (uint8_t) (stat_val & 0xff); 432 *(uint8_t *)buf = lbyte; 433 } 434 } 435 436 out: 437 /* Restore the original value of the control register. */ 438 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, 439 sc->sc_regs->smb_cntl, orig_cntl_val); 440 return rc; 441 }; 442 443 MODULE(MODULE_CLASS_DRIVER, imcsmb, "imc,iic"); 444 445 #ifdef _MODULE 446 #include "ioconf.c" 447 #endif 448 449 static int 450 imcsmb_modcmd(modcmd_t cmd, void *opaque) 451 { 452 int error = 0; 453 454 #ifdef _MODULE 455 switch (cmd) { 456 case MODULE_CMD_INIT: 457 error = config_init_component(cfdriver_ioconf_imcsmb, 458 cfattach_ioconf_imcsmb, cfdata_ioconf_imcsmb); 459 break; 460 case MODULE_CMD_FINI: 461 error = config_fini_component(cfdriver_ioconf_imcsmb, 462 cfattach_ioconf_imcsmb, cfdata_ioconf_imcsmb); 463 break; 464 default: 465 error = ENOTTY; 466 break; 467 } 468 #endif 469 470 return error; 471 } 472
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