pci_addr_fixup.c revision 1.2
1 /* $NetBSD: pci_addr_fixup.c,v 1.2 2008/12/18 12:18:20 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 UCHIYAMA Yasushi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pci_addr_fixup.c,v 1.2 2008/12/18 12:18:20 cegger Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/extent.h> 37 38 #include <machine/bus.h> 39 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcidevs.h> 43 44 #include <x86/pci/pci_addr_fixup.h> 45 46 struct pciaddr pciaddr; 47 48 static int pciaddrverbose = 0; 49 50 void pciaddr_resource_reserve(pci_chipset_tag_t, pcitag_t, void *context); 51 int pciaddr_do_resource_reserve(pci_chipset_tag_t, pcitag_t, int, 52 void *, int, bus_addr_t *, bus_size_t); 53 void pciaddr_resource_allocate(pci_chipset_tag_t, pcitag_t, void *context); 54 int pciaddr_do_resource_allocate(pci_chipset_tag_t, pcitag_t, int, 55 void *, int, bus_addr_t *, bus_size_t); 56 int device_is_agp(pci_chipset_tag_t, pcitag_t); 57 58 int device_is_agp(pci_chipset_tag_t, pcitag_t); 59 60 #define PCIADDR_MEM_START 0x0 61 #define PCIADDR_MEM_END 0xffffffff 62 #define PCIADDR_PORT_START 0x0 63 #define PCIADDR_PORT_END 0xffff 64 65 /* for ISA devices */ 66 #define PCIADDR_ISAPORT_RESERVE 0x5800 /* empirical value */ 67 #define PCIADDR_ISAMEM_RESERVE (16 * 1024 * 1024) 68 69 void 70 pci_addr_fixup(pci_chipset_tag_t pc, int maxbus) 71 { 72 extern paddr_t avail_end; 73 const char *verbose_header = 74 "[%s]-----------------------\n" 75 " device vendor product\n" 76 " register space address size\n" 77 "--------------------------------------------\n"; 78 const char *verbose_footer = 79 "--------------------------[%3d devices bogus]\n"; 80 const struct { 81 bus_addr_t start; 82 bus_size_t size; 83 const char *name; 84 } system_reserve [] = { 85 { 0xfec00000, 0x100000, "I/O APIC" }, 86 { 0xfee00000, 0x100000, "Local APIC" }, 87 { 0xfffe0000, 0x20000, "BIOS PROM" }, 88 { 0, 0, 0 }, /* terminator */ 89 }, *srp; 90 paddr_t start; 91 int error; 92 93 pciaddr.extent_mem = extent_create("PCI I/O memory space", 94 PCIADDR_MEM_START, 95 PCIADDR_MEM_END, 96 M_DEVBUF, 0, 0, EX_NOWAIT); 97 KASSERT(pciaddr.extent_mem); 98 pciaddr.extent_port = extent_create("PCI I/O port space", 99 PCIADDR_PORT_START, 100 PCIADDR_PORT_END, 101 M_DEVBUF, 0, 0, EX_NOWAIT); 102 KASSERT(pciaddr.extent_port); 103 104 /* 105 * 1. check & reserve system BIOS setting. 106 */ 107 aprint_debug(verbose_header, "System BIOS Setting"); 108 pci_device_foreach(pc, maxbus, pciaddr_resource_reserve, NULL); 109 aprint_debug(verbose_footer, pciaddr.nbogus); 110 111 /* 112 * 2. reserve non-PCI area. 113 */ 114 for (srp = system_reserve; srp->size; srp++) { 115 error = extent_alloc_region(pciaddr.extent_mem, srp->start, 116 srp->size, 117 EX_NOWAIT| EX_MALLOCOK); 118 if (error != 0) { 119 printf("WARNING: can't reserve area for %s.\n", 120 srp->name); 121 } 122 } 123 124 /* 125 * 3. determine allocation space 126 */ 127 start = x86_round_page(avail_end + 1); 128 if (start < PCIADDR_ISAMEM_RESERVE) 129 start = PCIADDR_ISAMEM_RESERVE; 130 pciaddr.mem_alloc_start = (start + 0x100000 + 1) & ~(0x100000 - 1); 131 pciaddr.port_alloc_start = PCIADDR_ISAPORT_RESERVE; 132 aprint_debug(" Physical memory end: 0x%08x\n PCI memory mapped I/O " 133 "space start: 0x%08x\n", (unsigned)avail_end, 134 (unsigned)pciaddr.mem_alloc_start); 135 136 if (pciaddr.nbogus == 0) 137 return; /* no need to fixup */ 138 139 /* 140 * 4. do fixup 141 */ 142 aprint_debug(verbose_header, "PCIBIOS fixup stage"); 143 pciaddr.nbogus = 0; 144 pci_device_foreach_min(pc, 0, maxbus, pciaddr_resource_allocate, NULL); 145 aprint_debug(verbose_footer, pciaddr.nbogus); 146 147 } 148 149 void 150 pciaddr_resource_reserve(pci_chipset_tag_t pc, pcitag_t tag, 151 void *context) 152 { 153 if (pciaddrverbose) 154 pciaddr_print_devid(pc, tag); 155 pciaddr_resource_manage(pc, tag, 156 pciaddr_do_resource_reserve, 157 &pciaddr); 158 } 159 160 void 161 pciaddr_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, 162 void *context) 163 { 164 if (pciaddrverbose) 165 pciaddr_print_devid(pc, tag); 166 pciaddr_resource_manage(pc, tag, 167 pciaddr_do_resource_allocate, 168 &pciaddr); 169 } 170 171 void 172 pciaddr_resource_manage(pci_chipset_tag_t pc, pcitag_t tag, 173 pciaddr_resource_manage_func_t func, void *ctx) 174 { 175 pcireg_t val, mask; 176 bus_addr_t addr; 177 bus_size_t size; 178 int error, useport, usemem, mapreg, type, reg_start, reg_end, width; 179 180 val = pci_conf_read(pc, tag, PCI_BHLC_REG); 181 switch (PCI_HDRTYPE_TYPE(val)) { 182 default: 183 printf("WARNING: unknown PCI device header."); 184 pciaddr.nbogus++; 185 return; 186 case 0: 187 reg_start = PCI_MAPREG_START; 188 reg_end = PCI_MAPREG_END; 189 break; 190 case 1: /* PCI-PCI bridge */ 191 reg_start = PCI_MAPREG_START; 192 reg_end = PCI_MAPREG_PPB_END; 193 break; 194 case 2: /* PCI-CardBus bridge */ 195 reg_start = PCI_MAPREG_START; 196 reg_end = PCI_MAPREG_PCB_END; 197 break; 198 } 199 error = useport = usemem = 0; 200 201 for (mapreg = reg_start; mapreg < reg_end; mapreg += width) { 202 /* inquire PCI device bus space requirement */ 203 val = pci_conf_read(pc, tag, mapreg); 204 pci_conf_write(pc, tag, mapreg, ~0); 205 206 mask = pci_conf_read(pc, tag, mapreg); 207 pci_conf_write(pc, tag, mapreg, val); 208 209 type = PCI_MAPREG_TYPE(val); 210 width = 4; 211 if (type == PCI_MAPREG_TYPE_MEM) { 212 if (PCI_MAPREG_MEM_TYPE(val) == 213 PCI_MAPREG_MEM_TYPE_64BIT) { 214 /* XXX We could examine the upper 32 bits 215 * XXX of the BAR here, but we are totally 216 * XXX unprepared to handle a non-zero value, 217 * XXX either here or anywhere else in 218 * XXX i386-land. 219 * XXX So just arrange to not look at the 220 * XXX upper 32 bits, lest we misinterpret 221 * XXX it as a 32-bit BAR set to zero. 222 */ 223 width = 8; 224 } 225 size = PCI_MAPREG_MEM_SIZE(mask); 226 } else { 227 size = PCI_MAPREG_IO_SIZE(mask); 228 } 229 addr = pciaddr_ioaddr(val); 230 231 if (!size) /* unused register */ 232 continue; 233 234 if (type == PCI_MAPREG_TYPE_MEM) 235 ++usemem; 236 else 237 ++useport; 238 239 /* reservation/allocation phase */ 240 error += (*func) (pc, tag, mapreg, ctx, type, &addr, size); 241 242 aprint_debug("\n\t%02xh %s 0x%08x 0x%08x", 243 mapreg, type ? "port" : "mem ", 244 (unsigned int)addr, (unsigned int)size); 245 } 246 247 /* enable/disable PCI device */ 248 val = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 249 if (error == 0) 250 val |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 251 PCI_COMMAND_MASTER_ENABLE); 252 else 253 val &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 254 PCI_COMMAND_MASTER_ENABLE); 255 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, val); 256 257 if (error) 258 pciaddr.nbogus++; 259 260 aprint_debug("\n\t\t[%s]\n", error ? "NG" : "OK"); 261 } 262 263 int 264 pciaddr_do_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, 265 int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size) 266 { 267 struct pciaddr *pciaddrmap = (struct pciaddr *)ctx; 268 bus_addr_t start; 269 int error; 270 struct extent *ex; 271 272 if (*addr) /* no need to allocate */ 273 return (0); 274 275 ex = (type == PCI_MAPREG_TYPE_MEM ? 276 pciaddrmap->extent_mem : pciaddrmap->extent_port); 277 278 /* XXX Don't allocate if device is AGP device to avoid conflict. */ 279 if (device_is_agp(pc, tag)) 280 return (0); 281 282 start = (type == PCI_MAPREG_TYPE_MEM ? 283 pciaddrmap->mem_alloc_start : pciaddrmap->port_alloc_start); 284 285 if (start < ex->ex_start || start + size - 1 >= ex->ex_end) { 286 aprint_debug("No available resources. fixup failed\n"); 287 return (1); 288 } 289 error = extent_alloc_subregion(ex, start, ex->ex_end, size, 290 size, 0, 291 EX_FAST|EX_NOWAIT|EX_MALLOCOK, addr); 292 if (error) { 293 aprint_debug("No available resources. fixup failed\n"); 294 return (1); 295 } 296 297 /* write new address to PCI device configuration header */ 298 pci_conf_write(pc, tag, mapreg, *addr); 299 /* check */ 300 if (!pciaddrverbose) 301 { 302 printf("pci_addr_fixup: "); 303 pciaddr_print_devid(pc, tag); 304 } 305 if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) { 306 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 307 printf("fixup failed. (new address=%#x)\n", (unsigned)*addr); 308 return (1); 309 } 310 if (!pciaddrverbose) 311 printf("new address 0x%08x\n", (unsigned)*addr); 312 313 return (0); 314 } 315 316 int 317 pciaddr_do_resource_reserve(pci_chipset_tag_t pc, pcitag_t tag, 318 int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size) 319 { 320 struct extent *ex; 321 struct pciaddr *pciaddrmap = (struct pciaddr *)ctx; 322 int error; 323 324 if (*addr == 0) 325 return (1); 326 327 ex = (type == PCI_MAPREG_TYPE_MEM ? 328 pciaddrmap->extent_mem : pciaddrmap->extent_port); 329 330 error = extent_alloc_region(ex, *addr, size, EX_NOWAIT| EX_MALLOCOK); 331 if (error) { 332 aprint_debug("Resource conflict.\n"); 333 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 334 return (1); 335 } 336 337 return (0); 338 } 339 340 bus_addr_t 341 pciaddr_ioaddr(uint32_t val) 342 { 343 return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM) 344 ? PCI_MAPREG_MEM_ADDR(val) 345 : PCI_MAPREG_IO_ADDR(val)); 346 } 347 348 void 349 pciaddr_print_devid(pci_chipset_tag_t pc, pcitag_t tag) 350 { 351 int bus, device, function; 352 pcireg_t id; 353 354 id = pci_conf_read(pc, tag, PCI_ID_REG); 355 pci_decompose_tag(pc, tag, &bus, &device, &function); 356 printf("%03d:%02d:%d 0x%04x 0x%04x ", bus, device, function, 357 PCI_VENDOR(id), PCI_PRODUCT(id)); 358 } 359 360 int 361 device_is_agp(pci_chipset_tag_t pc, pcitag_t tag) 362 { 363 pcireg_t class, status, rval; 364 int off; 365 366 /* Check AGP device. */ 367 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 368 if (PCI_CLASS(class) == PCI_CLASS_DISPLAY) { 369 status = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 370 if (status & PCI_STATUS_CAPLIST_SUPPORT) { 371 rval = pci_conf_read(pc, tag, PCI_CAPLISTPTR_REG); 372 for (off = PCI_CAPLIST_PTR(rval); 373 off != 0; 374 off = PCI_CAPLIST_NEXT(rval) ) { 375 rval = pci_conf_read(pc, tag, off); 376 if (PCI_CAPLIST_CAP(rval) == PCI_CAP_AGP) 377 return (1); 378 } 379 } 380 } 381 return (0); 382 } 383
Indexes created Tue Oct 14 08:09:56 GMT 2025