pci_machdep.c revision 1.1
1 /* $NetBSD: pci_machdep.c,v 1.1 2003/02/27 00:30:31 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Machine-specific functions for PCI autoconfiguration. 72 * 73 * On PCs, there are two methods of generating PCI configuration cycles. 74 * We try to detect the appropriate mechanism for this machine and set 75 * up a few function pointers to access the correct method directly. 76 * 77 * The configuration method can be hard-coded in the config file by 78 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 79 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.1 2003/02/27 00:30:31 fvdl Exp $"); 84 85 #include <sys/types.h> 86 #include <sys/param.h> 87 #include <sys/time.h> 88 #include <sys/systm.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/lock.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #define _X86_BUS_DMA_PRIVATE 96 #include <machine/bus.h> 97 98 #include <machine/pio.h> 99 #include <machine/intr.h> 100 101 #include <dev/isa/isavar.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcidevs.h> 105 106 #include "ioapic.h" 107 108 #if NIOAPIC > 0 109 #include <machine/i82093var.h> 110 #include <machine/mpbiosvar.h> 111 #endif 112 113 #include "opt_pci_conf_mode.h" 114 115 int pci_mode = -1; 116 117 struct simplelock pci_conf_slock = SIMPLELOCK_INITIALIZER; 118 119 #define PCI_CONF_LOCK(s) \ 120 do { \ 121 (s) = splhigh(); \ 122 simple_lock(&pci_conf_slock); \ 123 } while (0) 124 125 #define PCI_CONF_UNLOCK(s) \ 126 do { \ 127 simple_unlock(&pci_conf_slock); \ 128 splx((s)); \ 129 } while (0) 130 131 #define PCI_MODE1_ENABLE 0x80000000UL 132 #define PCI_MODE1_ADDRESS_REG 0x0cf8 133 #define PCI_MODE1_DATA_REG 0x0cfc 134 135 #define PCI_MODE2_ENABLE_REG 0x0cf8 136 #define PCI_MODE2_FORWARD_REG 0x0cfa 137 138 #define _m1tag(b, d, f) \ 139 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 140 #define _qe(bus, dev, fcn, vend, prod) \ 141 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 142 struct { 143 u_int32_t tag; 144 pcireg_t id; 145 } pcim1_quirk_tbl[] = { 146 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 147 /* XXX Triflex2 not tested */ 148 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 149 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 150 /* Triton needed for Connectix Virtual PC */ 151 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 152 /* Connectix Virtual PC 5 has a 440BX */ 153 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 154 {0, 0xffffffff} /* patchable */ 155 }; 156 #undef _m1tag 157 #undef _id 158 #undef _qe 159 160 /* 161 * PCI doesn't have any special needs; just use the generic versions 162 * of these functions. 163 */ 164 struct x86_bus_dma_tag pci_bus_dma_tag = { 165 0, /* _bounce_thresh */ 166 _bus_dmamap_create, 167 _bus_dmamap_destroy, 168 _bus_dmamap_load, 169 _bus_dmamap_load_mbuf, 170 _bus_dmamap_load_uio, 171 _bus_dmamap_load_raw, 172 _bus_dmamap_unload, 173 NULL, /* _dmamap_sync */ 174 _bus_dmamem_alloc, 175 _bus_dmamem_free, 176 _bus_dmamem_map, 177 _bus_dmamem_unmap, 178 _bus_dmamem_mmap, 179 }; 180 181 void 182 pci_attach_hook(parent, self, pba) 183 struct device *parent, *self; 184 struct pcibus_attach_args *pba; 185 { 186 187 if (pba->pba_bus == 0) 188 printf(": configuration mode %d", pci_mode); 189 } 190 191 int 192 pci_bus_maxdevs(pc, busno) 193 pci_chipset_tag_t pc; 194 int busno; 195 { 196 197 /* 198 * Bus number is irrelevant. If Configuration Mechanism 2 is in 199 * use, can only have devices 0-15 on any bus. If Configuration 200 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 201 * range). 202 */ 203 if (pci_mode == 2) 204 return (16); 205 else 206 return (32); 207 } 208 209 pcitag_t 210 pci_make_tag(pc, bus, device, function) 211 pci_chipset_tag_t pc; 212 int bus, device, function; 213 { 214 pcitag_t tag; 215 216 #ifndef PCI_CONF_MODE 217 switch (pci_mode) { 218 case 1: 219 goto mode1; 220 case 2: 221 goto mode2; 222 default: 223 panic("pci_make_tag: mode not configured"); 224 } 225 #endif 226 227 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 228 #ifndef PCI_CONF_MODE 229 mode1: 230 #endif 231 if (bus >= 256 || device >= 32 || function >= 8) 232 panic("pci_make_tag: bad request"); 233 234 tag.mode1 = PCI_MODE1_ENABLE | 235 (bus << 16) | (device << 11) | (function << 8); 236 return tag; 237 #endif 238 239 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 240 #ifndef PCI_CONF_MODE 241 mode2: 242 #endif 243 if (bus >= 256 || device >= 16 || function >= 8) 244 panic("pci_make_tag: bad request"); 245 246 tag.mode2.port = 0xc000 | (device << 8); 247 tag.mode2.enable = 0xf0 | (function << 1); 248 tag.mode2.forward = bus; 249 return tag; 250 #endif 251 } 252 253 void 254 pci_decompose_tag(pc, tag, bp, dp, fp) 255 pci_chipset_tag_t pc; 256 pcitag_t tag; 257 int *bp, *dp, *fp; 258 { 259 260 #ifndef PCI_CONF_MODE 261 switch (pci_mode) { 262 case 1: 263 goto mode1; 264 case 2: 265 goto mode2; 266 default: 267 panic("pci_decompose_tag: mode not configured"); 268 } 269 #endif 270 271 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 272 #ifndef PCI_CONF_MODE 273 mode1: 274 #endif 275 if (bp != NULL) 276 *bp = (tag.mode1 >> 16) & 0xff; 277 if (dp != NULL) 278 *dp = (tag.mode1 >> 11) & 0x1f; 279 if (fp != NULL) 280 *fp = (tag.mode1 >> 8) & 0x7; 281 return; 282 #endif 283 284 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 285 #ifndef PCI_CONF_MODE 286 mode2: 287 #endif 288 if (bp != NULL) 289 *bp = tag.mode2.forward & 0xff; 290 if (dp != NULL) 291 *dp = (tag.mode2.port >> 8) & 0xf; 292 if (fp != NULL) 293 *fp = (tag.mode2.enable >> 1) & 0x7; 294 #endif 295 } 296 297 pcireg_t 298 pci_conf_read(pc, tag, reg) 299 pci_chipset_tag_t pc; 300 pcitag_t tag; 301 int reg; 302 { 303 pcireg_t data; 304 int s; 305 306 #ifndef PCI_CONF_MODE 307 switch (pci_mode) { 308 case 1: 309 goto mode1; 310 case 2: 311 goto mode2; 312 default: 313 panic("pci_conf_read: mode not configured"); 314 } 315 #endif 316 317 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 318 #ifndef PCI_CONF_MODE 319 mode1: 320 #endif 321 PCI_CONF_LOCK(s); 322 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 323 data = inl(PCI_MODE1_DATA_REG); 324 outl(PCI_MODE1_ADDRESS_REG, 0); 325 PCI_CONF_UNLOCK(s); 326 return data; 327 #endif 328 329 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 330 #ifndef PCI_CONF_MODE 331 mode2: 332 #endif 333 PCI_CONF_LOCK(s); 334 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 335 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 336 data = inl(tag.mode2.port | reg); 337 outb(PCI_MODE2_ENABLE_REG, 0); 338 PCI_CONF_UNLOCK(s); 339 return data; 340 #endif 341 } 342 343 void 344 pci_conf_write(pc, tag, reg, data) 345 pci_chipset_tag_t pc; 346 pcitag_t tag; 347 int reg; 348 pcireg_t data; 349 { 350 int s; 351 352 #ifndef PCI_CONF_MODE 353 switch (pci_mode) { 354 case 1: 355 goto mode1; 356 case 2: 357 goto mode2; 358 default: 359 panic("pci_conf_write: mode not configured"); 360 } 361 #endif 362 363 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 364 #ifndef PCI_CONF_MODE 365 mode1: 366 #endif 367 PCI_CONF_LOCK(s); 368 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 369 outl(PCI_MODE1_DATA_REG, data); 370 outl(PCI_MODE1_ADDRESS_REG, 0); 371 PCI_CONF_UNLOCK(s); 372 return; 373 #endif 374 375 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 376 #ifndef PCI_CONF_MODE 377 mode2: 378 #endif 379 PCI_CONF_LOCK(s); 380 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 381 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 382 outl(tag.mode2.port | reg, data); 383 outb(PCI_MODE2_ENABLE_REG, 0); 384 PCI_CONF_UNLOCK(s); 385 #endif 386 } 387 388 int 389 pci_mode_detect() 390 { 391 392 #ifdef PCI_CONF_MODE 393 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 394 return (pci_mode = PCI_CONF_MODE); 395 #else 396 #error Invalid PCI configuration mode. 397 #endif 398 #else 399 u_int32_t sav, val; 400 int i; 401 pcireg_t idreg; 402 403 if (pci_mode != -1) 404 return pci_mode; 405 406 /* 407 * We try to divine which configuration mode the host bridge wants. 408 */ 409 410 sav = inl(PCI_MODE1_ADDRESS_REG); 411 412 pci_mode = 1; /* assume this for now */ 413 /* 414 * catch some known buggy implementations of mode 1 415 */ 416 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 417 i++) { 418 pcitag_t t; 419 420 if (!pcim1_quirk_tbl[i].tag) 421 break; 422 t.mode1 = pcim1_quirk_tbl[i].tag; 423 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 424 if (idreg == pcim1_quirk_tbl[i].id) { 425 #ifdef DEBUG 426 printf("known mode 1 PCI chipset (%08x)\n", 427 idreg); 428 #endif 429 return (pci_mode); 430 } 431 } 432 433 /* 434 * Strong check for standard compliant mode 1: 435 * 1. bit 31 ("enable") can be set 436 * 2. byte/word access does not affect register 437 */ 438 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 439 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 440 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 441 val = inl(PCI_MODE1_ADDRESS_REG); 442 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 443 #ifdef DEBUG 444 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 445 val); 446 #endif 447 goto not1; 448 } 449 outl(PCI_MODE1_ADDRESS_REG, 0); 450 val = inl(PCI_MODE1_ADDRESS_REG); 451 if ((val & 0x80fffffc) != 0) 452 goto not1; 453 return (pci_mode); 454 not1: 455 outl(PCI_MODE1_ADDRESS_REG, sav); 456 457 /* 458 * This mode 2 check is quite weak (and known to give false 459 * positives on some Compaq machines). 460 * However, this doesn't matter, because this is the 461 * last test, and simply no PCI devices will be found if 462 * this happens. 463 */ 464 outb(PCI_MODE2_ENABLE_REG, 0); 465 outb(PCI_MODE2_FORWARD_REG, 0); 466 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 467 inb(PCI_MODE2_FORWARD_REG) != 0) 468 goto not2; 469 return (pci_mode = 2); 470 not2: 471 472 return (pci_mode = 0); 473 #endif 474 } 475 476 int 477 pci_intr_map(pa, ihp) 478 struct pci_attach_args *pa; 479 pci_intr_handle_t *ihp; 480 { 481 int pin = pa->pa_intrpin; 482 int line = pa->pa_intrline; 483 #if NIOAPIC > 0 484 int rawpin = pa->pa_rawintrpin; 485 pci_chipset_tag_t pc = pa->pa_pc; 486 int bus, dev, func; 487 #endif 488 489 if (pin == 0) { 490 /* No IRQ used. */ 491 goto bad; 492 } 493 494 if (pin > PCI_INTERRUPT_PIN_MAX) { 495 printf("pci_intr_map: bad interrupt pin %d\n", pin); 496 goto bad; 497 } 498 499 #if NIOAPIC > 0 500 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 501 if (mp_busses != NULL) { 502 if (intr_find_mpmapping(bus, (dev<<2)|(rawpin-1), ihp) == 0) { 503 *ihp |= line; 504 return 0; 505 } 506 /* 507 * No explicit PCI mapping found. This is not fatal, 508 * we'll try the ISA (or possibly EISA) mappings next. 509 */ 510 } 511 #endif 512 513 /* 514 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 515 * `unknown' or `no connection' on a PC. We assume that a device with 516 * `no connection' either doesn't have an interrupt (in which case the 517 * pin number should be 0, and would have been noticed above), or 518 * wasn't configured by the BIOS (in which case we punt, since there's 519 * no real way we can know how the interrupt lines are mapped in the 520 * hardware). 521 * 522 * XXX 523 * Since IRQ 0 is only used by the clock, and we can't actually be sure 524 * that the BIOS did its job, we also recognize that as meaning that 525 * the BIOS has not configured the device. 526 */ 527 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 528 printf("pci_intr_map: no mapping for pin %c (line=%02x)\n", 529 '@' + pin, line); 530 goto bad; 531 } else { 532 if (line >= NUM_LEGACY_IRQS) { 533 printf("pci_intr_map: bad interrupt line %d\n", line); 534 goto bad; 535 } 536 if (line == 2) { 537 printf("pci_intr_map: changed line 2 to line 9\n"); 538 line = 9; 539 } 540 } 541 #if NIOAPIC > 0 542 if (mp_busses != NULL) { 543 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 544 *ihp |= line; 545 return 0; 546 } 547 #if NEISA > 0 548 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 549 *ihp |= line; 550 return 0; 551 } 552 #endif 553 printf("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 554 bus, dev, func, pin, line); 555 printf("pci_intr_map: no MP mapping found\n"); 556 } 557 #endif 558 559 *ihp = line; 560 return 0; 561 562 bad: 563 *ihp = -1; 564 return 1; 565 } 566 567 const char * 568 pci_intr_string(pc, ih) 569 pci_chipset_tag_t pc; 570 pci_intr_handle_t ih; 571 { 572 static char irqstr[64]; 573 574 if (ih == 0) 575 panic("pci_intr_string: bogus handle 0x%x", ih); 576 577 578 #if NIOAPIC > 0 579 if (ih & APIC_INT_VIA_APIC) 580 sprintf(irqstr, "apic %d int %d (irq %d)", 581 APIC_IRQ_APIC(ih), 582 APIC_IRQ_PIN(ih), 583 ih&0xff); 584 else 585 sprintf(irqstr, "irq %d", ih&0xff); 586 #else 587 588 sprintf(irqstr, "irq %d", ih&0xff); 589 #endif 590 return (irqstr); 591 592 } 593 594 const struct evcnt * 595 pci_intr_evcnt(pc, ih) 596 pci_chipset_tag_t pc; 597 pci_intr_handle_t ih; 598 { 599 600 /* XXX for now, no evcnt parent reported */ 601 return NULL; 602 } 603 604 void * 605 pci_intr_establish(pc, ih, level, func, arg) 606 pci_chipset_tag_t pc; 607 pci_intr_handle_t ih; 608 int level, (*func) __P((void *)); 609 void *arg; 610 { 611 int pin, irq; 612 struct pic *pic; 613 614 pic = &i8259_pic; 615 pin = irq = ih; 616 617 #if NIOAPIC > 0 618 if (ih & APIC_INT_VIA_APIC) { 619 pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih)); 620 if (pic == NULL) { 621 printf("pci_intr_establish: bad ioapic %d\n", 622 APIC_IRQ_APIC(ih)); 623 return NULL; 624 } 625 pin = APIC_IRQ_PIN(ih); 626 irq = APIC_IRQ_LEGACY_IRQ(ih); 627 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 628 irq = -1; 629 } 630 #endif 631 632 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg); 633 } 634 635 void 636 pci_intr_disestablish(pc, cookie) 637 pci_chipset_tag_t pc; 638 void *cookie; 639 { 640 641 intr_disestablish(cookie); 642 } 643 644 /* 645 * Determine which flags should be passed to the primary PCI bus's 646 * autoconfiguration node. We use this to detect broken chipsets 647 * which cannot safely use memory-mapped device access. 648 */ 649 int 650 pci_bus_flags() 651 { 652 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 653 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 654 int device, maxndevs; 655 pcitag_t tag; 656 pcireg_t id; 657 658 maxndevs = pci_bus_maxdevs(NULL, 0); 659 660 for (device = 0; device < maxndevs; device++) { 661 tag = pci_make_tag(NULL, 0, device, 0); 662 id = pci_conf_read(NULL, tag, PCI_ID_REG); 663 664 /* Invalid vendor ID value? */ 665 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 666 continue; 667 /* XXX Not invalid, but we've done this ~forever. */ 668 if (PCI_VENDOR(id) == 0) 669 continue; 670 671 switch (PCI_VENDOR(id)) { 672 case PCI_VENDOR_SIS: 673 switch (PCI_PRODUCT(id)) { 674 case PCI_PRODUCT_SIS_85C496: 675 goto disable_mem; 676 } 677 break; 678 } 679 } 680 681 return (rval); 682 683 disable_mem: 684 printf("Warning: broken PCI-Host bridge detected; " 685 "disabling memory-mapped access\n"); 686 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 687 PCI_FLAGS_MWI_OKAY); 688 return (rval); 689 } 690
Indexes created Thu Sep 25 16:09:42 GMT 2025