pci_machdep.c revision 1.10
1 /* $NetBSD: pci_machdep.c,v 1.10 2005/04/16 07:53:35 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Machine-specific functions for PCI autoconfiguration. 72 * 73 * On PCs, there are two methods of generating PCI configuration cycles. 74 * We try to detect the appropriate mechanism for this machine and set 75 * up a few function pointers to access the correct method directly. 76 * 77 * The configuration method can be hard-coded in the config file by 78 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 79 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.10 2005/04/16 07:53:35 yamt Exp $"); 84 85 #include <sys/types.h> 86 #include <sys/param.h> 87 #include <sys/time.h> 88 #include <sys/systm.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/lock.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <machine/bus.h> 96 #include <machine/bus_private.h> 97 98 #include <machine/pio.h> 99 #include <machine/intr.h> 100 101 #include <dev/isa/isareg.h> 102 #include <dev/isa/isavar.h> 103 #include <dev/pci/pcivar.h> 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcidevs.h> 106 107 #include "ioapic.h" 108 #include "eisa.h" 109 #include "opt_mpbios.h" 110 #include "opt_mpacpi.h" 111 112 #if NIOAPIC > 0 113 #include <machine/i82093var.h> 114 #include <machine/mpbiosvar.h> 115 #include <machine/pic.h> 116 #endif 117 118 #ifdef MPBIOS 119 #include <machine/mpbiosvar.h> 120 #endif 121 122 #ifdef MPACPI 123 #include <machine/mpacpi.h> 124 #endif 125 126 #include "opt_pci_conf_mode.h" 127 128 int pci_mode = -1; 129 130 struct simplelock pci_conf_slock = SIMPLELOCK_INITIALIZER; 131 132 #define PCI_CONF_LOCK(s) \ 133 do { \ 134 (s) = splhigh(); \ 135 simple_lock(&pci_conf_slock); \ 136 } while (0) 137 138 #define PCI_CONF_UNLOCK(s) \ 139 do { \ 140 simple_unlock(&pci_conf_slock); \ 141 splx((s)); \ 142 } while (0) 143 144 #define PCI_MODE1_ENABLE 0x80000000UL 145 #define PCI_MODE1_ADDRESS_REG 0x0cf8 146 #define PCI_MODE1_DATA_REG 0x0cfc 147 148 #define PCI_MODE2_ENABLE_REG 0x0cf8 149 #define PCI_MODE2_FORWARD_REG 0x0cfa 150 151 #define _m1tag(b, d, f) \ 152 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 153 #define _qe(bus, dev, fcn, vend, prod) \ 154 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 155 struct { 156 u_int32_t tag; 157 pcireg_t id; 158 } pcim1_quirk_tbl[] = { 159 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 160 /* XXX Triflex2 not tested */ 161 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 162 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 163 /* Triton needed for Connectix Virtual PC */ 164 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 165 /* Connectix Virtual PC 5 has a 440BX */ 166 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 167 {0, 0xffffffff} /* patchable */ 168 }; 169 #undef _m1tag 170 #undef _id 171 #undef _qe 172 173 /* 174 * PCI doesn't have any special needs; just use the generic versions 175 * of these functions. 176 */ 177 struct x86_bus_dma_tag pci_bus_dma_tag = { 178 #if defined(_LP64) || defined(PAE) 179 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 180 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 181 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 182 #else 183 0, 184 0, 185 0, 186 #endif 187 NULL, /* _may_bounce */ 188 _bus_dmamap_create, 189 _bus_dmamap_destroy, 190 _bus_dmamap_load, 191 _bus_dmamap_load_mbuf, 192 _bus_dmamap_load_uio, 193 _bus_dmamap_load_raw, 194 _bus_dmamap_unload, 195 #if defined(_LP64) || defined(PAE) 196 _bus_dmamap_sync, 197 #else 198 NULL, 199 #endif 200 _bus_dmamem_alloc, 201 _bus_dmamem_free, 202 _bus_dmamem_map, 203 _bus_dmamem_unmap, 204 _bus_dmamem_mmap, 205 }; 206 207 #ifdef _LP64 208 struct x86_bus_dma_tag pci_bus_dma64_tag = { 209 0, 210 0, 211 0, 212 NULL, /* _may_bounce */ 213 _bus_dmamap_create, 214 _bus_dmamap_destroy, 215 _bus_dmamap_load, 216 _bus_dmamap_load_mbuf, 217 _bus_dmamap_load_uio, 218 _bus_dmamap_load_raw, 219 _bus_dmamap_unload, 220 NULL, 221 _bus_dmamem_alloc, 222 _bus_dmamem_free, 223 _bus_dmamem_map, 224 _bus_dmamem_unmap, 225 _bus_dmamem_mmap, 226 }; 227 #endif 228 229 void 230 pci_attach_hook(parent, self, pba) 231 struct device *parent, *self; 232 struct pcibus_attach_args *pba; 233 { 234 235 if (pba->pba_bus == 0) 236 printf(": configuration mode %d", pci_mode); 237 #ifdef MPBIOS 238 mpbios_pci_attach_hook(parent, self, pba); 239 #endif 240 #ifdef MPACPI 241 mpacpi_pci_attach_hook(parent, self, pba); 242 #endif 243 } 244 245 int 246 pci_bus_maxdevs(pc, busno) 247 pci_chipset_tag_t pc; 248 int busno; 249 { 250 251 /* 252 * Bus number is irrelevant. If Configuration Mechanism 2 is in 253 * use, can only have devices 0-15 on any bus. If Configuration 254 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 255 * range). 256 */ 257 if (pci_mode == 2) 258 return (16); 259 else 260 return (32); 261 } 262 263 pcitag_t 264 pci_make_tag(pc, bus, device, function) 265 pci_chipset_tag_t pc; 266 int bus, device, function; 267 { 268 pcitag_t tag; 269 270 #ifndef PCI_CONF_MODE 271 switch (pci_mode) { 272 case 1: 273 goto mode1; 274 case 2: 275 goto mode2; 276 default: 277 panic("pci_make_tag: mode not configured"); 278 } 279 #endif 280 281 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 282 #ifndef PCI_CONF_MODE 283 mode1: 284 #endif 285 if (bus >= 256 || device >= 32 || function >= 8) 286 panic("pci_make_tag: bad request"); 287 288 tag.mode1 = PCI_MODE1_ENABLE | 289 (bus << 16) | (device << 11) | (function << 8); 290 return tag; 291 #endif 292 293 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 294 #ifndef PCI_CONF_MODE 295 mode2: 296 #endif 297 if (bus >= 256 || device >= 16 || function >= 8) 298 panic("pci_make_tag: bad request"); 299 300 tag.mode2.port = 0xc000 | (device << 8); 301 tag.mode2.enable = 0xf0 | (function << 1); 302 tag.mode2.forward = bus; 303 return tag; 304 #endif 305 } 306 307 void 308 pci_decompose_tag(pc, tag, bp, dp, fp) 309 pci_chipset_tag_t pc; 310 pcitag_t tag; 311 int *bp, *dp, *fp; 312 { 313 314 #ifndef PCI_CONF_MODE 315 switch (pci_mode) { 316 case 1: 317 goto mode1; 318 case 2: 319 goto mode2; 320 default: 321 panic("pci_decompose_tag: mode not configured"); 322 } 323 #endif 324 325 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 326 #ifndef PCI_CONF_MODE 327 mode1: 328 #endif 329 if (bp != NULL) 330 *bp = (tag.mode1 >> 16) & 0xff; 331 if (dp != NULL) 332 *dp = (tag.mode1 >> 11) & 0x1f; 333 if (fp != NULL) 334 *fp = (tag.mode1 >> 8) & 0x7; 335 return; 336 #endif 337 338 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 339 #ifndef PCI_CONF_MODE 340 mode2: 341 #endif 342 if (bp != NULL) 343 *bp = tag.mode2.forward & 0xff; 344 if (dp != NULL) 345 *dp = (tag.mode2.port >> 8) & 0xf; 346 if (fp != NULL) 347 *fp = (tag.mode2.enable >> 1) & 0x7; 348 #endif 349 } 350 351 pcireg_t 352 pci_conf_read(pc, tag, reg) 353 pci_chipset_tag_t pc; 354 pcitag_t tag; 355 int reg; 356 { 357 pcireg_t data; 358 int s; 359 360 #ifndef PCI_CONF_MODE 361 switch (pci_mode) { 362 case 1: 363 goto mode1; 364 case 2: 365 goto mode2; 366 default: 367 panic("pci_conf_read: mode not configured"); 368 } 369 #endif 370 371 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 372 #ifndef PCI_CONF_MODE 373 mode1: 374 #endif 375 PCI_CONF_LOCK(s); 376 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 377 data = inl(PCI_MODE1_DATA_REG); 378 outl(PCI_MODE1_ADDRESS_REG, 0); 379 PCI_CONF_UNLOCK(s); 380 return data; 381 #endif 382 383 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 384 #ifndef PCI_CONF_MODE 385 mode2: 386 #endif 387 PCI_CONF_LOCK(s); 388 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 389 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 390 data = inl(tag.mode2.port | reg); 391 outb(PCI_MODE2_ENABLE_REG, 0); 392 PCI_CONF_UNLOCK(s); 393 return data; 394 #endif 395 } 396 397 void 398 pci_conf_write(pc, tag, reg, data) 399 pci_chipset_tag_t pc; 400 pcitag_t tag; 401 int reg; 402 pcireg_t data; 403 { 404 int s; 405 406 #ifndef PCI_CONF_MODE 407 switch (pci_mode) { 408 case 1: 409 goto mode1; 410 case 2: 411 goto mode2; 412 default: 413 panic("pci_conf_write: mode not configured"); 414 } 415 #endif 416 417 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 418 #ifndef PCI_CONF_MODE 419 mode1: 420 #endif 421 PCI_CONF_LOCK(s); 422 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 423 outl(PCI_MODE1_DATA_REG, data); 424 outl(PCI_MODE1_ADDRESS_REG, 0); 425 PCI_CONF_UNLOCK(s); 426 return; 427 #endif 428 429 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 430 #ifndef PCI_CONF_MODE 431 mode2: 432 #endif 433 PCI_CONF_LOCK(s); 434 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 435 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 436 outl(tag.mode2.port | reg, data); 437 outb(PCI_MODE2_ENABLE_REG, 0); 438 PCI_CONF_UNLOCK(s); 439 #endif 440 } 441 442 int 443 pci_mode_detect() 444 { 445 446 #ifdef PCI_CONF_MODE 447 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 448 return (pci_mode = PCI_CONF_MODE); 449 #else 450 #error Invalid PCI configuration mode. 451 #endif 452 #else 453 u_int32_t sav, val; 454 int i; 455 pcireg_t idreg; 456 457 if (pci_mode != -1) 458 return pci_mode; 459 460 /* 461 * We try to divine which configuration mode the host bridge wants. 462 */ 463 464 sav = inl(PCI_MODE1_ADDRESS_REG); 465 466 pci_mode = 1; /* assume this for now */ 467 /* 468 * catch some known buggy implementations of mode 1 469 */ 470 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 471 i++) { 472 pcitag_t t; 473 474 if (!pcim1_quirk_tbl[i].tag) 475 break; 476 t.mode1 = pcim1_quirk_tbl[i].tag; 477 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 478 if (idreg == pcim1_quirk_tbl[i].id) { 479 #ifdef DEBUG 480 printf("known mode 1 PCI chipset (%08x)\n", 481 idreg); 482 #endif 483 return (pci_mode); 484 } 485 } 486 487 /* 488 * Strong check for standard compliant mode 1: 489 * 1. bit 31 ("enable") can be set 490 * 2. byte/word access does not affect register 491 */ 492 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 493 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 494 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 495 val = inl(PCI_MODE1_ADDRESS_REG); 496 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 497 #ifdef DEBUG 498 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 499 val); 500 #endif 501 goto not1; 502 } 503 outl(PCI_MODE1_ADDRESS_REG, 0); 504 val = inl(PCI_MODE1_ADDRESS_REG); 505 if ((val & 0x80fffffc) != 0) 506 goto not1; 507 return (pci_mode); 508 not1: 509 outl(PCI_MODE1_ADDRESS_REG, sav); 510 511 /* 512 * This mode 2 check is quite weak (and known to give false 513 * positives on some Compaq machines). 514 * However, this doesn't matter, because this is the 515 * last test, and simply no PCI devices will be found if 516 * this happens. 517 */ 518 outb(PCI_MODE2_ENABLE_REG, 0); 519 outb(PCI_MODE2_FORWARD_REG, 0); 520 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 521 inb(PCI_MODE2_FORWARD_REG) != 0) 522 goto not2; 523 return (pci_mode = 2); 524 not2: 525 526 return (pci_mode = 0); 527 #endif 528 } 529 530 int 531 pci_intr_map(pa, ihp) 532 struct pci_attach_args *pa; 533 pci_intr_handle_t *ihp; 534 { 535 int pin = pa->pa_intrpin; 536 int line = pa->pa_intrline; 537 #if NIOAPIC > 0 538 int rawpin = pa->pa_rawintrpin; 539 pci_chipset_tag_t pc = pa->pa_pc; 540 int bus, dev, func; 541 #endif 542 543 if (pin == 0) { 544 /* No IRQ used. */ 545 goto bad; 546 } 547 548 if (pin > PCI_INTERRUPT_PIN_MAX) { 549 printf("pci_intr_map: bad interrupt pin %d\n", pin); 550 goto bad; 551 } 552 553 #if NIOAPIC > 0 554 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 555 if (mp_busses != NULL) { 556 if (intr_find_mpmapping(bus, (dev<<2)|(rawpin-1), ihp) == 0) { 557 *ihp |= line; 558 return 0; 559 } 560 /* 561 * No explicit PCI mapping found. This is not fatal, 562 * we'll try the ISA (or possibly EISA) mappings next. 563 */ 564 } 565 #endif 566 567 /* 568 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 569 * `unknown' or `no connection' on a PC. We assume that a device with 570 * `no connection' either doesn't have an interrupt (in which case the 571 * pin number should be 0, and would have been noticed above), or 572 * wasn't configured by the BIOS (in which case we punt, since there's 573 * no real way we can know how the interrupt lines are mapped in the 574 * hardware). 575 * 576 * XXX 577 * Since IRQ 0 is only used by the clock, and we can't actually be sure 578 * that the BIOS did its job, we also recognize that as meaning that 579 * the BIOS has not configured the device. 580 */ 581 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 582 printf("pci_intr_map: no mapping for pin %c (line=%02x)\n", 583 '@' + pin, line); 584 goto bad; 585 } else { 586 if (line >= NUM_LEGACY_IRQS) { 587 printf("pci_intr_map: bad interrupt line %d\n", line); 588 goto bad; 589 } 590 if (line == 2) { 591 printf("pci_intr_map: changed line 2 to line 9\n"); 592 line = 9; 593 } 594 } 595 #if NIOAPIC > 0 596 if (mp_busses != NULL) { 597 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 598 *ihp |= line; 599 return 0; 600 } 601 #if NEISA > 0 602 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 603 *ihp |= line; 604 return 0; 605 } 606 #endif 607 printf("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 608 bus, dev, func, pin, line); 609 printf("pci_intr_map: no MP mapping found\n"); 610 } 611 #endif 612 613 *ihp = line; 614 return 0; 615 616 bad: 617 *ihp = -1; 618 return 1; 619 } 620 621 const char * 622 pci_intr_string(pc, ih) 623 pci_chipset_tag_t pc; 624 pci_intr_handle_t ih; 625 { 626 return intr_string(ih); 627 } 628 629 630 const struct evcnt * 631 pci_intr_evcnt(pc, ih) 632 pci_chipset_tag_t pc; 633 pci_intr_handle_t ih; 634 { 635 636 /* XXX for now, no evcnt parent reported */ 637 return NULL; 638 } 639 640 void * 641 pci_intr_establish(pc, ih, level, func, arg) 642 pci_chipset_tag_t pc; 643 pci_intr_handle_t ih; 644 int level, (*func) __P((void *)); 645 void *arg; 646 { 647 int pin, irq; 648 struct pic *pic; 649 650 pic = &i8259_pic; 651 pin = irq = ih; 652 653 #if NIOAPIC > 0 654 if (ih & APIC_INT_VIA_APIC) { 655 pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih)); 656 if (pic == NULL) { 657 printf("pci_intr_establish: bad ioapic %d\n", 658 APIC_IRQ_APIC(ih)); 659 return NULL; 660 } 661 pin = APIC_IRQ_PIN(ih); 662 irq = APIC_IRQ_LEGACY_IRQ(ih); 663 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 664 irq = -1; 665 } 666 #endif 667 668 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg); 669 } 670 671 void 672 pci_intr_disestablish(pc, cookie) 673 pci_chipset_tag_t pc; 674 void *cookie; 675 { 676 677 intr_disestablish(cookie); 678 } 679 680 /* 681 * Determine which flags should be passed to the primary PCI bus's 682 * autoconfiguration node. We use this to detect broken chipsets 683 * which cannot safely use memory-mapped device access. 684 */ 685 int 686 pci_bus_flags() 687 { 688 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 689 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 690 int device, maxndevs; 691 pcitag_t tag; 692 pcireg_t id; 693 694 maxndevs = pci_bus_maxdevs(NULL, 0); 695 696 for (device = 0; device < maxndevs; device++) { 697 tag = pci_make_tag(NULL, 0, device, 0); 698 id = pci_conf_read(NULL, tag, PCI_ID_REG); 699 700 /* Invalid vendor ID value? */ 701 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 702 continue; 703 /* XXX Not invalid, but we've done this ~forever. */ 704 if (PCI_VENDOR(id) == 0) 705 continue; 706 707 switch (PCI_VENDOR(id)) { 708 case PCI_VENDOR_SIS: 709 switch (PCI_PRODUCT(id)) { 710 case PCI_PRODUCT_SIS_85C496: 711 goto disable_mem; 712 } 713 break; 714 } 715 } 716 717 return (rval); 718 719 disable_mem: 720 printf("Warning: broken PCI-Host bridge detected; " 721 "disabling memory-mapped access\n"); 722 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 723 PCI_FLAGS_MWI_OKAY); 724 return (rval); 725 } 726
Indexes created Wed Sep 24 22:09:59 GMT 2025