pci_machdep.c revision 1.11
1 /* $NetBSD: pci_machdep.c,v 1.11 2005/06/20 11:04:15 sekiya Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Machine-specific functions for PCI autoconfiguration. 72 * 73 * On PCs, there are two methods of generating PCI configuration cycles. 74 * We try to detect the appropriate mechanism for this machine and set 75 * up a few function pointers to access the correct method directly. 76 * 77 * The configuration method can be hard-coded in the config file by 78 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 79 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.11 2005/06/20 11:04:15 sekiya Exp $"); 84 85 #include <sys/types.h> 86 #include <sys/param.h> 87 #include <sys/time.h> 88 #include <sys/systm.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/lock.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <machine/bus.h> 96 #include <machine/bus_private.h> 97 98 #include <machine/pio.h> 99 #include <machine/intr.h> 100 101 #include <dev/isa/isareg.h> 102 #include <dev/isa/isavar.h> 103 #include <dev/pci/pcivar.h> 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcidevs.h> 106 107 #include "ioapic.h" 108 #include "eisa.h" 109 #include "opt_mpbios.h" 110 #include "opt_mpacpi.h" 111 112 #if NIOAPIC > 0 113 #include <machine/i82093var.h> 114 #include <machine/mpbiosvar.h> 115 #include <machine/pic.h> 116 #endif 117 118 #ifdef MPBIOS 119 #include <machine/mpbiosvar.h> 120 #endif 121 122 #ifdef MPACPI 123 #include <machine/mpacpi.h> 124 #endif 125 126 #include "opt_pci_conf_mode.h" 127 128 int pci_mode = -1; 129 130 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 131 struct pci_bridge_hook_arg { 132 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 133 void *arg; 134 }; 135 136 137 struct simplelock pci_conf_slock = SIMPLELOCK_INITIALIZER; 138 139 #define PCI_CONF_LOCK(s) \ 140 do { \ 141 (s) = splhigh(); \ 142 simple_lock(&pci_conf_slock); \ 143 } while (0) 144 145 #define PCI_CONF_UNLOCK(s) \ 146 do { \ 147 simple_unlock(&pci_conf_slock); \ 148 splx((s)); \ 149 } while (0) 150 151 #define PCI_MODE1_ENABLE 0x80000000UL 152 #define PCI_MODE1_ADDRESS_REG 0x0cf8 153 #define PCI_MODE1_DATA_REG 0x0cfc 154 155 #define PCI_MODE2_ENABLE_REG 0x0cf8 156 #define PCI_MODE2_FORWARD_REG 0x0cfa 157 158 #define _m1tag(b, d, f) \ 159 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 160 #define _qe(bus, dev, fcn, vend, prod) \ 161 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 162 struct { 163 u_int32_t tag; 164 pcireg_t id; 165 } pcim1_quirk_tbl[] = { 166 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 167 /* XXX Triflex2 not tested */ 168 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 169 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 170 /* Triton needed for Connectix Virtual PC */ 171 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 172 /* Connectix Virtual PC 5 has a 440BX */ 173 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 174 {0, 0xffffffff} /* patchable */ 175 }; 176 #undef _m1tag 177 #undef _id 178 #undef _qe 179 180 /* 181 * PCI doesn't have any special needs; just use the generic versions 182 * of these functions. 183 */ 184 struct x86_bus_dma_tag pci_bus_dma_tag = { 185 #if defined(_LP64) || defined(PAE) 186 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 187 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 188 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 189 #else 190 0, 191 0, 192 0, 193 #endif 194 NULL, /* _may_bounce */ 195 _bus_dmamap_create, 196 _bus_dmamap_destroy, 197 _bus_dmamap_load, 198 _bus_dmamap_load_mbuf, 199 _bus_dmamap_load_uio, 200 _bus_dmamap_load_raw, 201 _bus_dmamap_unload, 202 #if defined(_LP64) || defined(PAE) 203 _bus_dmamap_sync, 204 #else 205 NULL, 206 #endif 207 _bus_dmamem_alloc, 208 _bus_dmamem_free, 209 _bus_dmamem_map, 210 _bus_dmamem_unmap, 211 _bus_dmamem_mmap, 212 }; 213 214 #ifdef _LP64 215 struct x86_bus_dma_tag pci_bus_dma64_tag = { 216 0, 217 0, 218 0, 219 NULL, /* _may_bounce */ 220 _bus_dmamap_create, 221 _bus_dmamap_destroy, 222 _bus_dmamap_load, 223 _bus_dmamap_load_mbuf, 224 _bus_dmamap_load_uio, 225 _bus_dmamap_load_raw, 226 _bus_dmamap_unload, 227 NULL, 228 _bus_dmamem_alloc, 229 _bus_dmamem_free, 230 _bus_dmamem_map, 231 _bus_dmamem_unmap, 232 _bus_dmamem_mmap, 233 }; 234 #endif 235 236 void 237 pci_attach_hook(parent, self, pba) 238 struct device *parent, *self; 239 struct pcibus_attach_args *pba; 240 { 241 242 if (pba->pba_bus == 0) 243 printf(": configuration mode %d", pci_mode); 244 #ifdef MPBIOS 245 mpbios_pci_attach_hook(parent, self, pba); 246 #endif 247 #ifdef MPACPI 248 mpacpi_pci_attach_hook(parent, self, pba); 249 #endif 250 } 251 252 int 253 pci_bus_maxdevs(pc, busno) 254 pci_chipset_tag_t pc; 255 int busno; 256 { 257 258 /* 259 * Bus number is irrelevant. If Configuration Mechanism 2 is in 260 * use, can only have devices 0-15 on any bus. If Configuration 261 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 262 * range). 263 */ 264 if (pci_mode == 2) 265 return (16); 266 else 267 return (32); 268 } 269 270 pcitag_t 271 pci_make_tag(pc, bus, device, function) 272 pci_chipset_tag_t pc; 273 int bus, device, function; 274 { 275 pcitag_t tag; 276 277 #ifndef PCI_CONF_MODE 278 switch (pci_mode) { 279 case 1: 280 goto mode1; 281 case 2: 282 goto mode2; 283 default: 284 panic("pci_make_tag: mode not configured"); 285 } 286 #endif 287 288 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 289 #ifndef PCI_CONF_MODE 290 mode1: 291 #endif 292 if (bus >= 256 || device >= 32 || function >= 8) 293 panic("pci_make_tag: bad request"); 294 295 tag.mode1 = PCI_MODE1_ENABLE | 296 (bus << 16) | (device << 11) | (function << 8); 297 return tag; 298 #endif 299 300 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 301 #ifndef PCI_CONF_MODE 302 mode2: 303 #endif 304 if (bus >= 256 || device >= 16 || function >= 8) 305 panic("pci_make_tag: bad request"); 306 307 tag.mode2.port = 0xc000 | (device << 8); 308 tag.mode2.enable = 0xf0 | (function << 1); 309 tag.mode2.forward = bus; 310 return tag; 311 #endif 312 } 313 314 void 315 pci_decompose_tag(pc, tag, bp, dp, fp) 316 pci_chipset_tag_t pc; 317 pcitag_t tag; 318 int *bp, *dp, *fp; 319 { 320 321 #ifndef PCI_CONF_MODE 322 switch (pci_mode) { 323 case 1: 324 goto mode1; 325 case 2: 326 goto mode2; 327 default: 328 panic("pci_decompose_tag: mode not configured"); 329 } 330 #endif 331 332 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 333 #ifndef PCI_CONF_MODE 334 mode1: 335 #endif 336 if (bp != NULL) 337 *bp = (tag.mode1 >> 16) & 0xff; 338 if (dp != NULL) 339 *dp = (tag.mode1 >> 11) & 0x1f; 340 if (fp != NULL) 341 *fp = (tag.mode1 >> 8) & 0x7; 342 return; 343 #endif 344 345 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 346 #ifndef PCI_CONF_MODE 347 mode2: 348 #endif 349 if (bp != NULL) 350 *bp = tag.mode2.forward & 0xff; 351 if (dp != NULL) 352 *dp = (tag.mode2.port >> 8) & 0xf; 353 if (fp != NULL) 354 *fp = (tag.mode2.enable >> 1) & 0x7; 355 #endif 356 } 357 358 pcireg_t 359 pci_conf_read(pc, tag, reg) 360 pci_chipset_tag_t pc; 361 pcitag_t tag; 362 int reg; 363 { 364 pcireg_t data; 365 int s; 366 367 #ifndef PCI_CONF_MODE 368 switch (pci_mode) { 369 case 1: 370 goto mode1; 371 case 2: 372 goto mode2; 373 default: 374 panic("pci_conf_read: mode not configured"); 375 } 376 #endif 377 378 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 379 #ifndef PCI_CONF_MODE 380 mode1: 381 #endif 382 PCI_CONF_LOCK(s); 383 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 384 data = inl(PCI_MODE1_DATA_REG); 385 outl(PCI_MODE1_ADDRESS_REG, 0); 386 PCI_CONF_UNLOCK(s); 387 return data; 388 #endif 389 390 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 391 #ifndef PCI_CONF_MODE 392 mode2: 393 #endif 394 PCI_CONF_LOCK(s); 395 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 396 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 397 data = inl(tag.mode2.port | reg); 398 outb(PCI_MODE2_ENABLE_REG, 0); 399 PCI_CONF_UNLOCK(s); 400 return data; 401 #endif 402 } 403 404 void 405 pci_conf_write(pc, tag, reg, data) 406 pci_chipset_tag_t pc; 407 pcitag_t tag; 408 int reg; 409 pcireg_t data; 410 { 411 int s; 412 413 #ifndef PCI_CONF_MODE 414 switch (pci_mode) { 415 case 1: 416 goto mode1; 417 case 2: 418 goto mode2; 419 default: 420 panic("pci_conf_write: mode not configured"); 421 } 422 #endif 423 424 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 425 #ifndef PCI_CONF_MODE 426 mode1: 427 #endif 428 PCI_CONF_LOCK(s); 429 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 430 outl(PCI_MODE1_DATA_REG, data); 431 outl(PCI_MODE1_ADDRESS_REG, 0); 432 PCI_CONF_UNLOCK(s); 433 return; 434 #endif 435 436 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 437 #ifndef PCI_CONF_MODE 438 mode2: 439 #endif 440 PCI_CONF_LOCK(s); 441 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 442 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 443 outl(tag.mode2.port | reg, data); 444 outb(PCI_MODE2_ENABLE_REG, 0); 445 PCI_CONF_UNLOCK(s); 446 #endif 447 } 448 449 int 450 pci_mode_detect() 451 { 452 453 #ifdef PCI_CONF_MODE 454 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 455 return (pci_mode = PCI_CONF_MODE); 456 #else 457 #error Invalid PCI configuration mode. 458 #endif 459 #else 460 u_int32_t sav, val; 461 int i; 462 pcireg_t idreg; 463 464 if (pci_mode != -1) 465 return pci_mode; 466 467 /* 468 * We try to divine which configuration mode the host bridge wants. 469 */ 470 471 sav = inl(PCI_MODE1_ADDRESS_REG); 472 473 pci_mode = 1; /* assume this for now */ 474 /* 475 * catch some known buggy implementations of mode 1 476 */ 477 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 478 i++) { 479 pcitag_t t; 480 481 if (!pcim1_quirk_tbl[i].tag) 482 break; 483 t.mode1 = pcim1_quirk_tbl[i].tag; 484 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 485 if (idreg == pcim1_quirk_tbl[i].id) { 486 #ifdef DEBUG 487 printf("known mode 1 PCI chipset (%08x)\n", 488 idreg); 489 #endif 490 return (pci_mode); 491 } 492 } 493 494 /* 495 * Strong check for standard compliant mode 1: 496 * 1. bit 31 ("enable") can be set 497 * 2. byte/word access does not affect register 498 */ 499 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 500 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 501 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 502 val = inl(PCI_MODE1_ADDRESS_REG); 503 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 504 #ifdef DEBUG 505 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 506 val); 507 #endif 508 goto not1; 509 } 510 outl(PCI_MODE1_ADDRESS_REG, 0); 511 val = inl(PCI_MODE1_ADDRESS_REG); 512 if ((val & 0x80fffffc) != 0) 513 goto not1; 514 return (pci_mode); 515 not1: 516 outl(PCI_MODE1_ADDRESS_REG, sav); 517 518 /* 519 * This mode 2 check is quite weak (and known to give false 520 * positives on some Compaq machines). 521 * However, this doesn't matter, because this is the 522 * last test, and simply no PCI devices will be found if 523 * this happens. 524 */ 525 outb(PCI_MODE2_ENABLE_REG, 0); 526 outb(PCI_MODE2_FORWARD_REG, 0); 527 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 528 inb(PCI_MODE2_FORWARD_REG) != 0) 529 goto not2; 530 return (pci_mode = 2); 531 not2: 532 533 return (pci_mode = 0); 534 #endif 535 } 536 537 int 538 pci_intr_map(pa, ihp) 539 struct pci_attach_args *pa; 540 pci_intr_handle_t *ihp; 541 { 542 int pin = pa->pa_intrpin; 543 int line = pa->pa_intrline; 544 #if NIOAPIC > 0 545 int rawpin = pa->pa_rawintrpin; 546 pci_chipset_tag_t pc = pa->pa_pc; 547 int bus, dev, func; 548 #endif 549 550 if (pin == 0) { 551 /* No IRQ used. */ 552 goto bad; 553 } 554 555 if (pin > PCI_INTERRUPT_PIN_MAX) { 556 printf("pci_intr_map: bad interrupt pin %d\n", pin); 557 goto bad; 558 } 559 560 #if NIOAPIC > 0 561 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 562 if (mp_busses != NULL) { 563 if (intr_find_mpmapping(bus, (dev<<2)|(rawpin-1), ihp) == 0) { 564 *ihp |= line; 565 return 0; 566 } 567 /* 568 * No explicit PCI mapping found. This is not fatal, 569 * we'll try the ISA (or possibly EISA) mappings next. 570 */ 571 } 572 #endif 573 574 /* 575 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 576 * `unknown' or `no connection' on a PC. We assume that a device with 577 * `no connection' either doesn't have an interrupt (in which case the 578 * pin number should be 0, and would have been noticed above), or 579 * wasn't configured by the BIOS (in which case we punt, since there's 580 * no real way we can know how the interrupt lines are mapped in the 581 * hardware). 582 * 583 * XXX 584 * Since IRQ 0 is only used by the clock, and we can't actually be sure 585 * that the BIOS did its job, we also recognize that as meaning that 586 * the BIOS has not configured the device. 587 */ 588 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 589 printf("pci_intr_map: no mapping for pin %c (line=%02x)\n", 590 '@' + pin, line); 591 goto bad; 592 } else { 593 if (line >= NUM_LEGACY_IRQS) { 594 printf("pci_intr_map: bad interrupt line %d\n", line); 595 goto bad; 596 } 597 if (line == 2) { 598 printf("pci_intr_map: changed line 2 to line 9\n"); 599 line = 9; 600 } 601 } 602 #if NIOAPIC > 0 603 if (mp_busses != NULL) { 604 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 605 *ihp |= line; 606 return 0; 607 } 608 #if NEISA > 0 609 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 610 *ihp |= line; 611 return 0; 612 } 613 #endif 614 printf("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 615 bus, dev, func, pin, line); 616 printf("pci_intr_map: no MP mapping found\n"); 617 } 618 #endif 619 620 *ihp = line; 621 return 0; 622 623 bad: 624 *ihp = -1; 625 return 1; 626 } 627 628 const char * 629 pci_intr_string(pc, ih) 630 pci_chipset_tag_t pc; 631 pci_intr_handle_t ih; 632 { 633 return intr_string(ih); 634 } 635 636 637 const struct evcnt * 638 pci_intr_evcnt(pc, ih) 639 pci_chipset_tag_t pc; 640 pci_intr_handle_t ih; 641 { 642 643 /* XXX for now, no evcnt parent reported */ 644 return NULL; 645 } 646 647 void * 648 pci_intr_establish(pc, ih, level, func, arg) 649 pci_chipset_tag_t pc; 650 pci_intr_handle_t ih; 651 int level, (*func) __P((void *)); 652 void *arg; 653 { 654 int pin, irq; 655 struct pic *pic; 656 657 pic = &i8259_pic; 658 pin = irq = ih; 659 660 #if NIOAPIC > 0 661 if (ih & APIC_INT_VIA_APIC) { 662 pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih)); 663 if (pic == NULL) { 664 printf("pci_intr_establish: bad ioapic %d\n", 665 APIC_IRQ_APIC(ih)); 666 return NULL; 667 } 668 pin = APIC_IRQ_PIN(ih); 669 irq = APIC_IRQ_LEGACY_IRQ(ih); 670 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 671 irq = -1; 672 } 673 #endif 674 675 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg); 676 } 677 678 void 679 pci_intr_disestablish(pc, cookie) 680 pci_chipset_tag_t pc; 681 void *cookie; 682 { 683 684 intr_disestablish(cookie); 685 } 686 687 /* 688 * Determine which flags should be passed to the primary PCI bus's 689 * autoconfiguration node. We use this to detect broken chipsets 690 * which cannot safely use memory-mapped device access. 691 */ 692 int 693 pci_bus_flags() 694 { 695 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 696 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 697 int device, maxndevs; 698 pcitag_t tag; 699 pcireg_t id; 700 701 maxndevs = pci_bus_maxdevs(NULL, 0); 702 703 for (device = 0; device < maxndevs; device++) { 704 tag = pci_make_tag(NULL, 0, device, 0); 705 id = pci_conf_read(NULL, tag, PCI_ID_REG); 706 707 /* Invalid vendor ID value? */ 708 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 709 continue; 710 /* XXX Not invalid, but we've done this ~forever. */ 711 if (PCI_VENDOR(id) == 0) 712 continue; 713 714 switch (PCI_VENDOR(id)) { 715 case PCI_VENDOR_SIS: 716 switch (PCI_PRODUCT(id)) { 717 case PCI_PRODUCT_SIS_85C496: 718 goto disable_mem; 719 } 720 break; 721 } 722 } 723 724 return (rval); 725 726 disable_mem: 727 printf("Warning: broken PCI-Host bridge detected; " 728 "disabling memory-mapped access\n"); 729 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 730 PCI_FLAGS_MWI_OKAY); 731 return (rval); 732 } 733 734 void 735 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 736 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 737 { 738 pci_device_foreach_min(pc, 0, maxbus, func, context); 739 } 740 741 void 742 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 743 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 744 { 745 const struct pci_quirkdata *qd; 746 int bus, device, function, maxdevs, nfuncs; 747 pcireg_t id, bhlcr; 748 pcitag_t tag; 749 750 for (bus = minbus; bus <= maxbus; bus++) { 751 maxdevs = pci_bus_maxdevs(pc, bus); 752 for (device = 0; device < maxdevs; device++) { 753 tag = pci_make_tag(pc, bus, device, 0); 754 id = pci_conf_read(pc, tag, PCI_ID_REG); 755 756 /* Invalid vendor ID value? */ 757 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 758 continue; 759 /* XXX Not invalid, but we've done this ~forever. */ 760 if (PCI_VENDOR(id) == 0) 761 continue; 762 763 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 764 PCI_PRODUCT(id)); 765 766 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 767 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 768 (qd != NULL && 769 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 770 nfuncs = 8; 771 else 772 nfuncs = 1; 773 774 for (function = 0; function < nfuncs; function++) { 775 tag = pci_make_tag(pc, bus, device, function); 776 id = pci_conf_read(pc, tag, PCI_ID_REG); 777 778 /* Invalid vendor ID value? */ 779 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 780 continue; 781 /* 782 * XXX Not invalid, but we've done this 783 * ~forever. 784 */ 785 if (PCI_VENDOR(id) == 0) 786 continue; 787 (*func)(pc, tag, context); 788 } 789 } 790 } 791 } 792 793 void 794 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 795 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 796 { 797 struct pci_bridge_hook_arg bridge_hook; 798 799 bridge_hook.func = func; 800 bridge_hook.arg = ctx; 801 802 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 803 &bridge_hook); 804 } 805 806 static void 807 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 808 { 809 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 810 pcireg_t reg; 811 812 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 813 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 814 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 815 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 816 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 817 } 818 } 819 820 821
Indexes created Fri Sep 26 08:10:20 GMT 2025