pci_machdep.c revision 1.12
1 /* $NetBSD: pci_machdep.c,v 1.12 2005/11/16 16:08:36 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Machine-specific functions for PCI autoconfiguration. 72 * 73 * On PCs, there are two methods of generating PCI configuration cycles. 74 * We try to detect the appropriate mechanism for this machine and set 75 * up a few function pointers to access the correct method directly. 76 * 77 * The configuration method can be hard-coded in the config file by 78 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 79 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.12 2005/11/16 16:08:36 christos Exp $"); 84 85 #include <sys/types.h> 86 #include <sys/param.h> 87 #include <sys/time.h> 88 #include <sys/systm.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/lock.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <machine/bus.h> 96 #include <machine/bus_private.h> 97 98 #include <machine/pio.h> 99 #include <machine/intr.h> 100 101 #include <dev/isa/isareg.h> 102 #include <dev/isa/isavar.h> 103 #include <dev/pci/pcivar.h> 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcidevs.h> 106 107 #include "ioapic.h" 108 #include "eisa.h" 109 #include "opt_mpbios.h" 110 #include "opt_mpacpi.h" 111 112 #if NIOAPIC > 0 113 #include <machine/i82093var.h> 114 #include <machine/mpbiosvar.h> 115 #include <machine/pic.h> 116 #endif 117 118 #ifdef MPBIOS 119 #include <machine/mpbiosvar.h> 120 #endif 121 122 #ifdef MPACPI 123 #include <machine/mpacpi.h> 124 #endif 125 126 #include "opt_pci_conf_mode.h" 127 128 int pci_mode = -1; 129 130 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 131 struct pci_bridge_hook_arg { 132 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 133 void *arg; 134 }; 135 136 137 struct simplelock pci_conf_slock = SIMPLELOCK_INITIALIZER; 138 139 #define PCI_CONF_LOCK(s) \ 140 do { \ 141 (s) = splhigh(); \ 142 simple_lock(&pci_conf_slock); \ 143 } while (0) 144 145 #define PCI_CONF_UNLOCK(s) \ 146 do { \ 147 simple_unlock(&pci_conf_slock); \ 148 splx((s)); \ 149 } while (0) 150 151 #define PCI_MODE1_ENABLE 0x80000000UL 152 #define PCI_MODE1_ADDRESS_REG 0x0cf8 153 #define PCI_MODE1_DATA_REG 0x0cfc 154 155 #define PCI_MODE2_ENABLE_REG 0x0cf8 156 #define PCI_MODE2_FORWARD_REG 0x0cfa 157 158 #define _m1tag(b, d, f) \ 159 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 160 #define _qe(bus, dev, fcn, vend, prod) \ 161 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 162 struct { 163 u_int32_t tag; 164 pcireg_t id; 165 } pcim1_quirk_tbl[] = { 166 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 167 /* XXX Triflex2 not tested */ 168 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 169 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 170 /* Triton needed for Connectix Virtual PC */ 171 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 172 /* Connectix Virtual PC 5 has a 440BX */ 173 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 174 /* SIS 741 */ 175 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 176 {0, 0xffffffff} /* patchable */ 177 }; 178 #undef _m1tag 179 #undef _id 180 #undef _qe 181 182 /* 183 * PCI doesn't have any special needs; just use the generic versions 184 * of these functions. 185 */ 186 struct x86_bus_dma_tag pci_bus_dma_tag = { 187 #if defined(_LP64) || defined(PAE) 188 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 189 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 190 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 191 #else 192 0, 193 0, 194 0, 195 #endif 196 NULL, /* _may_bounce */ 197 _bus_dmamap_create, 198 _bus_dmamap_destroy, 199 _bus_dmamap_load, 200 _bus_dmamap_load_mbuf, 201 _bus_dmamap_load_uio, 202 _bus_dmamap_load_raw, 203 _bus_dmamap_unload, 204 #if defined(_LP64) || defined(PAE) 205 _bus_dmamap_sync, 206 #else 207 NULL, 208 #endif 209 _bus_dmamem_alloc, 210 _bus_dmamem_free, 211 _bus_dmamem_map, 212 _bus_dmamem_unmap, 213 _bus_dmamem_mmap, 214 }; 215 216 #ifdef _LP64 217 struct x86_bus_dma_tag pci_bus_dma64_tag = { 218 0, 219 0, 220 0, 221 NULL, /* _may_bounce */ 222 _bus_dmamap_create, 223 _bus_dmamap_destroy, 224 _bus_dmamap_load, 225 _bus_dmamap_load_mbuf, 226 _bus_dmamap_load_uio, 227 _bus_dmamap_load_raw, 228 _bus_dmamap_unload, 229 NULL, 230 _bus_dmamem_alloc, 231 _bus_dmamem_free, 232 _bus_dmamem_map, 233 _bus_dmamem_unmap, 234 _bus_dmamem_mmap, 235 }; 236 #endif 237 238 void 239 pci_attach_hook(parent, self, pba) 240 struct device *parent, *self; 241 struct pcibus_attach_args *pba; 242 { 243 244 if (pba->pba_bus == 0) 245 printf(": configuration mode %d", pci_mode); 246 #ifdef MPBIOS 247 mpbios_pci_attach_hook(parent, self, pba); 248 #endif 249 #ifdef MPACPI 250 mpacpi_pci_attach_hook(parent, self, pba); 251 #endif 252 } 253 254 int 255 pci_bus_maxdevs(pc, busno) 256 pci_chipset_tag_t pc; 257 int busno; 258 { 259 260 /* 261 * Bus number is irrelevant. If Configuration Mechanism 2 is in 262 * use, can only have devices 0-15 on any bus. If Configuration 263 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 264 * range). 265 */ 266 if (pci_mode == 2) 267 return (16); 268 else 269 return (32); 270 } 271 272 pcitag_t 273 pci_make_tag(pc, bus, device, function) 274 pci_chipset_tag_t pc; 275 int bus, device, function; 276 { 277 pcitag_t tag; 278 279 #ifndef PCI_CONF_MODE 280 switch (pci_mode) { 281 case 1: 282 goto mode1; 283 case 2: 284 goto mode2; 285 default: 286 panic("pci_make_tag: mode not configured"); 287 } 288 #endif 289 290 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 291 #ifndef PCI_CONF_MODE 292 mode1: 293 #endif 294 if (bus >= 256 || device >= 32 || function >= 8) 295 panic("pci_make_tag: bad request"); 296 297 tag.mode1 = PCI_MODE1_ENABLE | 298 (bus << 16) | (device << 11) | (function << 8); 299 return tag; 300 #endif 301 302 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 303 #ifndef PCI_CONF_MODE 304 mode2: 305 #endif 306 if (bus >= 256 || device >= 16 || function >= 8) 307 panic("pci_make_tag: bad request"); 308 309 tag.mode2.port = 0xc000 | (device << 8); 310 tag.mode2.enable = 0xf0 | (function << 1); 311 tag.mode2.forward = bus; 312 return tag; 313 #endif 314 } 315 316 void 317 pci_decompose_tag(pc, tag, bp, dp, fp) 318 pci_chipset_tag_t pc; 319 pcitag_t tag; 320 int *bp, *dp, *fp; 321 { 322 323 #ifndef PCI_CONF_MODE 324 switch (pci_mode) { 325 case 1: 326 goto mode1; 327 case 2: 328 goto mode2; 329 default: 330 panic("pci_decompose_tag: mode not configured"); 331 } 332 #endif 333 334 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 335 #ifndef PCI_CONF_MODE 336 mode1: 337 #endif 338 if (bp != NULL) 339 *bp = (tag.mode1 >> 16) & 0xff; 340 if (dp != NULL) 341 *dp = (tag.mode1 >> 11) & 0x1f; 342 if (fp != NULL) 343 *fp = (tag.mode1 >> 8) & 0x7; 344 return; 345 #endif 346 347 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 348 #ifndef PCI_CONF_MODE 349 mode2: 350 #endif 351 if (bp != NULL) 352 *bp = tag.mode2.forward & 0xff; 353 if (dp != NULL) 354 *dp = (tag.mode2.port >> 8) & 0xf; 355 if (fp != NULL) 356 *fp = (tag.mode2.enable >> 1) & 0x7; 357 #endif 358 } 359 360 pcireg_t 361 pci_conf_read(pc, tag, reg) 362 pci_chipset_tag_t pc; 363 pcitag_t tag; 364 int reg; 365 { 366 pcireg_t data; 367 int s; 368 369 #ifndef PCI_CONF_MODE 370 switch (pci_mode) { 371 case 1: 372 goto mode1; 373 case 2: 374 goto mode2; 375 default: 376 panic("pci_conf_read: mode not configured"); 377 } 378 #endif 379 380 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 381 #ifndef PCI_CONF_MODE 382 mode1: 383 #endif 384 PCI_CONF_LOCK(s); 385 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 386 data = inl(PCI_MODE1_DATA_REG); 387 outl(PCI_MODE1_ADDRESS_REG, 0); 388 PCI_CONF_UNLOCK(s); 389 return data; 390 #endif 391 392 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 393 #ifndef PCI_CONF_MODE 394 mode2: 395 #endif 396 PCI_CONF_LOCK(s); 397 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 398 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 399 data = inl(tag.mode2.port | reg); 400 outb(PCI_MODE2_ENABLE_REG, 0); 401 PCI_CONF_UNLOCK(s); 402 return data; 403 #endif 404 } 405 406 void 407 pci_conf_write(pc, tag, reg, data) 408 pci_chipset_tag_t pc; 409 pcitag_t tag; 410 int reg; 411 pcireg_t data; 412 { 413 int s; 414 415 #ifndef PCI_CONF_MODE 416 switch (pci_mode) { 417 case 1: 418 goto mode1; 419 case 2: 420 goto mode2; 421 default: 422 panic("pci_conf_write: mode not configured"); 423 } 424 #endif 425 426 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 427 #ifndef PCI_CONF_MODE 428 mode1: 429 #endif 430 PCI_CONF_LOCK(s); 431 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 432 outl(PCI_MODE1_DATA_REG, data); 433 outl(PCI_MODE1_ADDRESS_REG, 0); 434 PCI_CONF_UNLOCK(s); 435 return; 436 #endif 437 438 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 439 #ifndef PCI_CONF_MODE 440 mode2: 441 #endif 442 PCI_CONF_LOCK(s); 443 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 444 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 445 outl(tag.mode2.port | reg, data); 446 outb(PCI_MODE2_ENABLE_REG, 0); 447 PCI_CONF_UNLOCK(s); 448 #endif 449 } 450 451 int 452 pci_mode_detect() 453 { 454 455 #ifdef PCI_CONF_MODE 456 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 457 return (pci_mode = PCI_CONF_MODE); 458 #else 459 #error Invalid PCI configuration mode. 460 #endif 461 #else 462 u_int32_t sav, val; 463 int i; 464 pcireg_t idreg; 465 466 if (pci_mode != -1) 467 return pci_mode; 468 469 /* 470 * We try to divine which configuration mode the host bridge wants. 471 */ 472 473 sav = inl(PCI_MODE1_ADDRESS_REG); 474 475 pci_mode = 1; /* assume this for now */ 476 /* 477 * catch some known buggy implementations of mode 1 478 */ 479 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 480 i++) { 481 pcitag_t t; 482 483 if (!pcim1_quirk_tbl[i].tag) 484 break; 485 t.mode1 = pcim1_quirk_tbl[i].tag; 486 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 487 if (idreg == pcim1_quirk_tbl[i].id) { 488 #ifdef DEBUG 489 printf("known mode 1 PCI chipset (%08x)\n", 490 idreg); 491 #endif 492 return (pci_mode); 493 } 494 } 495 496 /* 497 * Strong check for standard compliant mode 1: 498 * 1. bit 31 ("enable") can be set 499 * 2. byte/word access does not affect register 500 */ 501 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 502 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 503 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 504 val = inl(PCI_MODE1_ADDRESS_REG); 505 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 506 #ifdef DEBUG 507 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 508 val); 509 #endif 510 goto not1; 511 } 512 outl(PCI_MODE1_ADDRESS_REG, 0); 513 val = inl(PCI_MODE1_ADDRESS_REG); 514 if ((val & 0x80fffffc) != 0) 515 goto not1; 516 return (pci_mode); 517 not1: 518 outl(PCI_MODE1_ADDRESS_REG, sav); 519 520 /* 521 * This mode 2 check is quite weak (and known to give false 522 * positives on some Compaq machines). 523 * However, this doesn't matter, because this is the 524 * last test, and simply no PCI devices will be found if 525 * this happens. 526 */ 527 outb(PCI_MODE2_ENABLE_REG, 0); 528 outb(PCI_MODE2_FORWARD_REG, 0); 529 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 530 inb(PCI_MODE2_FORWARD_REG) != 0) 531 goto not2; 532 return (pci_mode = 2); 533 not2: 534 535 return (pci_mode = 0); 536 #endif 537 } 538 539 int 540 pci_intr_map(pa, ihp) 541 struct pci_attach_args *pa; 542 pci_intr_handle_t *ihp; 543 { 544 int pin = pa->pa_intrpin; 545 int line = pa->pa_intrline; 546 #if NIOAPIC > 0 547 int rawpin = pa->pa_rawintrpin; 548 pci_chipset_tag_t pc = pa->pa_pc; 549 int bus, dev, func; 550 #endif 551 552 if (pin == 0) { 553 /* No IRQ used. */ 554 goto bad; 555 } 556 557 if (pin > PCI_INTERRUPT_PIN_MAX) { 558 printf("pci_intr_map: bad interrupt pin %d\n", pin); 559 goto bad; 560 } 561 562 #if NIOAPIC > 0 563 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 564 if (mp_busses != NULL) { 565 if (intr_find_mpmapping(bus, (dev<<2)|(rawpin-1), ihp) == 0) { 566 *ihp |= line; 567 return 0; 568 } 569 /* 570 * No explicit PCI mapping found. This is not fatal, 571 * we'll try the ISA (or possibly EISA) mappings next. 572 */ 573 } 574 #endif 575 576 /* 577 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 578 * `unknown' or `no connection' on a PC. We assume that a device with 579 * `no connection' either doesn't have an interrupt (in which case the 580 * pin number should be 0, and would have been noticed above), or 581 * wasn't configured by the BIOS (in which case we punt, since there's 582 * no real way we can know how the interrupt lines are mapped in the 583 * hardware). 584 * 585 * XXX 586 * Since IRQ 0 is only used by the clock, and we can't actually be sure 587 * that the BIOS did its job, we also recognize that as meaning that 588 * the BIOS has not configured the device. 589 */ 590 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 591 printf("pci_intr_map: no mapping for pin %c (line=%02x)\n", 592 '@' + pin, line); 593 goto bad; 594 } else { 595 if (line >= NUM_LEGACY_IRQS) { 596 printf("pci_intr_map: bad interrupt line %d\n", line); 597 goto bad; 598 } 599 if (line == 2) { 600 printf("pci_intr_map: changed line 2 to line 9\n"); 601 line = 9; 602 } 603 } 604 #if NIOAPIC > 0 605 if (mp_busses != NULL) { 606 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 607 *ihp |= line; 608 return 0; 609 } 610 #if NEISA > 0 611 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 612 *ihp |= line; 613 return 0; 614 } 615 #endif 616 printf("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 617 bus, dev, func, pin, line); 618 printf("pci_intr_map: no MP mapping found\n"); 619 } 620 #endif 621 622 *ihp = line; 623 return 0; 624 625 bad: 626 *ihp = -1; 627 return 1; 628 } 629 630 const char * 631 pci_intr_string(pc, ih) 632 pci_chipset_tag_t pc; 633 pci_intr_handle_t ih; 634 { 635 return intr_string(ih); 636 } 637 638 639 const struct evcnt * 640 pci_intr_evcnt(pc, ih) 641 pci_chipset_tag_t pc; 642 pci_intr_handle_t ih; 643 { 644 645 /* XXX for now, no evcnt parent reported */ 646 return NULL; 647 } 648 649 void * 650 pci_intr_establish(pc, ih, level, func, arg) 651 pci_chipset_tag_t pc; 652 pci_intr_handle_t ih; 653 int level, (*func) __P((void *)); 654 void *arg; 655 { 656 int pin, irq; 657 struct pic *pic; 658 659 pic = &i8259_pic; 660 pin = irq = ih; 661 662 #if NIOAPIC > 0 663 if (ih & APIC_INT_VIA_APIC) { 664 pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih)); 665 if (pic == NULL) { 666 printf("pci_intr_establish: bad ioapic %d\n", 667 APIC_IRQ_APIC(ih)); 668 return NULL; 669 } 670 pin = APIC_IRQ_PIN(ih); 671 irq = APIC_IRQ_LEGACY_IRQ(ih); 672 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 673 irq = -1; 674 } 675 #endif 676 677 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg); 678 } 679 680 void 681 pci_intr_disestablish(pc, cookie) 682 pci_chipset_tag_t pc; 683 void *cookie; 684 { 685 686 intr_disestablish(cookie); 687 } 688 689 /* 690 * Determine which flags should be passed to the primary PCI bus's 691 * autoconfiguration node. We use this to detect broken chipsets 692 * which cannot safely use memory-mapped device access. 693 */ 694 int 695 pci_bus_flags() 696 { 697 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 698 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 699 int device, maxndevs; 700 pcitag_t tag; 701 pcireg_t id; 702 703 maxndevs = pci_bus_maxdevs(NULL, 0); 704 705 for (device = 0; device < maxndevs; device++) { 706 tag = pci_make_tag(NULL, 0, device, 0); 707 id = pci_conf_read(NULL, tag, PCI_ID_REG); 708 709 /* Invalid vendor ID value? */ 710 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 711 continue; 712 /* XXX Not invalid, but we've done this ~forever. */ 713 if (PCI_VENDOR(id) == 0) 714 continue; 715 716 switch (PCI_VENDOR(id)) { 717 case PCI_VENDOR_SIS: 718 switch (PCI_PRODUCT(id)) { 719 case PCI_PRODUCT_SIS_85C496: 720 goto disable_mem; 721 } 722 break; 723 } 724 } 725 726 return (rval); 727 728 disable_mem: 729 printf("Warning: broken PCI-Host bridge detected; " 730 "disabling memory-mapped access\n"); 731 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 732 PCI_FLAGS_MWI_OKAY); 733 return (rval); 734 } 735 736 void 737 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 738 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 739 { 740 pci_device_foreach_min(pc, 0, maxbus, func, context); 741 } 742 743 void 744 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 745 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 746 { 747 const struct pci_quirkdata *qd; 748 int bus, device, function, maxdevs, nfuncs; 749 pcireg_t id, bhlcr; 750 pcitag_t tag; 751 752 for (bus = minbus; bus <= maxbus; bus++) { 753 maxdevs = pci_bus_maxdevs(pc, bus); 754 for (device = 0; device < maxdevs; device++) { 755 tag = pci_make_tag(pc, bus, device, 0); 756 id = pci_conf_read(pc, tag, PCI_ID_REG); 757 758 /* Invalid vendor ID value? */ 759 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 760 continue; 761 /* XXX Not invalid, but we've done this ~forever. */ 762 if (PCI_VENDOR(id) == 0) 763 continue; 764 765 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 766 PCI_PRODUCT(id)); 767 768 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 769 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 770 (qd != NULL && 771 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 772 nfuncs = 8; 773 else 774 nfuncs = 1; 775 776 for (function = 0; function < nfuncs; function++) { 777 tag = pci_make_tag(pc, bus, device, function); 778 id = pci_conf_read(pc, tag, PCI_ID_REG); 779 780 /* Invalid vendor ID value? */ 781 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 782 continue; 783 /* 784 * XXX Not invalid, but we've done this 785 * ~forever. 786 */ 787 if (PCI_VENDOR(id) == 0) 788 continue; 789 (*func)(pc, tag, context); 790 } 791 } 792 } 793 } 794 795 void 796 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 797 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 798 { 799 struct pci_bridge_hook_arg bridge_hook; 800 801 bridge_hook.func = func; 802 bridge_hook.arg = ctx; 803 804 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 805 &bridge_hook); 806 } 807 808 static void 809 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 810 { 811 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 812 pcireg_t reg; 813 814 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 815 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 816 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 817 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 818 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 819 } 820 } 821 822 823
Indexes created Fri Sep 26 20:09:58 GMT 2025