pci_machdep.c revision 1.17
1 /* $NetBSD: pci_machdep.c,v 1.17 2006/10/12 01:30:44 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Machine-specific functions for PCI autoconfiguration. 72 * 73 * On PCs, there are two methods of generating PCI configuration cycles. 74 * We try to detect the appropriate mechanism for this machine and set 75 * up a few function pointers to access the correct method directly. 76 * 77 * The configuration method can be hard-coded in the config file by 78 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 79 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.17 2006/10/12 01:30:44 christos Exp $"); 84 85 #include <sys/types.h> 86 #include <sys/param.h> 87 #include <sys/time.h> 88 #include <sys/systm.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/lock.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <machine/bus.h> 96 #include <machine/bus_private.h> 97 98 #include <machine/pio.h> 99 100 #include <dev/isa/isareg.h> 101 #include <dev/isa/isavar.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcidevs.h> 105 106 #include "acpi.h" 107 #include "opt_mpbios.h" 108 #include "opt_acpi.h" 109 110 #ifdef MPBIOS 111 #include <machine/mpbiosvar.h> 112 #endif 113 114 #if NACPI > 0 115 #include <machine/mpacpi.h> 116 #endif 117 118 #include <machine/mpconfig.h> 119 120 #include "opt_pci_conf_mode.h" 121 122 int pci_mode = -1; 123 124 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 125 struct pci_bridge_hook_arg { 126 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 127 void *arg; 128 }; 129 130 131 struct simplelock pci_conf_slock = SIMPLELOCK_INITIALIZER; 132 133 #define PCI_CONF_LOCK(s) \ 134 do { \ 135 (s) = splhigh(); \ 136 simple_lock(&pci_conf_slock); \ 137 } while (0) 138 139 #define PCI_CONF_UNLOCK(s) \ 140 do { \ 141 simple_unlock(&pci_conf_slock); \ 142 splx((s)); \ 143 } while (0) 144 145 #define PCI_MODE1_ENABLE 0x80000000UL 146 #define PCI_MODE1_ADDRESS_REG 0x0cf8 147 #define PCI_MODE1_DATA_REG 0x0cfc 148 149 #define PCI_MODE2_ENABLE_REG 0x0cf8 150 #define PCI_MODE2_FORWARD_REG 0x0cfa 151 152 #define _m1tag(b, d, f) \ 153 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 154 #define _qe(bus, dev, fcn, vend, prod) \ 155 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 156 struct { 157 u_int32_t tag; 158 pcireg_t id; 159 } pcim1_quirk_tbl[] = { 160 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 161 /* XXX Triflex2 not tested */ 162 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 163 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 164 /* Triton needed for Connectix Virtual PC */ 165 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 166 /* Connectix Virtual PC 5 has a 440BX */ 167 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 168 /* Parallels Desktop for Mac */ 169 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 170 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 171 /* SIS 741 */ 172 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 173 {0, 0xffffffff} /* patchable */ 174 }; 175 #undef _m1tag 176 #undef _id 177 #undef _qe 178 179 /* 180 * PCI doesn't have any special needs; just use the generic versions 181 * of these functions. 182 */ 183 struct x86_bus_dma_tag pci_bus_dma_tag = { 184 #if defined(_LP64) || defined(PAE) 185 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 186 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 187 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 188 #else 189 0, 190 0, 191 0, 192 #endif 193 NULL, /* _may_bounce */ 194 _bus_dmamap_create, 195 _bus_dmamap_destroy, 196 _bus_dmamap_load, 197 _bus_dmamap_load_mbuf, 198 _bus_dmamap_load_uio, 199 _bus_dmamap_load_raw, 200 _bus_dmamap_unload, 201 #if defined(_LP64) || defined(PAE) 202 _bus_dmamap_sync, 203 #else 204 NULL, 205 #endif 206 _bus_dmamem_alloc, 207 _bus_dmamem_free, 208 _bus_dmamem_map, 209 _bus_dmamem_unmap, 210 _bus_dmamem_mmap, 211 }; 212 213 #ifdef _LP64 214 struct x86_bus_dma_tag pci_bus_dma64_tag = { 215 0, 216 0, 217 0, 218 NULL, /* _may_bounce */ 219 _bus_dmamap_create, 220 _bus_dmamap_destroy, 221 _bus_dmamap_load, 222 _bus_dmamap_load_mbuf, 223 _bus_dmamap_load_uio, 224 _bus_dmamap_load_raw, 225 _bus_dmamap_unload, 226 NULL, 227 _bus_dmamem_alloc, 228 _bus_dmamem_free, 229 _bus_dmamem_map, 230 _bus_dmamem_unmap, 231 _bus_dmamem_mmap, 232 }; 233 #endif 234 235 void 236 pci_attach_hook(struct device *parent __unused, struct device *self __unused, 237 struct pcibus_attach_args *pba) 238 { 239 240 if (pba->pba_bus == 0) 241 printf(": configuration mode %d", pci_mode); 242 #ifdef MPBIOS 243 mpbios_pci_attach_hook(parent, self, pba); 244 #endif 245 #if NACPI > 0 246 mpacpi_pci_attach_hook(parent, self, pba); 247 #endif 248 } 249 250 int 251 pci_bus_maxdevs(pci_chipset_tag_t pc __unused, int busno __unused) 252 { 253 254 /* 255 * Bus number is irrelevant. If Configuration Mechanism 2 is in 256 * use, can only have devices 0-15 on any bus. If Configuration 257 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 258 * range). 259 */ 260 if (pci_mode == 2) 261 return (16); 262 else 263 return (32); 264 } 265 266 pcitag_t 267 pci_make_tag(pci_chipset_tag_t pc __unused, int bus, int device, int function) 268 { 269 pcitag_t tag; 270 271 #ifndef PCI_CONF_MODE 272 switch (pci_mode) { 273 case 1: 274 goto mode1; 275 case 2: 276 goto mode2; 277 default: 278 panic("pci_make_tag: mode not configured"); 279 } 280 #endif 281 282 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 283 #ifndef PCI_CONF_MODE 284 mode1: 285 #endif 286 if (bus >= 256 || device >= 32 || function >= 8) 287 panic("pci_make_tag: bad request"); 288 289 tag.mode1 = PCI_MODE1_ENABLE | 290 (bus << 16) | (device << 11) | (function << 8); 291 return tag; 292 #endif 293 294 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 295 #ifndef PCI_CONF_MODE 296 mode2: 297 #endif 298 if (bus >= 256 || device >= 16 || function >= 8) 299 panic("pci_make_tag: bad request"); 300 301 tag.mode2.port = 0xc000 | (device << 8); 302 tag.mode2.enable = 0xf0 | (function << 1); 303 tag.mode2.forward = bus; 304 return tag; 305 #endif 306 } 307 308 void 309 pci_decompose_tag(pci_chipset_tag_t pc __unused, pcitag_t tag, 310 int *bp, int *dp, int *fp) 311 { 312 313 #ifndef PCI_CONF_MODE 314 switch (pci_mode) { 315 case 1: 316 goto mode1; 317 case 2: 318 goto mode2; 319 default: 320 panic("pci_decompose_tag: mode not configured"); 321 } 322 #endif 323 324 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 325 #ifndef PCI_CONF_MODE 326 mode1: 327 #endif 328 if (bp != NULL) 329 *bp = (tag.mode1 >> 16) & 0xff; 330 if (dp != NULL) 331 *dp = (tag.mode1 >> 11) & 0x1f; 332 if (fp != NULL) 333 *fp = (tag.mode1 >> 8) & 0x7; 334 return; 335 #endif 336 337 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 338 #ifndef PCI_CONF_MODE 339 mode2: 340 #endif 341 if (bp != NULL) 342 *bp = tag.mode2.forward & 0xff; 343 if (dp != NULL) 344 *dp = (tag.mode2.port >> 8) & 0xf; 345 if (fp != NULL) 346 *fp = (tag.mode2.enable >> 1) & 0x7; 347 #endif 348 } 349 350 pcireg_t 351 pci_conf_read( pci_chipset_tag_t pc __unused, pcitag_t tag __unused, 352 int reg __unused) 353 { 354 pcireg_t data; 355 int s; 356 357 #ifndef PCI_CONF_MODE 358 switch (pci_mode) { 359 case 1: 360 goto mode1; 361 case 2: 362 goto mode2; 363 default: 364 panic("pci_conf_read: mode not configured"); 365 } 366 #endif 367 368 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 369 #ifndef PCI_CONF_MODE 370 mode1: 371 #endif 372 PCI_CONF_LOCK(s); 373 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 374 data = inl(PCI_MODE1_DATA_REG); 375 outl(PCI_MODE1_ADDRESS_REG, 0); 376 PCI_CONF_UNLOCK(s); 377 return data; 378 #endif 379 380 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 381 #ifndef PCI_CONF_MODE 382 mode2: 383 #endif 384 PCI_CONF_LOCK(s); 385 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 386 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 387 data = inl(tag.mode2.port | reg); 388 outb(PCI_MODE2_ENABLE_REG, 0); 389 PCI_CONF_UNLOCK(s); 390 return data; 391 #endif 392 } 393 394 void 395 pci_conf_write(pci_chipset_tag_t pc __unused, pcitag_t tag, int reg, 396 pcireg_t data) 397 { 398 int s; 399 400 #ifndef PCI_CONF_MODE 401 switch (pci_mode) { 402 case 1: 403 goto mode1; 404 case 2: 405 goto mode2; 406 default: 407 panic("pci_conf_write: mode not configured"); 408 } 409 #endif 410 411 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 412 #ifndef PCI_CONF_MODE 413 mode1: 414 #endif 415 PCI_CONF_LOCK(s); 416 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 417 outl(PCI_MODE1_DATA_REG, data); 418 outl(PCI_MODE1_ADDRESS_REG, 0); 419 PCI_CONF_UNLOCK(s); 420 return; 421 #endif 422 423 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 424 #ifndef PCI_CONF_MODE 425 mode2: 426 #endif 427 PCI_CONF_LOCK(s); 428 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 429 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 430 outl(tag.mode2.port | reg, data); 431 outb(PCI_MODE2_ENABLE_REG, 0); 432 PCI_CONF_UNLOCK(s); 433 #endif 434 } 435 436 int 437 pci_mode_detect() 438 { 439 440 #ifdef PCI_CONF_MODE 441 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 442 return (pci_mode = PCI_CONF_MODE); 443 #else 444 #error Invalid PCI configuration mode. 445 #endif 446 #else 447 u_int32_t sav, val; 448 int i; 449 pcireg_t idreg; 450 451 if (pci_mode != -1) 452 return pci_mode; 453 454 /* 455 * We try to divine which configuration mode the host bridge wants. 456 */ 457 458 sav = inl(PCI_MODE1_ADDRESS_REG); 459 460 pci_mode = 1; /* assume this for now */ 461 /* 462 * catch some known buggy implementations of mode 1 463 */ 464 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 465 i++) { 466 pcitag_t t; 467 468 if (!pcim1_quirk_tbl[i].tag) 469 break; 470 t.mode1 = pcim1_quirk_tbl[i].tag; 471 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 472 if (idreg == pcim1_quirk_tbl[i].id) { 473 #ifdef DEBUG 474 printf("known mode 1 PCI chipset (%08x)\n", 475 idreg); 476 #endif 477 return (pci_mode); 478 } 479 } 480 481 /* 482 * Strong check for standard compliant mode 1: 483 * 1. bit 31 ("enable") can be set 484 * 2. byte/word access does not affect register 485 */ 486 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 487 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 488 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 489 val = inl(PCI_MODE1_ADDRESS_REG); 490 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 491 #ifdef DEBUG 492 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 493 val); 494 #endif 495 goto not1; 496 } 497 outl(PCI_MODE1_ADDRESS_REG, 0); 498 val = inl(PCI_MODE1_ADDRESS_REG); 499 if ((val & 0x80fffffc) != 0) 500 goto not1; 501 return (pci_mode); 502 not1: 503 outl(PCI_MODE1_ADDRESS_REG, sav); 504 505 /* 506 * This mode 2 check is quite weak (and known to give false 507 * positives on some Compaq machines). 508 * However, this doesn't matter, because this is the 509 * last test, and simply no PCI devices will be found if 510 * this happens. 511 */ 512 outb(PCI_MODE2_ENABLE_REG, 0); 513 outb(PCI_MODE2_FORWARD_REG, 0); 514 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 515 inb(PCI_MODE2_FORWARD_REG) != 0) 516 goto not2; 517 return (pci_mode = 2); 518 not2: 519 520 return (pci_mode = 0); 521 #endif 522 } 523 524 /* 525 * Determine which flags should be passed to the primary PCI bus's 526 * autoconfiguration node. We use this to detect broken chipsets 527 * which cannot safely use memory-mapped device access. 528 */ 529 int 530 pci_bus_flags() 531 { 532 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 533 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 534 int device, maxndevs; 535 pcitag_t tag; 536 pcireg_t id; 537 538 maxndevs = pci_bus_maxdevs(NULL, 0); 539 540 for (device = 0; device < maxndevs; device++) { 541 tag = pci_make_tag(NULL, 0, device, 0); 542 id = pci_conf_read(NULL, tag, PCI_ID_REG); 543 544 /* Invalid vendor ID value? */ 545 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 546 continue; 547 /* XXX Not invalid, but we've done this ~forever. */ 548 if (PCI_VENDOR(id) == 0) 549 continue; 550 551 switch (PCI_VENDOR(id)) { 552 case PCI_VENDOR_SIS: 553 switch (PCI_PRODUCT(id)) { 554 case PCI_PRODUCT_SIS_85C496: 555 goto disable_mem; 556 } 557 break; 558 } 559 } 560 561 return (rval); 562 563 disable_mem: 564 printf("Warning: broken PCI-Host bridge detected; " 565 "disabling memory-mapped access\n"); 566 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 567 PCI_FLAGS_MWI_OKAY); 568 return (rval); 569 } 570 571 void 572 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 573 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 574 { 575 pci_device_foreach_min(pc, 0, maxbus, func, context); 576 } 577 578 void 579 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 580 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 581 { 582 const struct pci_quirkdata *qd; 583 int bus, device, function, maxdevs, nfuncs; 584 pcireg_t id, bhlcr; 585 pcitag_t tag; 586 587 for (bus = minbus; bus <= maxbus; bus++) { 588 maxdevs = pci_bus_maxdevs(pc, bus); 589 for (device = 0; device < maxdevs; device++) { 590 tag = pci_make_tag(pc, bus, device, 0); 591 id = pci_conf_read(pc, tag, PCI_ID_REG); 592 593 /* Invalid vendor ID value? */ 594 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 595 continue; 596 /* XXX Not invalid, but we've done this ~forever. */ 597 if (PCI_VENDOR(id) == 0) 598 continue; 599 600 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 601 PCI_PRODUCT(id)); 602 603 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 604 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 605 (qd != NULL && 606 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 607 nfuncs = 8; 608 else 609 nfuncs = 1; 610 611 for (function = 0; function < nfuncs; function++) { 612 tag = pci_make_tag(pc, bus, device, function); 613 id = pci_conf_read(pc, tag, PCI_ID_REG); 614 615 /* Invalid vendor ID value? */ 616 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 617 continue; 618 /* 619 * XXX Not invalid, but we've done this 620 * ~forever. 621 */ 622 if (PCI_VENDOR(id) == 0) 623 continue; 624 (*func)(pc, tag, context); 625 } 626 } 627 } 628 } 629 630 void 631 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 632 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 633 { 634 struct pci_bridge_hook_arg bridge_hook; 635 636 bridge_hook.func = func; 637 bridge_hook.arg = ctx; 638 639 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 640 &bridge_hook); 641 } 642 643 static void 644 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 645 { 646 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 647 pcireg_t reg; 648 649 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 650 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 651 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 652 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 653 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 654 } 655 } 656
Indexes created Wed Sep 24 22:09:59 GMT 2025