pci_machdep.c revision 1.2
1 /* $NetBSD: pci_machdep.c,v 1.2 2003/04/28 20:26:18 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Machine-specific functions for PCI autoconfiguration. 72 * 73 * On PCs, there are two methods of generating PCI configuration cycles. 74 * We try to detect the appropriate mechanism for this machine and set 75 * up a few function pointers to access the correct method directly. 76 * 77 * The configuration method can be hard-coded in the config file by 78 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 79 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.2 2003/04/28 20:26:18 fvdl Exp $"); 84 85 #include <sys/types.h> 86 #include <sys/param.h> 87 #include <sys/time.h> 88 #include <sys/systm.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/lock.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #define _X86_BUS_DMA_PRIVATE 96 #include <machine/bus.h> 97 98 #include <machine/pio.h> 99 #include <machine/intr.h> 100 101 #include <dev/isa/isavar.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcidevs.h> 105 106 #include "ioapic.h" 107 #include "eisa.h" 108 109 #if NIOAPIC > 0 110 #include <machine/i82093var.h> 111 #include <machine/mpbiosvar.h> 112 #endif 113 114 #include "opt_pci_conf_mode.h" 115 116 int pci_mode = -1; 117 118 struct simplelock pci_conf_slock = SIMPLELOCK_INITIALIZER; 119 120 #define PCI_CONF_LOCK(s) \ 121 do { \ 122 (s) = splhigh(); \ 123 simple_lock(&pci_conf_slock); \ 124 } while (0) 125 126 #define PCI_CONF_UNLOCK(s) \ 127 do { \ 128 simple_unlock(&pci_conf_slock); \ 129 splx((s)); \ 130 } while (0) 131 132 #define PCI_MODE1_ENABLE 0x80000000UL 133 #define PCI_MODE1_ADDRESS_REG 0x0cf8 134 #define PCI_MODE1_DATA_REG 0x0cfc 135 136 #define PCI_MODE2_ENABLE_REG 0x0cf8 137 #define PCI_MODE2_FORWARD_REG 0x0cfa 138 139 #define _m1tag(b, d, f) \ 140 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 141 #define _qe(bus, dev, fcn, vend, prod) \ 142 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 143 struct { 144 u_int32_t tag; 145 pcireg_t id; 146 } pcim1_quirk_tbl[] = { 147 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 148 /* XXX Triflex2 not tested */ 149 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 150 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 151 /* Triton needed for Connectix Virtual PC */ 152 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 153 /* Connectix Virtual PC 5 has a 440BX */ 154 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 155 {0, 0xffffffff} /* patchable */ 156 }; 157 #undef _m1tag 158 #undef _id 159 #undef _qe 160 161 /* 162 * PCI doesn't have any special needs; just use the generic versions 163 * of these functions. 164 */ 165 struct x86_bus_dma_tag pci_bus_dma_tag = { 166 0, /* _bounce_thresh */ 167 _bus_dmamap_create, 168 _bus_dmamap_destroy, 169 _bus_dmamap_load, 170 _bus_dmamap_load_mbuf, 171 _bus_dmamap_load_uio, 172 _bus_dmamap_load_raw, 173 _bus_dmamap_unload, 174 NULL, /* _dmamap_sync */ 175 _bus_dmamem_alloc, 176 _bus_dmamem_free, 177 _bus_dmamem_map, 178 _bus_dmamem_unmap, 179 _bus_dmamem_mmap, 180 }; 181 182 void 183 pci_attach_hook(parent, self, pba) 184 struct device *parent, *self; 185 struct pcibus_attach_args *pba; 186 { 187 188 if (pba->pba_bus == 0) 189 printf(": configuration mode %d", pci_mode); 190 } 191 192 int 193 pci_bus_maxdevs(pc, busno) 194 pci_chipset_tag_t pc; 195 int busno; 196 { 197 198 /* 199 * Bus number is irrelevant. If Configuration Mechanism 2 is in 200 * use, can only have devices 0-15 on any bus. If Configuration 201 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 202 * range). 203 */ 204 if (pci_mode == 2) 205 return (16); 206 else 207 return (32); 208 } 209 210 pcitag_t 211 pci_make_tag(pc, bus, device, function) 212 pci_chipset_tag_t pc; 213 int bus, device, function; 214 { 215 pcitag_t tag; 216 217 #ifndef PCI_CONF_MODE 218 switch (pci_mode) { 219 case 1: 220 goto mode1; 221 case 2: 222 goto mode2; 223 default: 224 panic("pci_make_tag: mode not configured"); 225 } 226 #endif 227 228 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 229 #ifndef PCI_CONF_MODE 230 mode1: 231 #endif 232 if (bus >= 256 || device >= 32 || function >= 8) 233 panic("pci_make_tag: bad request"); 234 235 tag.mode1 = PCI_MODE1_ENABLE | 236 (bus << 16) | (device << 11) | (function << 8); 237 return tag; 238 #endif 239 240 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 241 #ifndef PCI_CONF_MODE 242 mode2: 243 #endif 244 if (bus >= 256 || device >= 16 || function >= 8) 245 panic("pci_make_tag: bad request"); 246 247 tag.mode2.port = 0xc000 | (device << 8); 248 tag.mode2.enable = 0xf0 | (function << 1); 249 tag.mode2.forward = bus; 250 return tag; 251 #endif 252 } 253 254 void 255 pci_decompose_tag(pc, tag, bp, dp, fp) 256 pci_chipset_tag_t pc; 257 pcitag_t tag; 258 int *bp, *dp, *fp; 259 { 260 261 #ifndef PCI_CONF_MODE 262 switch (pci_mode) { 263 case 1: 264 goto mode1; 265 case 2: 266 goto mode2; 267 default: 268 panic("pci_decompose_tag: mode not configured"); 269 } 270 #endif 271 272 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 273 #ifndef PCI_CONF_MODE 274 mode1: 275 #endif 276 if (bp != NULL) 277 *bp = (tag.mode1 >> 16) & 0xff; 278 if (dp != NULL) 279 *dp = (tag.mode1 >> 11) & 0x1f; 280 if (fp != NULL) 281 *fp = (tag.mode1 >> 8) & 0x7; 282 return; 283 #endif 284 285 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 286 #ifndef PCI_CONF_MODE 287 mode2: 288 #endif 289 if (bp != NULL) 290 *bp = tag.mode2.forward & 0xff; 291 if (dp != NULL) 292 *dp = (tag.mode2.port >> 8) & 0xf; 293 if (fp != NULL) 294 *fp = (tag.mode2.enable >> 1) & 0x7; 295 #endif 296 } 297 298 pcireg_t 299 pci_conf_read(pc, tag, reg) 300 pci_chipset_tag_t pc; 301 pcitag_t tag; 302 int reg; 303 { 304 pcireg_t data; 305 int s; 306 307 #ifndef PCI_CONF_MODE 308 switch (pci_mode) { 309 case 1: 310 goto mode1; 311 case 2: 312 goto mode2; 313 default: 314 panic("pci_conf_read: mode not configured"); 315 } 316 #endif 317 318 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 319 #ifndef PCI_CONF_MODE 320 mode1: 321 #endif 322 PCI_CONF_LOCK(s); 323 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 324 data = inl(PCI_MODE1_DATA_REG); 325 outl(PCI_MODE1_ADDRESS_REG, 0); 326 PCI_CONF_UNLOCK(s); 327 return data; 328 #endif 329 330 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 331 #ifndef PCI_CONF_MODE 332 mode2: 333 #endif 334 PCI_CONF_LOCK(s); 335 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 336 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 337 data = inl(tag.mode2.port | reg); 338 outb(PCI_MODE2_ENABLE_REG, 0); 339 PCI_CONF_UNLOCK(s); 340 return data; 341 #endif 342 } 343 344 void 345 pci_conf_write(pc, tag, reg, data) 346 pci_chipset_tag_t pc; 347 pcitag_t tag; 348 int reg; 349 pcireg_t data; 350 { 351 int s; 352 353 #ifndef PCI_CONF_MODE 354 switch (pci_mode) { 355 case 1: 356 goto mode1; 357 case 2: 358 goto mode2; 359 default: 360 panic("pci_conf_write: mode not configured"); 361 } 362 #endif 363 364 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 365 #ifndef PCI_CONF_MODE 366 mode1: 367 #endif 368 PCI_CONF_LOCK(s); 369 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 370 outl(PCI_MODE1_DATA_REG, data); 371 outl(PCI_MODE1_ADDRESS_REG, 0); 372 PCI_CONF_UNLOCK(s); 373 return; 374 #endif 375 376 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 377 #ifndef PCI_CONF_MODE 378 mode2: 379 #endif 380 PCI_CONF_LOCK(s); 381 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 382 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 383 outl(tag.mode2.port | reg, data); 384 outb(PCI_MODE2_ENABLE_REG, 0); 385 PCI_CONF_UNLOCK(s); 386 #endif 387 } 388 389 int 390 pci_mode_detect() 391 { 392 393 #ifdef PCI_CONF_MODE 394 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 395 return (pci_mode = PCI_CONF_MODE); 396 #else 397 #error Invalid PCI configuration mode. 398 #endif 399 #else 400 u_int32_t sav, val; 401 int i; 402 pcireg_t idreg; 403 404 if (pci_mode != -1) 405 return pci_mode; 406 407 /* 408 * We try to divine which configuration mode the host bridge wants. 409 */ 410 411 sav = inl(PCI_MODE1_ADDRESS_REG); 412 413 pci_mode = 1; /* assume this for now */ 414 /* 415 * catch some known buggy implementations of mode 1 416 */ 417 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 418 i++) { 419 pcitag_t t; 420 421 if (!pcim1_quirk_tbl[i].tag) 422 break; 423 t.mode1 = pcim1_quirk_tbl[i].tag; 424 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 425 if (idreg == pcim1_quirk_tbl[i].id) { 426 #ifdef DEBUG 427 printf("known mode 1 PCI chipset (%08x)\n", 428 idreg); 429 #endif 430 return (pci_mode); 431 } 432 } 433 434 /* 435 * Strong check for standard compliant mode 1: 436 * 1. bit 31 ("enable") can be set 437 * 2. byte/word access does not affect register 438 */ 439 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 440 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 441 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 442 val = inl(PCI_MODE1_ADDRESS_REG); 443 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 444 #ifdef DEBUG 445 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 446 val); 447 #endif 448 goto not1; 449 } 450 outl(PCI_MODE1_ADDRESS_REG, 0); 451 val = inl(PCI_MODE1_ADDRESS_REG); 452 if ((val & 0x80fffffc) != 0) 453 goto not1; 454 return (pci_mode); 455 not1: 456 outl(PCI_MODE1_ADDRESS_REG, sav); 457 458 /* 459 * This mode 2 check is quite weak (and known to give false 460 * positives on some Compaq machines). 461 * However, this doesn't matter, because this is the 462 * last test, and simply no PCI devices will be found if 463 * this happens. 464 */ 465 outb(PCI_MODE2_ENABLE_REG, 0); 466 outb(PCI_MODE2_FORWARD_REG, 0); 467 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 468 inb(PCI_MODE2_FORWARD_REG) != 0) 469 goto not2; 470 return (pci_mode = 2); 471 not2: 472 473 return (pci_mode = 0); 474 #endif 475 } 476 477 int 478 pci_intr_map(pa, ihp) 479 struct pci_attach_args *pa; 480 pci_intr_handle_t *ihp; 481 { 482 int pin = pa->pa_intrpin; 483 int line = pa->pa_intrline; 484 #if NIOAPIC > 0 485 int rawpin = pa->pa_rawintrpin; 486 pci_chipset_tag_t pc = pa->pa_pc; 487 int bus, dev, func; 488 #endif 489 490 if (pin == 0) { 491 /* No IRQ used. */ 492 goto bad; 493 } 494 495 if (pin > PCI_INTERRUPT_PIN_MAX) { 496 printf("pci_intr_map: bad interrupt pin %d\n", pin); 497 goto bad; 498 } 499 500 #if NIOAPIC > 0 501 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 502 if (mp_busses != NULL) { 503 if (intr_find_mpmapping(bus, (dev<<2)|(rawpin-1), ihp) == 0) { 504 *ihp |= line; 505 return 0; 506 } 507 /* 508 * No explicit PCI mapping found. This is not fatal, 509 * we'll try the ISA (or possibly EISA) mappings next. 510 */ 511 } 512 #endif 513 514 /* 515 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 516 * `unknown' or `no connection' on a PC. We assume that a device with 517 * `no connection' either doesn't have an interrupt (in which case the 518 * pin number should be 0, and would have been noticed above), or 519 * wasn't configured by the BIOS (in which case we punt, since there's 520 * no real way we can know how the interrupt lines are mapped in the 521 * hardware). 522 * 523 * XXX 524 * Since IRQ 0 is only used by the clock, and we can't actually be sure 525 * that the BIOS did its job, we also recognize that as meaning that 526 * the BIOS has not configured the device. 527 */ 528 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 529 printf("pci_intr_map: no mapping for pin %c (line=%02x)\n", 530 '@' + pin, line); 531 goto bad; 532 } else { 533 if (line >= NUM_LEGACY_IRQS) { 534 printf("pci_intr_map: bad interrupt line %d\n", line); 535 goto bad; 536 } 537 if (line == 2) { 538 printf("pci_intr_map: changed line 2 to line 9\n"); 539 line = 9; 540 } 541 } 542 #if NIOAPIC > 0 543 if (mp_busses != NULL) { 544 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 545 *ihp |= line; 546 return 0; 547 } 548 #if NEISA > 0 549 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 550 *ihp |= line; 551 return 0; 552 } 553 #endif 554 printf("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 555 bus, dev, func, pin, line); 556 printf("pci_intr_map: no MP mapping found\n"); 557 } 558 #endif 559 560 *ihp = line; 561 return 0; 562 563 bad: 564 *ihp = -1; 565 return 1; 566 } 567 568 const char * 569 pci_intr_string(pc, ih) 570 pci_chipset_tag_t pc; 571 pci_intr_handle_t ih; 572 { 573 static char irqstr[64]; 574 575 if (ih == 0) 576 panic("pci_intr_string: bogus handle 0x%x", ih); 577 578 579 #if NIOAPIC > 0 580 if (ih & APIC_INT_VIA_APIC) 581 sprintf(irqstr, "apic %d int %d (irq %d)", 582 APIC_IRQ_APIC(ih), 583 APIC_IRQ_PIN(ih), 584 ih&0xff); 585 else 586 sprintf(irqstr, "irq %d", ih&0xff); 587 #else 588 589 sprintf(irqstr, "irq %d", ih&0xff); 590 #endif 591 return (irqstr); 592 593 } 594 595 const struct evcnt * 596 pci_intr_evcnt(pc, ih) 597 pci_chipset_tag_t pc; 598 pci_intr_handle_t ih; 599 { 600 601 /* XXX for now, no evcnt parent reported */ 602 return NULL; 603 } 604 605 void * 606 pci_intr_establish(pc, ih, level, func, arg) 607 pci_chipset_tag_t pc; 608 pci_intr_handle_t ih; 609 int level, (*func) __P((void *)); 610 void *arg; 611 { 612 int pin, irq; 613 struct pic *pic; 614 615 pic = &i8259_pic; 616 pin = irq = ih; 617 618 #if NIOAPIC > 0 619 if (ih & APIC_INT_VIA_APIC) { 620 pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih)); 621 if (pic == NULL) { 622 printf("pci_intr_establish: bad ioapic %d\n", 623 APIC_IRQ_APIC(ih)); 624 return NULL; 625 } 626 pin = APIC_IRQ_PIN(ih); 627 irq = APIC_IRQ_LEGACY_IRQ(ih); 628 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 629 irq = -1; 630 } 631 #endif 632 633 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg); 634 } 635 636 void 637 pci_intr_disestablish(pc, cookie) 638 pci_chipset_tag_t pc; 639 void *cookie; 640 { 641 642 intr_disestablish(cookie); 643 } 644 645 /* 646 * Determine which flags should be passed to the primary PCI bus's 647 * autoconfiguration node. We use this to detect broken chipsets 648 * which cannot safely use memory-mapped device access. 649 */ 650 int 651 pci_bus_flags() 652 { 653 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 654 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 655 int device, maxndevs; 656 pcitag_t tag; 657 pcireg_t id; 658 659 maxndevs = pci_bus_maxdevs(NULL, 0); 660 661 for (device = 0; device < maxndevs; device++) { 662 tag = pci_make_tag(NULL, 0, device, 0); 663 id = pci_conf_read(NULL, tag, PCI_ID_REG); 664 665 /* Invalid vendor ID value? */ 666 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 667 continue; 668 /* XXX Not invalid, but we've done this ~forever. */ 669 if (PCI_VENDOR(id) == 0) 670 continue; 671 672 switch (PCI_VENDOR(id)) { 673 case PCI_VENDOR_SIS: 674 switch (PCI_PRODUCT(id)) { 675 case PCI_PRODUCT_SIS_85C496: 676 goto disable_mem; 677 } 678 break; 679 } 680 } 681 682 return (rval); 683 684 disable_mem: 685 printf("Warning: broken PCI-Host bridge detected; " 686 "disabling memory-mapped access\n"); 687 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 688 PCI_FLAGS_MWI_OKAY); 689 return (rval); 690 } 691
Indexes created Tue Sep 23 23:09:58 GMT 2025