pci_machdep.c revision 1.20
1 /* $NetBSD: pci_machdep.c,v 1.20 2007/02/06 03:13:37 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Machine-specific functions for PCI autoconfiguration. 72 * 73 * On PCs, there are two methods of generating PCI configuration cycles. 74 * We try to detect the appropriate mechanism for this machine and set 75 * up a few function pointers to access the correct method directly. 76 * 77 * The configuration method can be hard-coded in the config file by 78 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 79 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.20 2007/02/06 03:13:37 jmcneill Exp $"); 84 85 #include <sys/types.h> 86 #include <sys/param.h> 87 #include <sys/time.h> 88 #include <sys/systm.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/lock.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <machine/bus.h> 96 #include <machine/bus_private.h> 97 98 #include <machine/pio.h> 99 100 #include <dev/isa/isareg.h> 101 #include <dev/isa/isavar.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcidevs.h> 105 106 #include "acpi.h" 107 #include "opt_mpbios.h" 108 #include "opt_acpi.h" 109 110 #ifdef MPBIOS 111 #include <machine/mpbiosvar.h> 112 #endif 113 114 #if NACPI > 0 115 #include <machine/mpacpi.h> 116 #endif 117 118 #include <machine/mpconfig.h> 119 120 #include "opt_pci_conf_mode.h" 121 122 #ifdef __i386__ 123 #include "opt_xbox.h" 124 #ifdef XBOX 125 #include <machine/xbox.h> 126 #endif 127 #endif 128 129 int pci_mode = -1; 130 131 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 132 struct pci_bridge_hook_arg { 133 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 134 void *arg; 135 }; 136 137 138 struct simplelock pci_conf_slock = SIMPLELOCK_INITIALIZER; 139 140 #define PCI_CONF_LOCK(s) \ 141 do { \ 142 (s) = splhigh(); \ 143 simple_lock(&pci_conf_slock); \ 144 } while (0) 145 146 #define PCI_CONF_UNLOCK(s) \ 147 do { \ 148 simple_unlock(&pci_conf_slock); \ 149 splx((s)); \ 150 } while (0) 151 152 #define PCI_MODE1_ENABLE 0x80000000UL 153 #define PCI_MODE1_ADDRESS_REG 0x0cf8 154 #define PCI_MODE1_DATA_REG 0x0cfc 155 156 #define PCI_MODE2_ENABLE_REG 0x0cf8 157 #define PCI_MODE2_FORWARD_REG 0x0cfa 158 159 #define _m1tag(b, d, f) \ 160 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 161 #define _qe(bus, dev, fcn, vend, prod) \ 162 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 163 struct { 164 u_int32_t tag; 165 pcireg_t id; 166 } pcim1_quirk_tbl[] = { 167 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 168 /* XXX Triflex2 not tested */ 169 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 170 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 171 /* Triton needed for Connectix Virtual PC */ 172 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 173 /* Connectix Virtual PC 5 has a 440BX */ 174 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 175 /* Parallels Desktop for Mac */ 176 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 177 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 178 /* SIS 741 */ 179 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 180 {0, 0xffffffff} /* patchable */ 181 }; 182 #undef _m1tag 183 #undef _id 184 #undef _qe 185 186 /* 187 * PCI doesn't have any special needs; just use the generic versions 188 * of these functions. 189 */ 190 struct x86_bus_dma_tag pci_bus_dma_tag = { 191 #if defined(_LP64) || defined(PAE) 192 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 193 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 194 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 195 #else 196 0, 197 0, 198 0, 199 #endif 200 NULL, /* _may_bounce */ 201 _bus_dmamap_create, 202 _bus_dmamap_destroy, 203 _bus_dmamap_load, 204 _bus_dmamap_load_mbuf, 205 _bus_dmamap_load_uio, 206 _bus_dmamap_load_raw, 207 _bus_dmamap_unload, 208 #if defined(_LP64) || defined(PAE) 209 _bus_dmamap_sync, 210 #else 211 NULL, 212 #endif 213 _bus_dmamem_alloc, 214 _bus_dmamem_free, 215 _bus_dmamem_map, 216 _bus_dmamem_unmap, 217 _bus_dmamem_mmap, 218 }; 219 220 #ifdef _LP64 221 struct x86_bus_dma_tag pci_bus_dma64_tag = { 222 0, 223 0, 224 0, 225 NULL, /* _may_bounce */ 226 _bus_dmamap_create, 227 _bus_dmamap_destroy, 228 _bus_dmamap_load, 229 _bus_dmamap_load_mbuf, 230 _bus_dmamap_load_uio, 231 _bus_dmamap_load_raw, 232 _bus_dmamap_unload, 233 NULL, 234 _bus_dmamem_alloc, 235 _bus_dmamem_free, 236 _bus_dmamem_map, 237 _bus_dmamem_unmap, 238 _bus_dmamem_mmap, 239 }; 240 #endif 241 242 void 243 pci_attach_hook(struct device *parent, struct device *self, 244 struct pcibus_attach_args *pba) 245 { 246 247 if (pba->pba_bus == 0) 248 printf(": configuration mode %d", pci_mode); 249 #ifdef MPBIOS 250 mpbios_pci_attach_hook(parent, self, pba); 251 #endif 252 #if NACPI > 0 253 mpacpi_pci_attach_hook(parent, self, pba); 254 #endif 255 } 256 257 int 258 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 259 { 260 261 #if defined(__i386__) && defined(XBOX) 262 /* 263 * Scanning above the first device is fatal on the Microsoft Xbox. 264 * If busno=1, only allow for one device. 265 */ 266 if (arch_i386_is_xbox) { 267 if (busno == 1) 268 return 1; 269 else if (busno > 1) 270 return 0; 271 } 272 #endif 273 274 /* 275 * Bus number is irrelevant. If Configuration Mechanism 2 is in 276 * use, can only have devices 0-15 on any bus. If Configuration 277 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 278 * range). 279 */ 280 if (pci_mode == 2) 281 return (16); 282 else 283 return (32); 284 } 285 286 pcitag_t 287 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 288 { 289 pcitag_t tag; 290 291 #ifndef PCI_CONF_MODE 292 switch (pci_mode) { 293 case 1: 294 goto mode1; 295 case 2: 296 goto mode2; 297 default: 298 panic("pci_make_tag: mode not configured"); 299 } 300 #endif 301 302 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 303 #ifndef PCI_CONF_MODE 304 mode1: 305 #endif 306 if (bus >= 256 || device >= 32 || function >= 8) 307 panic("pci_make_tag: bad request"); 308 309 tag.mode1 = PCI_MODE1_ENABLE | 310 (bus << 16) | (device << 11) | (function << 8); 311 return tag; 312 #endif 313 314 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 315 #ifndef PCI_CONF_MODE 316 mode2: 317 #endif 318 if (bus >= 256 || device >= 16 || function >= 8) 319 panic("pci_make_tag: bad request"); 320 321 tag.mode2.port = 0xc000 | (device << 8); 322 tag.mode2.enable = 0xf0 | (function << 1); 323 tag.mode2.forward = bus; 324 return tag; 325 #endif 326 } 327 328 void 329 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 330 int *bp, int *dp, int *fp) 331 { 332 333 #ifndef PCI_CONF_MODE 334 switch (pci_mode) { 335 case 1: 336 goto mode1; 337 case 2: 338 goto mode2; 339 default: 340 panic("pci_decompose_tag: mode not configured"); 341 } 342 #endif 343 344 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 345 #ifndef PCI_CONF_MODE 346 mode1: 347 #endif 348 if (bp != NULL) 349 *bp = (tag.mode1 >> 16) & 0xff; 350 if (dp != NULL) 351 *dp = (tag.mode1 >> 11) & 0x1f; 352 if (fp != NULL) 353 *fp = (tag.mode1 >> 8) & 0x7; 354 return; 355 #endif 356 357 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 358 #ifndef PCI_CONF_MODE 359 mode2: 360 #endif 361 if (bp != NULL) 362 *bp = tag.mode2.forward & 0xff; 363 if (dp != NULL) 364 *dp = (tag.mode2.port >> 8) & 0xf; 365 if (fp != NULL) 366 *fp = (tag.mode2.enable >> 1) & 0x7; 367 #endif 368 } 369 370 pcireg_t 371 pci_conf_read( pci_chipset_tag_t pc, pcitag_t tag, 372 int reg) 373 { 374 pcireg_t data; 375 int s; 376 377 #if defined(__i386__) && defined(XBOX) 378 if (arch_i386_is_xbox) { 379 int bus, dev, fn; 380 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 381 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 382 return (pcireg_t)-1; 383 } 384 #endif 385 386 #ifndef PCI_CONF_MODE 387 switch (pci_mode) { 388 case 1: 389 goto mode1; 390 case 2: 391 goto mode2; 392 default: 393 panic("pci_conf_read: mode not configured"); 394 } 395 #endif 396 397 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 398 #ifndef PCI_CONF_MODE 399 mode1: 400 #endif 401 PCI_CONF_LOCK(s); 402 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 403 data = inl(PCI_MODE1_DATA_REG); 404 outl(PCI_MODE1_ADDRESS_REG, 0); 405 PCI_CONF_UNLOCK(s); 406 return data; 407 #endif 408 409 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 410 #ifndef PCI_CONF_MODE 411 mode2: 412 #endif 413 PCI_CONF_LOCK(s); 414 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 415 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 416 data = inl(tag.mode2.port | reg); 417 outb(PCI_MODE2_ENABLE_REG, 0); 418 PCI_CONF_UNLOCK(s); 419 return data; 420 #endif 421 } 422 423 void 424 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, 425 pcireg_t data) 426 { 427 int s; 428 429 #if defined(__i386__) && defined(XBOX) 430 if (arch_i386_is_xbox) { 431 int bus, dev, fn; 432 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 433 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 434 return; 435 } 436 #endif 437 438 #ifndef PCI_CONF_MODE 439 switch (pci_mode) { 440 case 1: 441 goto mode1; 442 case 2: 443 goto mode2; 444 default: 445 panic("pci_conf_write: mode not configured"); 446 } 447 #endif 448 449 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 450 #ifndef PCI_CONF_MODE 451 mode1: 452 #endif 453 PCI_CONF_LOCK(s); 454 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 455 outl(PCI_MODE1_DATA_REG, data); 456 outl(PCI_MODE1_ADDRESS_REG, 0); 457 PCI_CONF_UNLOCK(s); 458 return; 459 #endif 460 461 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 462 #ifndef PCI_CONF_MODE 463 mode2: 464 #endif 465 PCI_CONF_LOCK(s); 466 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 467 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 468 outl(tag.mode2.port | reg, data); 469 outb(PCI_MODE2_ENABLE_REG, 0); 470 PCI_CONF_UNLOCK(s); 471 #endif 472 } 473 474 int 475 pci_mode_detect() 476 { 477 478 #ifdef PCI_CONF_MODE 479 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 480 return (pci_mode = PCI_CONF_MODE); 481 #else 482 #error Invalid PCI configuration mode. 483 #endif 484 #else 485 u_int32_t sav, val; 486 int i; 487 pcireg_t idreg; 488 489 if (pci_mode != -1) 490 return pci_mode; 491 492 /* 493 * We try to divine which configuration mode the host bridge wants. 494 */ 495 496 sav = inl(PCI_MODE1_ADDRESS_REG); 497 498 pci_mode = 1; /* assume this for now */ 499 /* 500 * catch some known buggy implementations of mode 1 501 */ 502 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 503 i++) { 504 pcitag_t t; 505 506 if (!pcim1_quirk_tbl[i].tag) 507 break; 508 t.mode1 = pcim1_quirk_tbl[i].tag; 509 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 510 if (idreg == pcim1_quirk_tbl[i].id) { 511 #ifdef DEBUG 512 printf("known mode 1 PCI chipset (%08x)\n", 513 idreg); 514 #endif 515 return (pci_mode); 516 } 517 } 518 519 /* 520 * Strong check for standard compliant mode 1: 521 * 1. bit 31 ("enable") can be set 522 * 2. byte/word access does not affect register 523 */ 524 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 525 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 526 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 527 val = inl(PCI_MODE1_ADDRESS_REG); 528 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 529 #ifdef DEBUG 530 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 531 val); 532 #endif 533 goto not1; 534 } 535 outl(PCI_MODE1_ADDRESS_REG, 0); 536 val = inl(PCI_MODE1_ADDRESS_REG); 537 if ((val & 0x80fffffc) != 0) 538 goto not1; 539 return (pci_mode); 540 not1: 541 outl(PCI_MODE1_ADDRESS_REG, sav); 542 543 /* 544 * This mode 2 check is quite weak (and known to give false 545 * positives on some Compaq machines). 546 * However, this doesn't matter, because this is the 547 * last test, and simply no PCI devices will be found if 548 * this happens. 549 */ 550 outb(PCI_MODE2_ENABLE_REG, 0); 551 outb(PCI_MODE2_FORWARD_REG, 0); 552 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 553 inb(PCI_MODE2_FORWARD_REG) != 0) 554 goto not2; 555 return (pci_mode = 2); 556 not2: 557 558 return (pci_mode = 0); 559 #endif 560 } 561 562 /* 563 * Determine which flags should be passed to the primary PCI bus's 564 * autoconfiguration node. We use this to detect broken chipsets 565 * which cannot safely use memory-mapped device access. 566 */ 567 int 568 pci_bus_flags() 569 { 570 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 571 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 572 int device, maxndevs; 573 pcitag_t tag; 574 pcireg_t id; 575 576 maxndevs = pci_bus_maxdevs(NULL, 0); 577 578 for (device = 0; device < maxndevs; device++) { 579 tag = pci_make_tag(NULL, 0, device, 0); 580 id = pci_conf_read(NULL, tag, PCI_ID_REG); 581 582 /* Invalid vendor ID value? */ 583 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 584 continue; 585 /* XXX Not invalid, but we've done this ~forever. */ 586 if (PCI_VENDOR(id) == 0) 587 continue; 588 589 switch (PCI_VENDOR(id)) { 590 case PCI_VENDOR_SIS: 591 switch (PCI_PRODUCT(id)) { 592 case PCI_PRODUCT_SIS_85C496: 593 goto disable_mem; 594 } 595 break; 596 } 597 } 598 599 return (rval); 600 601 disable_mem: 602 printf("Warning: broken PCI-Host bridge detected; " 603 "disabling memory-mapped access\n"); 604 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 605 PCI_FLAGS_MWI_OKAY); 606 return (rval); 607 } 608 609 void 610 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 611 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 612 { 613 pci_device_foreach_min(pc, 0, maxbus, func, context); 614 } 615 616 void 617 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 618 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 619 { 620 const struct pci_quirkdata *qd; 621 int bus, device, function, maxdevs, nfuncs; 622 pcireg_t id, bhlcr; 623 pcitag_t tag; 624 625 for (bus = minbus; bus <= maxbus; bus++) { 626 maxdevs = pci_bus_maxdevs(pc, bus); 627 for (device = 0; device < maxdevs; device++) { 628 tag = pci_make_tag(pc, bus, device, 0); 629 id = pci_conf_read(pc, tag, PCI_ID_REG); 630 631 /* Invalid vendor ID value? */ 632 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 633 continue; 634 /* XXX Not invalid, but we've done this ~forever. */ 635 if (PCI_VENDOR(id) == 0) 636 continue; 637 638 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 639 PCI_PRODUCT(id)); 640 641 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 642 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 643 (qd != NULL && 644 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 645 nfuncs = 8; 646 else 647 nfuncs = 1; 648 649 for (function = 0; function < nfuncs; function++) { 650 tag = pci_make_tag(pc, bus, device, function); 651 id = pci_conf_read(pc, tag, PCI_ID_REG); 652 653 /* Invalid vendor ID value? */ 654 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 655 continue; 656 /* 657 * XXX Not invalid, but we've done this 658 * ~forever. 659 */ 660 if (PCI_VENDOR(id) == 0) 661 continue; 662 (*func)(pc, tag, context); 663 } 664 } 665 } 666 } 667 668 void 669 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 670 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 671 { 672 struct pci_bridge_hook_arg bridge_hook; 673 674 bridge_hook.func = func; 675 bridge_hook.arg = ctx; 676 677 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 678 &bridge_hook); 679 } 680 681 static void 682 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 683 { 684 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 685 pcireg_t reg; 686 687 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 688 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 689 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 690 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 691 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 692 } 693 } 694
Indexes created Fri Sep 26 08:10:20 GMT 2025