pci_machdep.c revision 1.3
1 /* $NetBSD: pci_machdep.c,v 1.3 2003/05/07 21:33:58 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Machine-specific functions for PCI autoconfiguration. 72 * 73 * On PCs, there are two methods of generating PCI configuration cycles. 74 * We try to detect the appropriate mechanism for this machine and set 75 * up a few function pointers to access the correct method directly. 76 * 77 * The configuration method can be hard-coded in the config file by 78 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 79 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.3 2003/05/07 21:33:58 fvdl Exp $"); 84 85 #include <sys/types.h> 86 #include <sys/param.h> 87 #include <sys/time.h> 88 #include <sys/systm.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/lock.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #define _X86_BUS_DMA_PRIVATE 96 #include <machine/bus.h> 97 98 #include <machine/pio.h> 99 #include <machine/intr.h> 100 101 #include <dev/isa/isareg.h> 102 #include <dev/isa/isavar.h> 103 #include <dev/pci/pcivar.h> 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcidevs.h> 106 107 #include "ioapic.h" 108 #include "eisa.h" 109 110 #if NIOAPIC > 0 111 #include <machine/i82093var.h> 112 #include <machine/mpbiosvar.h> 113 #endif 114 115 #include "opt_pci_conf_mode.h" 116 117 int pci_mode = -1; 118 119 struct simplelock pci_conf_slock = SIMPLELOCK_INITIALIZER; 120 121 #define PCI_CONF_LOCK(s) \ 122 do { \ 123 (s) = splhigh(); \ 124 simple_lock(&pci_conf_slock); \ 125 } while (0) 126 127 #define PCI_CONF_UNLOCK(s) \ 128 do { \ 129 simple_unlock(&pci_conf_slock); \ 130 splx((s)); \ 131 } while (0) 132 133 #define PCI_MODE1_ENABLE 0x80000000UL 134 #define PCI_MODE1_ADDRESS_REG 0x0cf8 135 #define PCI_MODE1_DATA_REG 0x0cfc 136 137 #define PCI_MODE2_ENABLE_REG 0x0cf8 138 #define PCI_MODE2_FORWARD_REG 0x0cfa 139 140 #define _m1tag(b, d, f) \ 141 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 142 #define _qe(bus, dev, fcn, vend, prod) \ 143 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 144 struct { 145 u_int32_t tag; 146 pcireg_t id; 147 } pcim1_quirk_tbl[] = { 148 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 149 /* XXX Triflex2 not tested */ 150 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 151 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 152 /* Triton needed for Connectix Virtual PC */ 153 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 154 /* Connectix Virtual PC 5 has a 440BX */ 155 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 156 {0, 0xffffffff} /* patchable */ 157 }; 158 #undef _m1tag 159 #undef _id 160 #undef _qe 161 162 /* 163 * PCI doesn't have any special needs; just use the generic versions 164 * of these functions. 165 */ 166 struct x86_bus_dma_tag pci_bus_dma_tag = { 167 #if defined(_LP64) || defined(PAE) 168 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 169 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 170 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 171 #else 172 0, 173 0, 174 0, 175 #endif 176 NULL, /* _may_bounce */ 177 _bus_dmamap_create, 178 _bus_dmamap_destroy, 179 _bus_dmamap_load, 180 _bus_dmamap_load_mbuf, 181 _bus_dmamap_load_uio, 182 _bus_dmamap_load_raw, 183 _bus_dmamap_unload, 184 #if defined(_LP64) || defined(PAE) 185 _bus_dmamap_sync, 186 #else 187 NULL, 188 #endif 189 _bus_dmamem_alloc, 190 _bus_dmamem_free, 191 _bus_dmamem_map, 192 _bus_dmamem_unmap, 193 _bus_dmamem_mmap, 194 }; 195 196 void 197 pci_attach_hook(parent, self, pba) 198 struct device *parent, *self; 199 struct pcibus_attach_args *pba; 200 { 201 202 if (pba->pba_bus == 0) 203 printf(": configuration mode %d", pci_mode); 204 } 205 206 int 207 pci_bus_maxdevs(pc, busno) 208 pci_chipset_tag_t pc; 209 int busno; 210 { 211 212 /* 213 * Bus number is irrelevant. If Configuration Mechanism 2 is in 214 * use, can only have devices 0-15 on any bus. If Configuration 215 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 216 * range). 217 */ 218 if (pci_mode == 2) 219 return (16); 220 else 221 return (32); 222 } 223 224 pcitag_t 225 pci_make_tag(pc, bus, device, function) 226 pci_chipset_tag_t pc; 227 int bus, device, function; 228 { 229 pcitag_t tag; 230 231 #ifndef PCI_CONF_MODE 232 switch (pci_mode) { 233 case 1: 234 goto mode1; 235 case 2: 236 goto mode2; 237 default: 238 panic("pci_make_tag: mode not configured"); 239 } 240 #endif 241 242 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 243 #ifndef PCI_CONF_MODE 244 mode1: 245 #endif 246 if (bus >= 256 || device >= 32 || function >= 8) 247 panic("pci_make_tag: bad request"); 248 249 tag.mode1 = PCI_MODE1_ENABLE | 250 (bus << 16) | (device << 11) | (function << 8); 251 return tag; 252 #endif 253 254 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 255 #ifndef PCI_CONF_MODE 256 mode2: 257 #endif 258 if (bus >= 256 || device >= 16 || function >= 8) 259 panic("pci_make_tag: bad request"); 260 261 tag.mode2.port = 0xc000 | (device << 8); 262 tag.mode2.enable = 0xf0 | (function << 1); 263 tag.mode2.forward = bus; 264 return tag; 265 #endif 266 } 267 268 void 269 pci_decompose_tag(pc, tag, bp, dp, fp) 270 pci_chipset_tag_t pc; 271 pcitag_t tag; 272 int *bp, *dp, *fp; 273 { 274 275 #ifndef PCI_CONF_MODE 276 switch (pci_mode) { 277 case 1: 278 goto mode1; 279 case 2: 280 goto mode2; 281 default: 282 panic("pci_decompose_tag: mode not configured"); 283 } 284 #endif 285 286 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 287 #ifndef PCI_CONF_MODE 288 mode1: 289 #endif 290 if (bp != NULL) 291 *bp = (tag.mode1 >> 16) & 0xff; 292 if (dp != NULL) 293 *dp = (tag.mode1 >> 11) & 0x1f; 294 if (fp != NULL) 295 *fp = (tag.mode1 >> 8) & 0x7; 296 return; 297 #endif 298 299 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 300 #ifndef PCI_CONF_MODE 301 mode2: 302 #endif 303 if (bp != NULL) 304 *bp = tag.mode2.forward & 0xff; 305 if (dp != NULL) 306 *dp = (tag.mode2.port >> 8) & 0xf; 307 if (fp != NULL) 308 *fp = (tag.mode2.enable >> 1) & 0x7; 309 #endif 310 } 311 312 pcireg_t 313 pci_conf_read(pc, tag, reg) 314 pci_chipset_tag_t pc; 315 pcitag_t tag; 316 int reg; 317 { 318 pcireg_t data; 319 int s; 320 321 #ifndef PCI_CONF_MODE 322 switch (pci_mode) { 323 case 1: 324 goto mode1; 325 case 2: 326 goto mode2; 327 default: 328 panic("pci_conf_read: mode not configured"); 329 } 330 #endif 331 332 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 333 #ifndef PCI_CONF_MODE 334 mode1: 335 #endif 336 PCI_CONF_LOCK(s); 337 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 338 data = inl(PCI_MODE1_DATA_REG); 339 outl(PCI_MODE1_ADDRESS_REG, 0); 340 PCI_CONF_UNLOCK(s); 341 return data; 342 #endif 343 344 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 345 #ifndef PCI_CONF_MODE 346 mode2: 347 #endif 348 PCI_CONF_LOCK(s); 349 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 350 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 351 data = inl(tag.mode2.port | reg); 352 outb(PCI_MODE2_ENABLE_REG, 0); 353 PCI_CONF_UNLOCK(s); 354 return data; 355 #endif 356 } 357 358 void 359 pci_conf_write(pc, tag, reg, data) 360 pci_chipset_tag_t pc; 361 pcitag_t tag; 362 int reg; 363 pcireg_t data; 364 { 365 int s; 366 367 #ifndef PCI_CONF_MODE 368 switch (pci_mode) { 369 case 1: 370 goto mode1; 371 case 2: 372 goto mode2; 373 default: 374 panic("pci_conf_write: mode not configured"); 375 } 376 #endif 377 378 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 379 #ifndef PCI_CONF_MODE 380 mode1: 381 #endif 382 PCI_CONF_LOCK(s); 383 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 384 outl(PCI_MODE1_DATA_REG, data); 385 outl(PCI_MODE1_ADDRESS_REG, 0); 386 PCI_CONF_UNLOCK(s); 387 return; 388 #endif 389 390 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 391 #ifndef PCI_CONF_MODE 392 mode2: 393 #endif 394 PCI_CONF_LOCK(s); 395 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 396 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 397 outl(tag.mode2.port | reg, data); 398 outb(PCI_MODE2_ENABLE_REG, 0); 399 PCI_CONF_UNLOCK(s); 400 #endif 401 } 402 403 int 404 pci_mode_detect() 405 { 406 407 #ifdef PCI_CONF_MODE 408 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 409 return (pci_mode = PCI_CONF_MODE); 410 #else 411 #error Invalid PCI configuration mode. 412 #endif 413 #else 414 u_int32_t sav, val; 415 int i; 416 pcireg_t idreg; 417 418 if (pci_mode != -1) 419 return pci_mode; 420 421 /* 422 * We try to divine which configuration mode the host bridge wants. 423 */ 424 425 sav = inl(PCI_MODE1_ADDRESS_REG); 426 427 pci_mode = 1; /* assume this for now */ 428 /* 429 * catch some known buggy implementations of mode 1 430 */ 431 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 432 i++) { 433 pcitag_t t; 434 435 if (!pcim1_quirk_tbl[i].tag) 436 break; 437 t.mode1 = pcim1_quirk_tbl[i].tag; 438 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 439 if (idreg == pcim1_quirk_tbl[i].id) { 440 #ifdef DEBUG 441 printf("known mode 1 PCI chipset (%08x)\n", 442 idreg); 443 #endif 444 return (pci_mode); 445 } 446 } 447 448 /* 449 * Strong check for standard compliant mode 1: 450 * 1. bit 31 ("enable") can be set 451 * 2. byte/word access does not affect register 452 */ 453 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 454 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 455 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 456 val = inl(PCI_MODE1_ADDRESS_REG); 457 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 458 #ifdef DEBUG 459 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 460 val); 461 #endif 462 goto not1; 463 } 464 outl(PCI_MODE1_ADDRESS_REG, 0); 465 val = inl(PCI_MODE1_ADDRESS_REG); 466 if ((val & 0x80fffffc) != 0) 467 goto not1; 468 return (pci_mode); 469 not1: 470 outl(PCI_MODE1_ADDRESS_REG, sav); 471 472 /* 473 * This mode 2 check is quite weak (and known to give false 474 * positives on some Compaq machines). 475 * However, this doesn't matter, because this is the 476 * last test, and simply no PCI devices will be found if 477 * this happens. 478 */ 479 outb(PCI_MODE2_ENABLE_REG, 0); 480 outb(PCI_MODE2_FORWARD_REG, 0); 481 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 482 inb(PCI_MODE2_FORWARD_REG) != 0) 483 goto not2; 484 return (pci_mode = 2); 485 not2: 486 487 return (pci_mode = 0); 488 #endif 489 } 490 491 int 492 pci_intr_map(pa, ihp) 493 struct pci_attach_args *pa; 494 pci_intr_handle_t *ihp; 495 { 496 int pin = pa->pa_intrpin; 497 int line = pa->pa_intrline; 498 #if NIOAPIC > 0 499 int rawpin = pa->pa_rawintrpin; 500 pci_chipset_tag_t pc = pa->pa_pc; 501 int bus, dev, func; 502 #endif 503 504 if (pin == 0) { 505 /* No IRQ used. */ 506 goto bad; 507 } 508 509 if (pin > PCI_INTERRUPT_PIN_MAX) { 510 printf("pci_intr_map: bad interrupt pin %d\n", pin); 511 goto bad; 512 } 513 514 #if NIOAPIC > 0 515 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 516 if (mp_busses != NULL) { 517 if (intr_find_mpmapping(bus, (dev<<2)|(rawpin-1), ihp) == 0) { 518 *ihp |= line; 519 return 0; 520 } 521 /* 522 * No explicit PCI mapping found. This is not fatal, 523 * we'll try the ISA (or possibly EISA) mappings next. 524 */ 525 } 526 #endif 527 528 /* 529 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 530 * `unknown' or `no connection' on a PC. We assume that a device with 531 * `no connection' either doesn't have an interrupt (in which case the 532 * pin number should be 0, and would have been noticed above), or 533 * wasn't configured by the BIOS (in which case we punt, since there's 534 * no real way we can know how the interrupt lines are mapped in the 535 * hardware). 536 * 537 * XXX 538 * Since IRQ 0 is only used by the clock, and we can't actually be sure 539 * that the BIOS did its job, we also recognize that as meaning that 540 * the BIOS has not configured the device. 541 */ 542 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 543 printf("pci_intr_map: no mapping for pin %c (line=%02x)\n", 544 '@' + pin, line); 545 goto bad; 546 } else { 547 if (line >= NUM_LEGACY_IRQS) { 548 printf("pci_intr_map: bad interrupt line %d\n", line); 549 goto bad; 550 } 551 if (line == 2) { 552 printf("pci_intr_map: changed line 2 to line 9\n"); 553 line = 9; 554 } 555 } 556 #if NIOAPIC > 0 557 if (mp_busses != NULL) { 558 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 559 *ihp |= line; 560 return 0; 561 } 562 #if NEISA > 0 563 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 564 *ihp |= line; 565 return 0; 566 } 567 #endif 568 printf("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 569 bus, dev, func, pin, line); 570 printf("pci_intr_map: no MP mapping found\n"); 571 } 572 #endif 573 574 *ihp = line; 575 return 0; 576 577 bad: 578 *ihp = -1; 579 return 1; 580 } 581 582 const char * 583 pci_intr_string(pc, ih) 584 pci_chipset_tag_t pc; 585 pci_intr_handle_t ih; 586 { 587 static char irqstr[64]; 588 589 if (ih == 0) 590 panic("pci_intr_string: bogus handle 0x%x", ih); 591 592 593 #if NIOAPIC > 0 594 if (ih & APIC_INT_VIA_APIC) 595 sprintf(irqstr, "apic %d int %d (irq %d)", 596 APIC_IRQ_APIC(ih), 597 APIC_IRQ_PIN(ih), 598 ih&0xff); 599 else 600 sprintf(irqstr, "irq %d", ih&0xff); 601 #else 602 603 sprintf(irqstr, "irq %d", ih&0xff); 604 #endif 605 return (irqstr); 606 607 } 608 609 const struct evcnt * 610 pci_intr_evcnt(pc, ih) 611 pci_chipset_tag_t pc; 612 pci_intr_handle_t ih; 613 { 614 615 /* XXX for now, no evcnt parent reported */ 616 return NULL; 617 } 618 619 void * 620 pci_intr_establish(pc, ih, level, func, arg) 621 pci_chipset_tag_t pc; 622 pci_intr_handle_t ih; 623 int level, (*func) __P((void *)); 624 void *arg; 625 { 626 int pin, irq; 627 struct pic *pic; 628 629 pic = &i8259_pic; 630 pin = irq = ih; 631 632 #if NIOAPIC > 0 633 if (ih & APIC_INT_VIA_APIC) { 634 pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih)); 635 if (pic == NULL) { 636 printf("pci_intr_establish: bad ioapic %d\n", 637 APIC_IRQ_APIC(ih)); 638 return NULL; 639 } 640 pin = APIC_IRQ_PIN(ih); 641 irq = APIC_IRQ_LEGACY_IRQ(ih); 642 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 643 irq = -1; 644 } 645 #endif 646 647 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg); 648 } 649 650 void 651 pci_intr_disestablish(pc, cookie) 652 pci_chipset_tag_t pc; 653 void *cookie; 654 { 655 656 intr_disestablish(cookie); 657 } 658 659 /* 660 * Determine which flags should be passed to the primary PCI bus's 661 * autoconfiguration node. We use this to detect broken chipsets 662 * which cannot safely use memory-mapped device access. 663 */ 664 int 665 pci_bus_flags() 666 { 667 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 668 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 669 int device, maxndevs; 670 pcitag_t tag; 671 pcireg_t id; 672 673 maxndevs = pci_bus_maxdevs(NULL, 0); 674 675 for (device = 0; device < maxndevs; device++) { 676 tag = pci_make_tag(NULL, 0, device, 0); 677 id = pci_conf_read(NULL, tag, PCI_ID_REG); 678 679 /* Invalid vendor ID value? */ 680 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 681 continue; 682 /* XXX Not invalid, but we've done this ~forever. */ 683 if (PCI_VENDOR(id) == 0) 684 continue; 685 686 switch (PCI_VENDOR(id)) { 687 case PCI_VENDOR_SIS: 688 switch (PCI_PRODUCT(id)) { 689 case PCI_PRODUCT_SIS_85C496: 690 goto disable_mem; 691 } 692 break; 693 } 694 } 695 696 return (rval); 697 698 disable_mem: 699 printf("Warning: broken PCI-Host bridge detected; " 700 "disabling memory-mapped access\n"); 701 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 702 PCI_FLAGS_MWI_OKAY); 703 return (rval); 704 } 705
Indexes created Tue Sep 23 14:10:03 GMT 2025