pci_machdep.c revision 1.31
1 /* $NetBSD: pci_machdep.c,v 1.31 2008/01/14 18:44:17 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Machine-specific functions for PCI autoconfiguration. 72 * 73 * On PCs, there are two methods of generating PCI configuration cycles. 74 * We try to detect the appropriate mechanism for this machine and set 75 * up a few function pointers to access the correct method directly. 76 * 77 * The configuration method can be hard-coded in the config file by 78 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 79 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.31 2008/01/14 18:44:17 dyoung Exp $"); 84 85 #include <sys/types.h> 86 #include <sys/param.h> 87 #include <sys/time.h> 88 #include <sys/systm.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/bus.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <machine/bus_private.h> 96 97 #include <machine/pio.h> 98 #include <machine/lock.h> 99 100 #include <dev/isa/isareg.h> 101 #include <dev/isa/isavar.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcidevs.h> 105 106 #include "acpi.h" 107 #include "opt_mpbios.h" 108 #include "opt_acpi.h" 109 110 #ifdef MPBIOS 111 #include <machine/mpbiosvar.h> 112 #endif 113 114 #if NACPI > 0 115 #include <machine/mpacpi.h> 116 #endif 117 118 #include <machine/mpconfig.h> 119 120 #include "opt_pci_conf_mode.h" 121 122 #ifdef __i386__ 123 #include "opt_xbox.h" 124 #ifdef XBOX 125 #include <machine/xbox.h> 126 #endif 127 #endif 128 129 int pci_mode = -1; 130 131 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 132 struct pci_bridge_hook_arg { 133 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 134 void *arg; 135 }; 136 137 138 __cpu_simple_lock_t pci_conf_lock = __SIMPLELOCK_UNLOCKED; 139 140 #define PCI_CONF_LOCK(s) \ 141 do { \ 142 (s) = splhigh(); \ 143 __cpu_simple_lock(&pci_conf_lock); \ 144 } while (0) 145 146 #define PCI_CONF_UNLOCK(s) \ 147 do { \ 148 __cpu_simple_unlock(&pci_conf_lock); \ 149 splx((s)); \ 150 } while (0) 151 152 #define PCI_MODE1_ENABLE 0x80000000UL 153 #define PCI_MODE1_ADDRESS_REG 0x0cf8 154 #define PCI_MODE1_DATA_REG 0x0cfc 155 156 #define PCI_MODE2_ENABLE_REG 0x0cf8 157 #define PCI_MODE2_FORWARD_REG 0x0cfa 158 159 #define _m1tag(b, d, f) \ 160 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 161 #define _qe(bus, dev, fcn, vend, prod) \ 162 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 163 struct { 164 u_int32_t tag; 165 pcireg_t id; 166 } pcim1_quirk_tbl[] = { 167 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 168 /* XXX Triflex2 not tested */ 169 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 170 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 171 /* Triton needed for Connectix Virtual PC */ 172 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 173 /* Connectix Virtual PC 5 has a 440BX */ 174 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 175 /* Parallels Desktop for Mac */ 176 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 177 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 178 /* SIS 741 */ 179 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 180 {0, 0xffffffff} /* patchable */ 181 }; 182 #undef _m1tag 183 #undef _id 184 #undef _qe 185 186 /* 187 * PCI doesn't have any special needs; just use the generic versions 188 * of these functions. 189 */ 190 struct x86_bus_dma_tag pci_bus_dma_tag = { 191 0, /* tag_needs_free */ 192 #if defined(_LP64) || defined(PAE) 193 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 194 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 195 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 196 #else 197 0, 198 0, 199 0, 200 #endif 201 NULL, /* _may_bounce */ 202 _bus_dmamap_create, 203 _bus_dmamap_destroy, 204 _bus_dmamap_load, 205 _bus_dmamap_load_mbuf, 206 _bus_dmamap_load_uio, 207 _bus_dmamap_load_raw, 208 _bus_dmamap_unload, 209 _bus_dmamap_sync, 210 _bus_dmamem_alloc, 211 _bus_dmamem_free, 212 _bus_dmamem_map, 213 _bus_dmamem_unmap, 214 _bus_dmamem_mmap, 215 _bus_dmatag_subregion, 216 _bus_dmatag_destroy, 217 }; 218 219 #ifdef _LP64 220 struct x86_bus_dma_tag pci_bus_dma64_tag = { 221 0, /* tag_needs_free */ 222 0, 223 0, 224 0, 225 NULL, /* _may_bounce */ 226 _bus_dmamap_create, 227 _bus_dmamap_destroy, 228 _bus_dmamap_load, 229 _bus_dmamap_load_mbuf, 230 _bus_dmamap_load_uio, 231 _bus_dmamap_load_raw, 232 _bus_dmamap_unload, 233 NULL, 234 _bus_dmamem_alloc, 235 _bus_dmamem_free, 236 _bus_dmamem_map, 237 _bus_dmamem_unmap, 238 _bus_dmamem_mmap, 239 _bus_dmatag_subregion, 240 _bus_dmatag_destroy, 241 }; 242 #endif 243 244 void 245 pci_attach_hook(struct device *parent, struct device *self, 246 struct pcibus_attach_args *pba) 247 { 248 249 if (pba->pba_bus == 0) 250 aprint_normal(": configuration mode %d", pci_mode); 251 #ifdef MPBIOS 252 mpbios_pci_attach_hook(parent, self, pba); 253 #endif 254 #if NACPI > 0 255 mpacpi_pci_attach_hook(parent, self, pba); 256 #endif 257 } 258 259 int 260 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 261 { 262 263 #if defined(__i386__) && defined(XBOX) 264 /* 265 * Scanning above the first device is fatal on the Microsoft Xbox. 266 * If busno=1, only allow for one device. 267 */ 268 if (arch_i386_is_xbox) { 269 if (busno == 1) 270 return 1; 271 else if (busno > 1) 272 return 0; 273 } 274 #endif 275 276 /* 277 * Bus number is irrelevant. If Configuration Mechanism 2 is in 278 * use, can only have devices 0-15 on any bus. If Configuration 279 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 280 * range). 281 */ 282 if (pci_mode == 2) 283 return (16); 284 else 285 return (32); 286 } 287 288 pcitag_t 289 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 290 { 291 pcitag_t tag; 292 293 #ifndef PCI_CONF_MODE 294 switch (pci_mode) { 295 case 1: 296 goto mode1; 297 case 2: 298 goto mode2; 299 default: 300 panic("pci_make_tag: mode not configured"); 301 } 302 #endif 303 304 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 305 #ifndef PCI_CONF_MODE 306 mode1: 307 #endif 308 if (bus >= 256 || device >= 32 || function >= 8) 309 panic("pci_make_tag: bad request"); 310 311 tag.mode1 = PCI_MODE1_ENABLE | 312 (bus << 16) | (device << 11) | (function << 8); 313 return tag; 314 #endif 315 316 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 317 #ifndef PCI_CONF_MODE 318 mode2: 319 #endif 320 if (bus >= 256 || device >= 16 || function >= 8) 321 panic("pci_make_tag: bad request"); 322 323 tag.mode2.port = 0xc000 | (device << 8); 324 tag.mode2.enable = 0xf0 | (function << 1); 325 tag.mode2.forward = bus; 326 return tag; 327 #endif 328 } 329 330 void 331 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 332 int *bp, int *dp, int *fp) 333 { 334 335 #ifndef PCI_CONF_MODE 336 switch (pci_mode) { 337 case 1: 338 goto mode1; 339 case 2: 340 goto mode2; 341 default: 342 panic("pci_decompose_tag: mode not configured"); 343 } 344 #endif 345 346 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 347 #ifndef PCI_CONF_MODE 348 mode1: 349 #endif 350 if (bp != NULL) 351 *bp = (tag.mode1 >> 16) & 0xff; 352 if (dp != NULL) 353 *dp = (tag.mode1 >> 11) & 0x1f; 354 if (fp != NULL) 355 *fp = (tag.mode1 >> 8) & 0x7; 356 return; 357 #endif 358 359 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 360 #ifndef PCI_CONF_MODE 361 mode2: 362 #endif 363 if (bp != NULL) 364 *bp = tag.mode2.forward & 0xff; 365 if (dp != NULL) 366 *dp = (tag.mode2.port >> 8) & 0xf; 367 if (fp != NULL) 368 *fp = (tag.mode2.enable >> 1) & 0x7; 369 #endif 370 } 371 372 pcireg_t 373 pci_conf_read( pci_chipset_tag_t pc, pcitag_t tag, 374 int reg) 375 { 376 pcireg_t data; 377 int s; 378 379 KASSERT((reg & 0x3) == 0); 380 #if defined(__i386__) && defined(XBOX) 381 if (arch_i386_is_xbox) { 382 int bus, dev, fn; 383 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 384 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 385 return (pcireg_t)-1; 386 } 387 #endif 388 389 #ifndef PCI_CONF_MODE 390 switch (pci_mode) { 391 case 1: 392 goto mode1; 393 case 2: 394 goto mode2; 395 default: 396 panic("pci_conf_read: mode not configured"); 397 } 398 #endif 399 400 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 401 #ifndef PCI_CONF_MODE 402 mode1: 403 #endif 404 PCI_CONF_LOCK(s); 405 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 406 data = inl(PCI_MODE1_DATA_REG); 407 outl(PCI_MODE1_ADDRESS_REG, 0); 408 PCI_CONF_UNLOCK(s); 409 return data; 410 #endif 411 412 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 413 #ifndef PCI_CONF_MODE 414 mode2: 415 #endif 416 PCI_CONF_LOCK(s); 417 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 418 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 419 data = inl(tag.mode2.port | reg); 420 outb(PCI_MODE2_ENABLE_REG, 0); 421 PCI_CONF_UNLOCK(s); 422 return data; 423 #endif 424 } 425 426 void 427 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, 428 pcireg_t data) 429 { 430 int s; 431 432 KASSERT((reg & 0x3) == 0); 433 #if defined(__i386__) && defined(XBOX) 434 if (arch_i386_is_xbox) { 435 int bus, dev, fn; 436 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 437 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 438 return; 439 } 440 #endif 441 442 #ifndef PCI_CONF_MODE 443 switch (pci_mode) { 444 case 1: 445 goto mode1; 446 case 2: 447 goto mode2; 448 default: 449 panic("pci_conf_write: mode not configured"); 450 } 451 #endif 452 453 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 454 #ifndef PCI_CONF_MODE 455 mode1: 456 #endif 457 PCI_CONF_LOCK(s); 458 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 459 outl(PCI_MODE1_DATA_REG, data); 460 outl(PCI_MODE1_ADDRESS_REG, 0); 461 PCI_CONF_UNLOCK(s); 462 return; 463 #endif 464 465 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 466 #ifndef PCI_CONF_MODE 467 mode2: 468 #endif 469 PCI_CONF_LOCK(s); 470 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 471 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 472 outl(tag.mode2.port | reg, data); 473 outb(PCI_MODE2_ENABLE_REG, 0); 474 PCI_CONF_UNLOCK(s); 475 #endif 476 } 477 478 int 479 pci_mode_detect() 480 { 481 482 #ifdef PCI_CONF_MODE 483 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 484 return (pci_mode = PCI_CONF_MODE); 485 #else 486 #error Invalid PCI configuration mode. 487 #endif 488 #else 489 u_int32_t sav, val; 490 int i; 491 pcireg_t idreg; 492 493 if (pci_mode != -1) 494 return pci_mode; 495 496 /* 497 * We try to divine which configuration mode the host bridge wants. 498 */ 499 500 sav = inl(PCI_MODE1_ADDRESS_REG); 501 502 pci_mode = 1; /* assume this for now */ 503 /* 504 * catch some known buggy implementations of mode 1 505 */ 506 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 507 pcitag_t t; 508 509 if (!pcim1_quirk_tbl[i].tag) 510 break; 511 t.mode1 = pcim1_quirk_tbl[i].tag; 512 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 513 if (idreg == pcim1_quirk_tbl[i].id) { 514 #ifdef DEBUG 515 printf("known mode 1 PCI chipset (%08x)\n", 516 idreg); 517 #endif 518 return (pci_mode); 519 } 520 } 521 522 /* 523 * Strong check for standard compliant mode 1: 524 * 1. bit 31 ("enable") can be set 525 * 2. byte/word access does not affect register 526 */ 527 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 528 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 529 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 530 val = inl(PCI_MODE1_ADDRESS_REG); 531 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 532 #ifdef DEBUG 533 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 534 val); 535 #endif 536 goto not1; 537 } 538 outl(PCI_MODE1_ADDRESS_REG, 0); 539 val = inl(PCI_MODE1_ADDRESS_REG); 540 if ((val & 0x80fffffc) != 0) 541 goto not1; 542 return (pci_mode); 543 not1: 544 outl(PCI_MODE1_ADDRESS_REG, sav); 545 546 /* 547 * This mode 2 check is quite weak (and known to give false 548 * positives on some Compaq machines). 549 * However, this doesn't matter, because this is the 550 * last test, and simply no PCI devices will be found if 551 * this happens. 552 */ 553 outb(PCI_MODE2_ENABLE_REG, 0); 554 outb(PCI_MODE2_FORWARD_REG, 0); 555 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 556 inb(PCI_MODE2_FORWARD_REG) != 0) 557 goto not2; 558 return (pci_mode = 2); 559 not2: 560 561 return (pci_mode = 0); 562 #endif 563 } 564 565 /* 566 * Determine which flags should be passed to the primary PCI bus's 567 * autoconfiguration node. We use this to detect broken chipsets 568 * which cannot safely use memory-mapped device access. 569 */ 570 int 571 pci_bus_flags() 572 { 573 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 574 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 575 int device, maxndevs; 576 pcitag_t tag; 577 pcireg_t id; 578 579 maxndevs = pci_bus_maxdevs(NULL, 0); 580 581 for (device = 0; device < maxndevs; device++) { 582 tag = pci_make_tag(NULL, 0, device, 0); 583 id = pci_conf_read(NULL, tag, PCI_ID_REG); 584 585 /* Invalid vendor ID value? */ 586 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 587 continue; 588 /* XXX Not invalid, but we've done this ~forever. */ 589 if (PCI_VENDOR(id) == 0) 590 continue; 591 592 switch (PCI_VENDOR(id)) { 593 case PCI_VENDOR_SIS: 594 switch (PCI_PRODUCT(id)) { 595 case PCI_PRODUCT_SIS_85C496: 596 goto disable_mem; 597 } 598 break; 599 } 600 } 601 602 return (rval); 603 604 disable_mem: 605 printf("Warning: broken PCI-Host bridge detected; " 606 "disabling memory-mapped access\n"); 607 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 608 PCI_FLAGS_MWI_OKAY); 609 return (rval); 610 } 611 612 void 613 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 614 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 615 { 616 pci_device_foreach_min(pc, 0, maxbus, func, context); 617 } 618 619 void 620 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 621 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 622 { 623 const struct pci_quirkdata *qd; 624 int bus, device, function, maxdevs, nfuncs; 625 pcireg_t id, bhlcr; 626 pcitag_t tag; 627 628 for (bus = minbus; bus <= maxbus; bus++) { 629 maxdevs = pci_bus_maxdevs(pc, bus); 630 for (device = 0; device < maxdevs; device++) { 631 tag = pci_make_tag(pc, bus, device, 0); 632 id = pci_conf_read(pc, tag, PCI_ID_REG); 633 634 /* Invalid vendor ID value? */ 635 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 636 continue; 637 /* XXX Not invalid, but we've done this ~forever. */ 638 if (PCI_VENDOR(id) == 0) 639 continue; 640 641 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 642 PCI_PRODUCT(id)); 643 644 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 645 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 646 (qd != NULL && 647 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 648 nfuncs = 8; 649 else 650 nfuncs = 1; 651 652 for (function = 0; function < nfuncs; function++) { 653 tag = pci_make_tag(pc, bus, device, function); 654 id = pci_conf_read(pc, tag, PCI_ID_REG); 655 656 /* Invalid vendor ID value? */ 657 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 658 continue; 659 /* 660 * XXX Not invalid, but we've done this 661 * ~forever. 662 */ 663 if (PCI_VENDOR(id) == 0) 664 continue; 665 (*func)(pc, tag, context); 666 } 667 } 668 } 669 } 670 671 void 672 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 673 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 674 { 675 struct pci_bridge_hook_arg bridge_hook; 676 677 bridge_hook.func = func; 678 bridge_hook.arg = ctx; 679 680 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 681 &bridge_hook); 682 } 683 684 static void 685 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 686 { 687 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 688 pcireg_t reg; 689 690 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 691 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 692 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 693 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 694 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 695 } 696 } 697
Indexes created Fri Sep 26 20:09:58 GMT 2025