pci_machdep.c revision 1.33
1 /* $NetBSD: pci_machdep.c,v 1.33 2008/04/16 16:06:51 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Machine-specific functions for PCI autoconfiguration. 72 * 73 * On PCs, there are two methods of generating PCI configuration cycles. 74 * We try to detect the appropriate mechanism for this machine and set 75 * up a few function pointers to access the correct method directly. 76 * 77 * The configuration method can be hard-coded in the config file by 78 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 79 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.33 2008/04/16 16:06:51 cegger Exp $"); 84 85 #include <sys/types.h> 86 #include <sys/param.h> 87 #include <sys/time.h> 88 #include <sys/systm.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/bus.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <machine/bus_private.h> 96 97 #include <machine/pio.h> 98 #include <machine/lock.h> 99 100 #include <dev/isa/isareg.h> 101 #include <dev/isa/isavar.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcidevs.h> 105 106 #include "acpi.h" 107 #include "opt_mpbios.h" 108 #include "opt_acpi.h" 109 110 #ifdef MPBIOS 111 #include <machine/mpbiosvar.h> 112 #endif 113 114 #if NACPI > 0 115 #include <machine/mpacpi.h> 116 #endif 117 118 #include <machine/mpconfig.h> 119 120 #include "opt_pci_conf_mode.h" 121 122 #ifdef __i386__ 123 #include "opt_xbox.h" 124 #ifdef XBOX 125 #include <machine/xbox.h> 126 #endif 127 #endif 128 129 int pci_mode = -1; 130 131 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 132 struct pci_bridge_hook_arg { 133 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 134 void *arg; 135 }; 136 137 138 __cpu_simple_lock_t pci_conf_lock = __SIMPLELOCK_UNLOCKED; 139 140 #define PCI_CONF_LOCK(s) \ 141 do { \ 142 (s) = splhigh(); \ 143 __cpu_simple_lock(&pci_conf_lock); \ 144 } while (0) 145 146 #define PCI_CONF_UNLOCK(s) \ 147 do { \ 148 __cpu_simple_unlock(&pci_conf_lock); \ 149 splx((s)); \ 150 } while (0) 151 152 #define PCI_MODE1_ENABLE 0x80000000UL 153 #define PCI_MODE1_ADDRESS_REG 0x0cf8 154 #define PCI_MODE1_DATA_REG 0x0cfc 155 156 #define PCI_MODE2_ENABLE_REG 0x0cf8 157 #define PCI_MODE2_FORWARD_REG 0x0cfa 158 159 #define _m1tag(b, d, f) \ 160 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 161 #define _qe(bus, dev, fcn, vend, prod) \ 162 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 163 struct { 164 uint32_t tag; 165 pcireg_t id; 166 } pcim1_quirk_tbl[] = { 167 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 168 /* XXX Triflex2 not tested */ 169 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 170 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 171 /* Triton needed for Connectix Virtual PC */ 172 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 173 /* Connectix Virtual PC 5 has a 440BX */ 174 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 175 /* Parallels Desktop for Mac */ 176 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 177 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 178 /* SIS 741 */ 179 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 180 {0, 0xffffffff} /* patchable */ 181 }; 182 #undef _m1tag 183 #undef _id 184 #undef _qe 185 186 /* 187 * PCI doesn't have any special needs; just use the generic versions 188 * of these functions. 189 */ 190 struct x86_bus_dma_tag pci_bus_dma_tag = { 191 0, /* tag_needs_free */ 192 #if defined(_LP64) || defined(PAE) 193 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 194 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 195 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 196 #else 197 0, 198 0, 199 0, 200 #endif 201 NULL, /* _may_bounce */ 202 _bus_dmamap_create, 203 _bus_dmamap_destroy, 204 _bus_dmamap_load, 205 _bus_dmamap_load_mbuf, 206 _bus_dmamap_load_uio, 207 _bus_dmamap_load_raw, 208 _bus_dmamap_unload, 209 _bus_dmamap_sync, 210 _bus_dmamem_alloc, 211 _bus_dmamem_free, 212 _bus_dmamem_map, 213 _bus_dmamem_unmap, 214 _bus_dmamem_mmap, 215 _bus_dmatag_subregion, 216 _bus_dmatag_destroy, 217 }; 218 219 #ifdef _LP64 220 struct x86_bus_dma_tag pci_bus_dma64_tag = { 221 0, /* tag_needs_free */ 222 0, 223 0, 224 0, 225 NULL, /* _may_bounce */ 226 _bus_dmamap_create, 227 _bus_dmamap_destroy, 228 _bus_dmamap_load, 229 _bus_dmamap_load_mbuf, 230 _bus_dmamap_load_uio, 231 _bus_dmamap_load_raw, 232 _bus_dmamap_unload, 233 NULL, 234 _bus_dmamem_alloc, 235 _bus_dmamem_free, 236 _bus_dmamem_map, 237 _bus_dmamem_unmap, 238 _bus_dmamem_mmap, 239 _bus_dmatag_subregion, 240 _bus_dmatag_destroy, 241 }; 242 #endif 243 244 void 245 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 246 { 247 248 if (pba->pba_bus == 0) 249 aprint_normal(": configuration mode %d", pci_mode); 250 #ifdef MPBIOS 251 mpbios_pci_attach_hook(parent, self, pba); 252 #endif 253 #if NACPI > 0 254 mpacpi_pci_attach_hook(parent, self, pba); 255 #endif 256 } 257 258 int 259 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 260 { 261 262 #if defined(__i386__) && defined(XBOX) 263 /* 264 * Scanning above the first device is fatal on the Microsoft Xbox. 265 * If busno=1, only allow for one device. 266 */ 267 if (arch_i386_is_xbox) { 268 if (busno == 1) 269 return 1; 270 else if (busno > 1) 271 return 0; 272 } 273 #endif 274 275 /* 276 * Bus number is irrelevant. If Configuration Mechanism 2 is in 277 * use, can only have devices 0-15 on any bus. If Configuration 278 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 279 * range). 280 */ 281 if (pci_mode == 2) 282 return (16); 283 else 284 return (32); 285 } 286 287 pcitag_t 288 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 289 { 290 pcitag_t tag; 291 292 #ifndef PCI_CONF_MODE 293 switch (pci_mode) { 294 case 1: 295 goto mode1; 296 case 2: 297 goto mode2; 298 default: 299 panic("pci_make_tag: mode not configured"); 300 } 301 #endif 302 303 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 304 #ifndef PCI_CONF_MODE 305 mode1: 306 #endif 307 if (bus >= 256 || device >= 32 || function >= 8) 308 panic("pci_make_tag: bad request"); 309 310 tag.mode1 = PCI_MODE1_ENABLE | 311 (bus << 16) | (device << 11) | (function << 8); 312 return tag; 313 #endif 314 315 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 316 #ifndef PCI_CONF_MODE 317 mode2: 318 #endif 319 if (bus >= 256 || device >= 16 || function >= 8) 320 panic("pci_make_tag: bad request"); 321 322 tag.mode2.port = 0xc000 | (device << 8); 323 tag.mode2.enable = 0xf0 | (function << 1); 324 tag.mode2.forward = bus; 325 return tag; 326 #endif 327 } 328 329 void 330 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 331 int *bp, int *dp, int *fp) 332 { 333 334 #ifndef PCI_CONF_MODE 335 switch (pci_mode) { 336 case 1: 337 goto mode1; 338 case 2: 339 goto mode2; 340 default: 341 panic("pci_decompose_tag: mode not configured"); 342 } 343 #endif 344 345 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 346 #ifndef PCI_CONF_MODE 347 mode1: 348 #endif 349 if (bp != NULL) 350 *bp = (tag.mode1 >> 16) & 0xff; 351 if (dp != NULL) 352 *dp = (tag.mode1 >> 11) & 0x1f; 353 if (fp != NULL) 354 *fp = (tag.mode1 >> 8) & 0x7; 355 return; 356 #endif 357 358 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 359 #ifndef PCI_CONF_MODE 360 mode2: 361 #endif 362 if (bp != NULL) 363 *bp = tag.mode2.forward & 0xff; 364 if (dp != NULL) 365 *dp = (tag.mode2.port >> 8) & 0xf; 366 if (fp != NULL) 367 *fp = (tag.mode2.enable >> 1) & 0x7; 368 #endif 369 } 370 371 pcireg_t 372 pci_conf_read( pci_chipset_tag_t pc, pcitag_t tag, 373 int reg) 374 { 375 pcireg_t data; 376 int s; 377 378 KASSERT((reg & 0x3) == 0); 379 #if defined(__i386__) && defined(XBOX) 380 if (arch_i386_is_xbox) { 381 int bus, dev, fn; 382 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 383 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 384 return (pcireg_t)-1; 385 } 386 #endif 387 388 #ifndef PCI_CONF_MODE 389 switch (pci_mode) { 390 case 1: 391 goto mode1; 392 case 2: 393 goto mode2; 394 default: 395 panic("pci_conf_read: mode not configured"); 396 } 397 #endif 398 399 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 400 #ifndef PCI_CONF_MODE 401 mode1: 402 #endif 403 PCI_CONF_LOCK(s); 404 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 405 data = inl(PCI_MODE1_DATA_REG); 406 outl(PCI_MODE1_ADDRESS_REG, 0); 407 PCI_CONF_UNLOCK(s); 408 return data; 409 #endif 410 411 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 412 #ifndef PCI_CONF_MODE 413 mode2: 414 #endif 415 PCI_CONF_LOCK(s); 416 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 417 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 418 data = inl(tag.mode2.port | reg); 419 outb(PCI_MODE2_ENABLE_REG, 0); 420 PCI_CONF_UNLOCK(s); 421 return data; 422 #endif 423 } 424 425 void 426 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, 427 pcireg_t data) 428 { 429 int s; 430 431 KASSERT((reg & 0x3) == 0); 432 #if defined(__i386__) && defined(XBOX) 433 if (arch_i386_is_xbox) { 434 int bus, dev, fn; 435 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 436 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 437 return; 438 } 439 #endif 440 441 #ifndef PCI_CONF_MODE 442 switch (pci_mode) { 443 case 1: 444 goto mode1; 445 case 2: 446 goto mode2; 447 default: 448 panic("pci_conf_write: mode not configured"); 449 } 450 #endif 451 452 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 453 #ifndef PCI_CONF_MODE 454 mode1: 455 #endif 456 PCI_CONF_LOCK(s); 457 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 458 outl(PCI_MODE1_DATA_REG, data); 459 outl(PCI_MODE1_ADDRESS_REG, 0); 460 PCI_CONF_UNLOCK(s); 461 return; 462 #endif 463 464 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 465 #ifndef PCI_CONF_MODE 466 mode2: 467 #endif 468 PCI_CONF_LOCK(s); 469 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 470 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 471 outl(tag.mode2.port | reg, data); 472 outb(PCI_MODE2_ENABLE_REG, 0); 473 PCI_CONF_UNLOCK(s); 474 #endif 475 } 476 477 int 478 pci_mode_detect(void) 479 { 480 481 #ifdef PCI_CONF_MODE 482 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 483 return (pci_mode = PCI_CONF_MODE); 484 #else 485 #error Invalid PCI configuration mode. 486 #endif 487 #else 488 uint32_t sav, val; 489 int i; 490 pcireg_t idreg; 491 492 if (pci_mode != -1) 493 return pci_mode; 494 495 /* 496 * We try to divine which configuration mode the host bridge wants. 497 */ 498 499 sav = inl(PCI_MODE1_ADDRESS_REG); 500 501 pci_mode = 1; /* assume this for now */ 502 /* 503 * catch some known buggy implementations of mode 1 504 */ 505 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 506 pcitag_t t; 507 508 if (!pcim1_quirk_tbl[i].tag) 509 break; 510 t.mode1 = pcim1_quirk_tbl[i].tag; 511 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 512 if (idreg == pcim1_quirk_tbl[i].id) { 513 #ifdef DEBUG 514 printf("known mode 1 PCI chipset (%08x)\n", 515 idreg); 516 #endif 517 return (pci_mode); 518 } 519 } 520 521 /* 522 * Strong check for standard compliant mode 1: 523 * 1. bit 31 ("enable") can be set 524 * 2. byte/word access does not affect register 525 */ 526 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 527 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 528 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 529 val = inl(PCI_MODE1_ADDRESS_REG); 530 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 531 #ifdef DEBUG 532 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 533 val); 534 #endif 535 goto not1; 536 } 537 outl(PCI_MODE1_ADDRESS_REG, 0); 538 val = inl(PCI_MODE1_ADDRESS_REG); 539 if ((val & 0x80fffffc) != 0) 540 goto not1; 541 return (pci_mode); 542 not1: 543 outl(PCI_MODE1_ADDRESS_REG, sav); 544 545 /* 546 * This mode 2 check is quite weak (and known to give false 547 * positives on some Compaq machines). 548 * However, this doesn't matter, because this is the 549 * last test, and simply no PCI devices will be found if 550 * this happens. 551 */ 552 outb(PCI_MODE2_ENABLE_REG, 0); 553 outb(PCI_MODE2_FORWARD_REG, 0); 554 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 555 inb(PCI_MODE2_FORWARD_REG) != 0) 556 goto not2; 557 return (pci_mode = 2); 558 not2: 559 560 return (pci_mode = 0); 561 #endif 562 } 563 564 /* 565 * Determine which flags should be passed to the primary PCI bus's 566 * autoconfiguration node. We use this to detect broken chipsets 567 * which cannot safely use memory-mapped device access. 568 */ 569 int 570 pci_bus_flags() 571 { 572 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 573 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 574 int device, maxndevs; 575 pcitag_t tag; 576 pcireg_t id; 577 578 maxndevs = pci_bus_maxdevs(NULL, 0); 579 580 for (device = 0; device < maxndevs; device++) { 581 tag = pci_make_tag(NULL, 0, device, 0); 582 id = pci_conf_read(NULL, tag, PCI_ID_REG); 583 584 /* Invalid vendor ID value? */ 585 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 586 continue; 587 /* XXX Not invalid, but we've done this ~forever. */ 588 if (PCI_VENDOR(id) == 0) 589 continue; 590 591 switch (PCI_VENDOR(id)) { 592 case PCI_VENDOR_SIS: 593 switch (PCI_PRODUCT(id)) { 594 case PCI_PRODUCT_SIS_85C496: 595 goto disable_mem; 596 } 597 break; 598 } 599 } 600 601 return (rval); 602 603 disable_mem: 604 printf("Warning: broken PCI-Host bridge detected; " 605 "disabling memory-mapped access\n"); 606 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 607 PCI_FLAGS_MWI_OKAY); 608 return (rval); 609 } 610 611 void 612 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 613 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 614 { 615 pci_device_foreach_min(pc, 0, maxbus, func, context); 616 } 617 618 void 619 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 620 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 621 { 622 const struct pci_quirkdata *qd; 623 int bus, device, function, maxdevs, nfuncs; 624 pcireg_t id, bhlcr; 625 pcitag_t tag; 626 627 for (bus = minbus; bus <= maxbus; bus++) { 628 maxdevs = pci_bus_maxdevs(pc, bus); 629 for (device = 0; device < maxdevs; device++) { 630 tag = pci_make_tag(pc, bus, device, 0); 631 id = pci_conf_read(pc, tag, PCI_ID_REG); 632 633 /* Invalid vendor ID value? */ 634 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 635 continue; 636 /* XXX Not invalid, but we've done this ~forever. */ 637 if (PCI_VENDOR(id) == 0) 638 continue; 639 640 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 641 PCI_PRODUCT(id)); 642 643 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 644 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 645 (qd != NULL && 646 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 647 nfuncs = 8; 648 else 649 nfuncs = 1; 650 651 for (function = 0; function < nfuncs; function++) { 652 tag = pci_make_tag(pc, bus, device, function); 653 id = pci_conf_read(pc, tag, PCI_ID_REG); 654 655 /* Invalid vendor ID value? */ 656 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 657 continue; 658 /* 659 * XXX Not invalid, but we've done this 660 * ~forever. 661 */ 662 if (PCI_VENDOR(id) == 0) 663 continue; 664 (*func)(pc, tag, context); 665 } 666 } 667 } 668 } 669 670 void 671 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 672 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 673 { 674 struct pci_bridge_hook_arg bridge_hook; 675 676 bridge_hook.func = func; 677 bridge_hook.arg = ctx; 678 679 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 680 &bridge_hook); 681 } 682 683 static void 684 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 685 { 686 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 687 pcireg_t reg; 688 689 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 690 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 691 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 692 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 693 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 694 } 695 } 696
Indexes created Fri Sep 26 20:09:58 GMT 2025