pci_machdep.c revision 1.36
1 /* $NetBSD: pci_machdep.c,v 1.36 2009/07/03 13:15:22 drochner Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.36 2009/07/03 13:15:22 drochner Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/bus_private.h> 89 90 #include <machine/pio.h> 91 #include <machine/lock.h> 92 93 #include <dev/isa/isareg.h> 94 #include <dev/isa/isavar.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcidevs.h> 98 99 #include "acpi.h" 100 #include "opt_mpbios.h" 101 #include "opt_acpi.h" 102 103 #ifdef MPBIOS 104 #include <machine/mpbiosvar.h> 105 #endif 106 107 #if NACPI > 0 108 #include <machine/mpacpi.h> 109 #endif 110 111 #include <machine/mpconfig.h> 112 113 #include "opt_pci_conf_mode.h" 114 115 #ifdef __i386__ 116 #include "opt_xbox.h" 117 #ifdef XBOX 118 #include <machine/xbox.h> 119 #endif 120 #endif 121 122 int pci_mode = -1; 123 124 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 125 struct pci_bridge_hook_arg { 126 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 127 void *arg; 128 }; 129 130 131 __cpu_simple_lock_t pci_conf_lock = __SIMPLELOCK_UNLOCKED; 132 133 #define PCI_CONF_LOCK(s) \ 134 do { \ 135 (s) = splhigh(); \ 136 __cpu_simple_lock(&pci_conf_lock); \ 137 } while (0) 138 139 #define PCI_CONF_UNLOCK(s) \ 140 do { \ 141 __cpu_simple_unlock(&pci_conf_lock); \ 142 splx((s)); \ 143 } while (0) 144 145 #define PCI_MODE1_ENABLE 0x80000000UL 146 #define PCI_MODE1_ADDRESS_REG 0x0cf8 147 #define PCI_MODE1_DATA_REG 0x0cfc 148 149 #define PCI_MODE2_ENABLE_REG 0x0cf8 150 #define PCI_MODE2_FORWARD_REG 0x0cfa 151 152 #define _m1tag(b, d, f) \ 153 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 154 #define _qe(bus, dev, fcn, vend, prod) \ 155 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 156 struct { 157 uint32_t tag; 158 pcireg_t id; 159 } pcim1_quirk_tbl[] = { 160 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 161 /* XXX Triflex2 not tested */ 162 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 163 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 164 /* Triton needed for Connectix Virtual PC */ 165 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 166 /* Connectix Virtual PC 5 has a 440BX */ 167 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 168 /* Parallels Desktop for Mac */ 169 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 170 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 171 /* SIS 740 */ 172 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 173 /* SIS 741 */ 174 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 175 {0, 0xffffffff} /* patchable */ 176 }; 177 #undef _m1tag 178 #undef _id 179 #undef _qe 180 181 /* 182 * PCI doesn't have any special needs; just use the generic versions 183 * of these functions. 184 */ 185 struct x86_bus_dma_tag pci_bus_dma_tag = { 186 0, /* tag_needs_free */ 187 #if defined(_LP64) || defined(PAE) 188 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 189 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 190 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 191 #else 192 0, 193 0, 194 0, 195 #endif 196 NULL, /* _may_bounce */ 197 _bus_dmamap_create, 198 _bus_dmamap_destroy, 199 _bus_dmamap_load, 200 _bus_dmamap_load_mbuf, 201 _bus_dmamap_load_uio, 202 _bus_dmamap_load_raw, 203 _bus_dmamap_unload, 204 _bus_dmamap_sync, 205 _bus_dmamem_alloc, 206 _bus_dmamem_free, 207 _bus_dmamem_map, 208 _bus_dmamem_unmap, 209 _bus_dmamem_mmap, 210 _bus_dmatag_subregion, 211 _bus_dmatag_destroy, 212 }; 213 214 #ifdef _LP64 215 struct x86_bus_dma_tag pci_bus_dma64_tag = { 216 0, /* tag_needs_free */ 217 0, 218 0, 219 0, 220 NULL, /* _may_bounce */ 221 _bus_dmamap_create, 222 _bus_dmamap_destroy, 223 _bus_dmamap_load, 224 _bus_dmamap_load_mbuf, 225 _bus_dmamap_load_uio, 226 _bus_dmamap_load_raw, 227 _bus_dmamap_unload, 228 NULL, 229 _bus_dmamem_alloc, 230 _bus_dmamem_free, 231 _bus_dmamem_map, 232 _bus_dmamem_unmap, 233 _bus_dmamem_mmap, 234 _bus_dmatag_subregion, 235 _bus_dmatag_destroy, 236 }; 237 #endif 238 239 void 240 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 241 { 242 243 if (pba->pba_bus == 0) 244 aprint_normal(": configuration mode %d", pci_mode); 245 #ifdef MPBIOS 246 mpbios_pci_attach_hook(parent, self, pba); 247 #endif 248 #if NACPI > 0 249 mpacpi_pci_attach_hook(parent, self, pba); 250 #endif 251 } 252 253 int 254 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 255 { 256 257 #if defined(__i386__) && defined(XBOX) 258 /* 259 * Scanning above the first device is fatal on the Microsoft Xbox. 260 * If busno=1, only allow for one device. 261 */ 262 if (arch_i386_is_xbox) { 263 if (busno == 1) 264 return 1; 265 else if (busno > 1) 266 return 0; 267 } 268 #endif 269 270 /* 271 * Bus number is irrelevant. If Configuration Mechanism 2 is in 272 * use, can only have devices 0-15 on any bus. If Configuration 273 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 274 * range). 275 */ 276 if (pci_mode == 2) 277 return (16); 278 else 279 return (32); 280 } 281 282 pcitag_t 283 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 284 { 285 pcitag_t tag; 286 287 #ifndef PCI_CONF_MODE 288 switch (pci_mode) { 289 case 1: 290 goto mode1; 291 case 2: 292 goto mode2; 293 default: 294 panic("pci_make_tag: mode not configured"); 295 } 296 #endif 297 298 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 299 #ifndef PCI_CONF_MODE 300 mode1: 301 #endif 302 if (bus >= 256 || device >= 32 || function >= 8) 303 panic("pci_make_tag: bad request"); 304 305 tag.mode1 = PCI_MODE1_ENABLE | 306 (bus << 16) | (device << 11) | (function << 8); 307 return tag; 308 #endif 309 310 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 311 #ifndef PCI_CONF_MODE 312 mode2: 313 #endif 314 if (bus >= 256 || device >= 16 || function >= 8) 315 panic("pci_make_tag: bad request"); 316 317 tag.mode2.port = 0xc000 | (device << 8); 318 tag.mode2.enable = 0xf0 | (function << 1); 319 tag.mode2.forward = bus; 320 return tag; 321 #endif 322 } 323 324 void 325 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 326 int *bp, int *dp, int *fp) 327 { 328 329 #ifndef PCI_CONF_MODE 330 switch (pci_mode) { 331 case 1: 332 goto mode1; 333 case 2: 334 goto mode2; 335 default: 336 panic("pci_decompose_tag: mode not configured"); 337 } 338 #endif 339 340 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 341 #ifndef PCI_CONF_MODE 342 mode1: 343 #endif 344 if (bp != NULL) 345 *bp = (tag.mode1 >> 16) & 0xff; 346 if (dp != NULL) 347 *dp = (tag.mode1 >> 11) & 0x1f; 348 if (fp != NULL) 349 *fp = (tag.mode1 >> 8) & 0x7; 350 return; 351 #endif 352 353 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 354 #ifndef PCI_CONF_MODE 355 mode2: 356 #endif 357 if (bp != NULL) 358 *bp = tag.mode2.forward & 0xff; 359 if (dp != NULL) 360 *dp = (tag.mode2.port >> 8) & 0xf; 361 if (fp != NULL) 362 *fp = (tag.mode2.enable >> 1) & 0x7; 363 #endif 364 } 365 366 pcireg_t 367 pci_conf_read( pci_chipset_tag_t pc, pcitag_t tag, 368 int reg) 369 { 370 pcireg_t data; 371 int s; 372 373 KASSERT((reg & 0x3) == 0); 374 #if defined(__i386__) && defined(XBOX) 375 if (arch_i386_is_xbox) { 376 int bus, dev, fn; 377 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 378 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 379 return (pcireg_t)-1; 380 } 381 #endif 382 383 #ifndef PCI_CONF_MODE 384 switch (pci_mode) { 385 case 1: 386 goto mode1; 387 case 2: 388 goto mode2; 389 default: 390 panic("pci_conf_read: mode not configured"); 391 } 392 #endif 393 394 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 395 #ifndef PCI_CONF_MODE 396 mode1: 397 #endif 398 PCI_CONF_LOCK(s); 399 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 400 data = inl(PCI_MODE1_DATA_REG); 401 outl(PCI_MODE1_ADDRESS_REG, 0); 402 PCI_CONF_UNLOCK(s); 403 return data; 404 #endif 405 406 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 407 #ifndef PCI_CONF_MODE 408 mode2: 409 #endif 410 PCI_CONF_LOCK(s); 411 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 412 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 413 data = inl(tag.mode2.port | reg); 414 outb(PCI_MODE2_ENABLE_REG, 0); 415 PCI_CONF_UNLOCK(s); 416 return data; 417 #endif 418 } 419 420 void 421 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, 422 pcireg_t data) 423 { 424 int s; 425 426 KASSERT((reg & 0x3) == 0); 427 #if defined(__i386__) && defined(XBOX) 428 if (arch_i386_is_xbox) { 429 int bus, dev, fn; 430 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 431 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 432 return; 433 } 434 #endif 435 436 #ifndef PCI_CONF_MODE 437 switch (pci_mode) { 438 case 1: 439 goto mode1; 440 case 2: 441 goto mode2; 442 default: 443 panic("pci_conf_write: mode not configured"); 444 } 445 #endif 446 447 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1) 448 #ifndef PCI_CONF_MODE 449 mode1: 450 #endif 451 PCI_CONF_LOCK(s); 452 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 453 outl(PCI_MODE1_DATA_REG, data); 454 outl(PCI_MODE1_ADDRESS_REG, 0); 455 PCI_CONF_UNLOCK(s); 456 return; 457 #endif 458 459 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2) 460 #ifndef PCI_CONF_MODE 461 mode2: 462 #endif 463 PCI_CONF_LOCK(s); 464 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 465 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 466 outl(tag.mode2.port | reg, data); 467 outb(PCI_MODE2_ENABLE_REG, 0); 468 PCI_CONF_UNLOCK(s); 469 #endif 470 } 471 472 int 473 pci_mode_detect(void) 474 { 475 476 #ifdef PCI_CONF_MODE 477 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 478 return (pci_mode = PCI_CONF_MODE); 479 #else 480 #error Invalid PCI configuration mode. 481 #endif 482 #else 483 uint32_t sav, val; 484 int i; 485 pcireg_t idreg; 486 487 if (pci_mode != -1) 488 return pci_mode; 489 490 /* 491 * We try to divine which configuration mode the host bridge wants. 492 */ 493 494 sav = inl(PCI_MODE1_ADDRESS_REG); 495 496 pci_mode = 1; /* assume this for now */ 497 /* 498 * catch some known buggy implementations of mode 1 499 */ 500 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 501 pcitag_t t; 502 503 if (!pcim1_quirk_tbl[i].tag) 504 break; 505 t.mode1 = pcim1_quirk_tbl[i].tag; 506 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 507 if (idreg == pcim1_quirk_tbl[i].id) { 508 #ifdef DEBUG 509 printf("known mode 1 PCI chipset (%08x)\n", 510 idreg); 511 #endif 512 return (pci_mode); 513 } 514 } 515 516 /* 517 * Strong check for standard compliant mode 1: 518 * 1. bit 31 ("enable") can be set 519 * 2. byte/word access does not affect register 520 */ 521 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 522 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 523 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 524 val = inl(PCI_MODE1_ADDRESS_REG); 525 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 526 #ifdef DEBUG 527 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 528 val); 529 #endif 530 goto not1; 531 } 532 outl(PCI_MODE1_ADDRESS_REG, 0); 533 val = inl(PCI_MODE1_ADDRESS_REG); 534 if ((val & 0x80fffffc) != 0) 535 goto not1; 536 return (pci_mode); 537 not1: 538 outl(PCI_MODE1_ADDRESS_REG, sav); 539 540 /* 541 * This mode 2 check is quite weak (and known to give false 542 * positives on some Compaq machines). 543 * However, this doesn't matter, because this is the 544 * last test, and simply no PCI devices will be found if 545 * this happens. 546 */ 547 outb(PCI_MODE2_ENABLE_REG, 0); 548 outb(PCI_MODE2_FORWARD_REG, 0); 549 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 550 inb(PCI_MODE2_FORWARD_REG) != 0) 551 goto not2; 552 return (pci_mode = 2); 553 not2: 554 555 return (pci_mode = 0); 556 #endif 557 } 558 559 /* 560 * Determine which flags should be passed to the primary PCI bus's 561 * autoconfiguration node. We use this to detect broken chipsets 562 * which cannot safely use memory-mapped device access. 563 */ 564 int 565 pci_bus_flags(void) 566 { 567 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 568 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 569 int device, maxndevs; 570 pcitag_t tag; 571 pcireg_t id; 572 573 maxndevs = pci_bus_maxdevs(NULL, 0); 574 575 for (device = 0; device < maxndevs; device++) { 576 tag = pci_make_tag(NULL, 0, device, 0); 577 id = pci_conf_read(NULL, tag, PCI_ID_REG); 578 579 /* Invalid vendor ID value? */ 580 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 581 continue; 582 /* XXX Not invalid, but we've done this ~forever. */ 583 if (PCI_VENDOR(id) == 0) 584 continue; 585 586 switch (PCI_VENDOR(id)) { 587 case PCI_VENDOR_SIS: 588 switch (PCI_PRODUCT(id)) { 589 case PCI_PRODUCT_SIS_85C496: 590 goto disable_mem; 591 } 592 break; 593 } 594 } 595 596 return (rval); 597 598 disable_mem: 599 printf("Warning: broken PCI-Host bridge detected; " 600 "disabling memory-mapped access\n"); 601 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 602 PCI_FLAGS_MWI_OKAY); 603 return (rval); 604 } 605 606 void 607 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 608 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 609 { 610 pci_device_foreach_min(pc, 0, maxbus, func, context); 611 } 612 613 void 614 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 615 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 616 { 617 const struct pci_quirkdata *qd; 618 int bus, device, function, maxdevs, nfuncs; 619 pcireg_t id, bhlcr; 620 pcitag_t tag; 621 622 for (bus = minbus; bus <= maxbus; bus++) { 623 maxdevs = pci_bus_maxdevs(pc, bus); 624 for (device = 0; device < maxdevs; device++) { 625 tag = pci_make_tag(pc, bus, device, 0); 626 id = pci_conf_read(pc, tag, PCI_ID_REG); 627 628 /* Invalid vendor ID value? */ 629 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 630 continue; 631 /* XXX Not invalid, but we've done this ~forever. */ 632 if (PCI_VENDOR(id) == 0) 633 continue; 634 635 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 636 PCI_PRODUCT(id)); 637 638 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 639 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 640 (qd != NULL && 641 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 642 nfuncs = 8; 643 else 644 nfuncs = 1; 645 646 for (function = 0; function < nfuncs; function++) { 647 tag = pci_make_tag(pc, bus, device, function); 648 id = pci_conf_read(pc, tag, PCI_ID_REG); 649 650 /* Invalid vendor ID value? */ 651 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 652 continue; 653 /* 654 * XXX Not invalid, but we've done this 655 * ~forever. 656 */ 657 if (PCI_VENDOR(id) == 0) 658 continue; 659 (*func)(pc, tag, context); 660 } 661 } 662 } 663 } 664 665 void 666 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 667 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 668 { 669 struct pci_bridge_hook_arg bridge_hook; 670 671 bridge_hook.func = func; 672 bridge_hook.arg = ctx; 673 674 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 675 &bridge_hook); 676 } 677 678 static void 679 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 680 { 681 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 682 pcireg_t reg; 683 684 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 685 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 686 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 687 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 688 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 689 } 690 } 691
Indexes created Fri Sep 26 20:09:58 GMT 2025