pci_machdep.c revision 1.38
1 /* $NetBSD: pci_machdep.c,v 1.38 2010/02/16 00:03:47 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.38 2010/02/16 00:03:47 dyoung Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/bus_private.h> 89 90 #include <machine/pio.h> 91 #include <machine/lock.h> 92 93 #include <dev/isa/isareg.h> 94 #include <dev/isa/isavar.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcidevs.h> 98 99 #include "acpica.h" 100 #include "opt_mpbios.h" 101 #include "opt_acpi.h" 102 103 #ifdef MPBIOS 104 #include <machine/mpbiosvar.h> 105 #endif 106 107 #if NACPICA > 0 108 #include <machine/mpacpi.h> 109 #endif 110 111 #include <machine/mpconfig.h> 112 113 #include "opt_pci_conf_mode.h" 114 115 #ifdef __i386__ 116 #include "opt_xbox.h" 117 #ifdef XBOX 118 #include <machine/xbox.h> 119 #endif 120 #endif 121 122 #ifdef PCI_CONF_MODE 123 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 124 static int pci_mode = PCI_CONF_MODE; 125 #else 126 #error Invalid PCI configuration mode. 127 #endif 128 #else 129 static int pci_mode = -1; 130 #endif 131 132 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 133 struct pci_bridge_hook_arg { 134 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 135 void *arg; 136 }; 137 138 139 __cpu_simple_lock_t pci_conf_lock = __SIMPLELOCK_UNLOCKED; 140 141 #define PCI_CONF_LOCK(s) \ 142 do { \ 143 (s) = splhigh(); \ 144 __cpu_simple_lock(&pci_conf_lock); \ 145 } while (0) 146 147 #define PCI_CONF_UNLOCK(s) \ 148 do { \ 149 __cpu_simple_unlock(&pci_conf_lock); \ 150 splx((s)); \ 151 } while (0) 152 153 #define PCI_MODE1_ENABLE 0x80000000UL 154 #define PCI_MODE1_ADDRESS_REG 0x0cf8 155 #define PCI_MODE1_DATA_REG 0x0cfc 156 157 #define PCI_MODE2_ENABLE_REG 0x0cf8 158 #define PCI_MODE2_FORWARD_REG 0x0cfa 159 160 #define _m1tag(b, d, f) \ 161 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 162 #define _qe(bus, dev, fcn, vend, prod) \ 163 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 164 struct { 165 uint32_t tag; 166 pcireg_t id; 167 } pcim1_quirk_tbl[] = { 168 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 169 /* XXX Triflex2 not tested */ 170 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 171 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 172 /* Triton needed for Connectix Virtual PC */ 173 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 174 /* Connectix Virtual PC 5 has a 440BX */ 175 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 176 /* Parallels Desktop for Mac */ 177 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 178 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 179 /* SIS 740 */ 180 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 181 /* SIS 741 */ 182 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 183 {0, 0xffffffff} /* patchable */ 184 }; 185 #undef _m1tag 186 #undef _id 187 #undef _qe 188 189 /* 190 * PCI doesn't have any special needs; just use the generic versions 191 * of these functions. 192 */ 193 struct x86_bus_dma_tag pci_bus_dma_tag = { 194 0, /* tag_needs_free */ 195 #if defined(_LP64) || defined(PAE) 196 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 197 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 198 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 199 #else 200 0, 201 0, 202 0, 203 #endif 204 NULL, /* _may_bounce */ 205 _bus_dmamap_create, 206 _bus_dmamap_destroy, 207 _bus_dmamap_load, 208 _bus_dmamap_load_mbuf, 209 _bus_dmamap_load_uio, 210 _bus_dmamap_load_raw, 211 _bus_dmamap_unload, 212 _bus_dmamap_sync, 213 _bus_dmamem_alloc, 214 _bus_dmamem_free, 215 _bus_dmamem_map, 216 _bus_dmamem_unmap, 217 _bus_dmamem_mmap, 218 _bus_dmatag_subregion, 219 _bus_dmatag_destroy, 220 }; 221 222 #ifdef _LP64 223 struct x86_bus_dma_tag pci_bus_dma64_tag = { 224 0, /* tag_needs_free */ 225 0, 226 0, 227 0, 228 NULL, /* _may_bounce */ 229 _bus_dmamap_create, 230 _bus_dmamap_destroy, 231 _bus_dmamap_load, 232 _bus_dmamap_load_mbuf, 233 _bus_dmamap_load_uio, 234 _bus_dmamap_load_raw, 235 _bus_dmamap_unload, 236 NULL, 237 _bus_dmamem_alloc, 238 _bus_dmamem_free, 239 _bus_dmamem_map, 240 _bus_dmamem_unmap, 241 _bus_dmamem_mmap, 242 _bus_dmatag_subregion, 243 _bus_dmatag_destroy, 244 }; 245 #endif 246 247 void 248 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 249 { 250 251 if (pba->pba_bus == 0) 252 aprint_normal(": configuration mode %d", pci_mode); 253 #ifdef MPBIOS 254 mpbios_pci_attach_hook(parent, self, pba); 255 #endif 256 #if NACPICA > 0 257 mpacpi_pci_attach_hook(parent, self, pba); 258 #endif 259 } 260 261 int 262 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 263 { 264 265 #if defined(__i386__) && defined(XBOX) 266 /* 267 * Scanning above the first device is fatal on the Microsoft Xbox. 268 * If busno=1, only allow for one device. 269 */ 270 if (arch_i386_is_xbox) { 271 if (busno == 1) 272 return 1; 273 else if (busno > 1) 274 return 0; 275 } 276 #endif 277 278 /* 279 * Bus number is irrelevant. If Configuration Mechanism 2 is in 280 * use, can only have devices 0-15 on any bus. If Configuration 281 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 282 * range). 283 */ 284 if (pci_mode == 2) 285 return (16); 286 else 287 return (32); 288 } 289 290 pcitag_t 291 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 292 { 293 pcitag_t tag; 294 295 switch (pci_mode) { 296 case 1: 297 if (bus >= 256 || device >= 32 || function >= 8) 298 panic("pci_make_tag: bad request"); 299 300 tag.mode1 = PCI_MODE1_ENABLE | 301 (bus << 16) | (device << 11) | (function << 8); 302 return tag; 303 case 2: 304 if (bus >= 256 || device >= 16 || function >= 8) 305 panic("pci_make_tag: bad request"); 306 307 tag.mode2.port = 0xc000 | (device << 8); 308 tag.mode2.enable = 0xf0 | (function << 1); 309 tag.mode2.forward = bus; 310 return tag; 311 default: 312 panic("pci_make_tag: mode not configured"); 313 } 314 } 315 316 void 317 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 318 int *bp, int *dp, int *fp) 319 { 320 321 switch (pci_mode) { 322 case 1: 323 if (bp != NULL) 324 *bp = (tag.mode1 >> 16) & 0xff; 325 if (dp != NULL) 326 *dp = (tag.mode1 >> 11) & 0x1f; 327 if (fp != NULL) 328 *fp = (tag.mode1 >> 8) & 0x7; 329 return; 330 case 2: 331 if (bp != NULL) 332 *bp = tag.mode2.forward & 0xff; 333 if (dp != NULL) 334 *dp = (tag.mode2.port >> 8) & 0xf; 335 if (fp != NULL) 336 *fp = (tag.mode2.enable >> 1) & 0x7; 337 return; 338 default: 339 panic("pci_decompose_tag: mode not configured"); 340 } 341 } 342 343 pcireg_t 344 pci_conf_read( pci_chipset_tag_t pc, pcitag_t tag, 345 int reg) 346 { 347 pcireg_t data; 348 int s; 349 350 KASSERT((reg & 0x3) == 0); 351 #if defined(__i386__) && defined(XBOX) 352 if (arch_i386_is_xbox) { 353 int bus, dev, fn; 354 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 355 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 356 return (pcireg_t)-1; 357 } 358 #endif 359 360 switch (pci_mode) { 361 case 1: 362 PCI_CONF_LOCK(s); 363 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 364 data = inl(PCI_MODE1_DATA_REG); 365 outl(PCI_MODE1_ADDRESS_REG, 0); 366 PCI_CONF_UNLOCK(s); 367 return data; 368 case 2: 369 PCI_CONF_LOCK(s); 370 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 371 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 372 data = inl(tag.mode2.port | reg); 373 outb(PCI_MODE2_ENABLE_REG, 0); 374 PCI_CONF_UNLOCK(s); 375 return data; 376 default: 377 panic("pci_conf_read: mode not configured"); 378 } 379 } 380 381 void 382 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, 383 pcireg_t data) 384 { 385 int s; 386 387 KASSERT((reg & 0x3) == 0); 388 #if defined(__i386__) && defined(XBOX) 389 if (arch_i386_is_xbox) { 390 int bus, dev, fn; 391 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 392 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 393 return; 394 } 395 #endif 396 397 switch (pci_mode) { 398 case 1: 399 PCI_CONF_LOCK(s); 400 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 401 outl(PCI_MODE1_DATA_REG, data); 402 outl(PCI_MODE1_ADDRESS_REG, 0); 403 PCI_CONF_UNLOCK(s); 404 return; 405 case 2: 406 PCI_CONF_LOCK(s); 407 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 408 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 409 outl(tag.mode2.port | reg, data); 410 outb(PCI_MODE2_ENABLE_REG, 0); 411 PCI_CONF_UNLOCK(s); 412 return; 413 default: 414 panic("pci_conf_write: mode not configured"); 415 } 416 } 417 418 void 419 pci_mode_set(int mode) 420 { 421 KASSERT(pci_mode == -1 || pci_mode == mode); 422 423 pci_mode = mode; 424 } 425 426 int 427 pci_mode_detect(void) 428 { 429 uint32_t sav, val; 430 int i; 431 pcireg_t idreg; 432 433 if (pci_mode != -1) 434 return pci_mode; 435 436 /* 437 * We try to divine which configuration mode the host bridge wants. 438 */ 439 440 sav = inl(PCI_MODE1_ADDRESS_REG); 441 442 pci_mode = 1; /* assume this for now */ 443 /* 444 * catch some known buggy implementations of mode 1 445 */ 446 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 447 pcitag_t t; 448 449 if (!pcim1_quirk_tbl[i].tag) 450 break; 451 t.mode1 = pcim1_quirk_tbl[i].tag; 452 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 453 if (idreg == pcim1_quirk_tbl[i].id) { 454 #ifdef DEBUG 455 printf("known mode 1 PCI chipset (%08x)\n", 456 idreg); 457 #endif 458 return (pci_mode); 459 } 460 } 461 462 /* 463 * Strong check for standard compliant mode 1: 464 * 1. bit 31 ("enable") can be set 465 * 2. byte/word access does not affect register 466 */ 467 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 468 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 469 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 470 val = inl(PCI_MODE1_ADDRESS_REG); 471 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 472 #ifdef DEBUG 473 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 474 val); 475 #endif 476 goto not1; 477 } 478 outl(PCI_MODE1_ADDRESS_REG, 0); 479 val = inl(PCI_MODE1_ADDRESS_REG); 480 if ((val & 0x80fffffc) != 0) 481 goto not1; 482 return (pci_mode); 483 not1: 484 outl(PCI_MODE1_ADDRESS_REG, sav); 485 486 /* 487 * This mode 2 check is quite weak (and known to give false 488 * positives on some Compaq machines). 489 * However, this doesn't matter, because this is the 490 * last test, and simply no PCI devices will be found if 491 * this happens. 492 */ 493 outb(PCI_MODE2_ENABLE_REG, 0); 494 outb(PCI_MODE2_FORWARD_REG, 0); 495 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 496 inb(PCI_MODE2_FORWARD_REG) != 0) 497 goto not2; 498 return (pci_mode = 2); 499 not2: 500 501 return (pci_mode = 0); 502 } 503 504 /* 505 * Determine which flags should be passed to the primary PCI bus's 506 * autoconfiguration node. We use this to detect broken chipsets 507 * which cannot safely use memory-mapped device access. 508 */ 509 int 510 pci_bus_flags(void) 511 { 512 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 513 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 514 int device, maxndevs; 515 pcitag_t tag; 516 pcireg_t id; 517 518 maxndevs = pci_bus_maxdevs(NULL, 0); 519 520 for (device = 0; device < maxndevs; device++) { 521 tag = pci_make_tag(NULL, 0, device, 0); 522 id = pci_conf_read(NULL, tag, PCI_ID_REG); 523 524 /* Invalid vendor ID value? */ 525 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 526 continue; 527 /* XXX Not invalid, but we've done this ~forever. */ 528 if (PCI_VENDOR(id) == 0) 529 continue; 530 531 switch (PCI_VENDOR(id)) { 532 case PCI_VENDOR_SIS: 533 switch (PCI_PRODUCT(id)) { 534 case PCI_PRODUCT_SIS_85C496: 535 goto disable_mem; 536 } 537 break; 538 } 539 } 540 541 return (rval); 542 543 disable_mem: 544 printf("Warning: broken PCI-Host bridge detected; " 545 "disabling memory-mapped access\n"); 546 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 547 PCI_FLAGS_MWI_OKAY); 548 return (rval); 549 } 550 551 void 552 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 553 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 554 { 555 pci_device_foreach_min(pc, 0, maxbus, func, context); 556 } 557 558 void 559 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 560 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 561 { 562 const struct pci_quirkdata *qd; 563 int bus, device, function, maxdevs, nfuncs; 564 pcireg_t id, bhlcr; 565 pcitag_t tag; 566 567 for (bus = minbus; bus <= maxbus; bus++) { 568 maxdevs = pci_bus_maxdevs(pc, bus); 569 for (device = 0; device < maxdevs; device++) { 570 tag = pci_make_tag(pc, bus, device, 0); 571 id = pci_conf_read(pc, tag, PCI_ID_REG); 572 573 /* Invalid vendor ID value? */ 574 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 575 continue; 576 /* XXX Not invalid, but we've done this ~forever. */ 577 if (PCI_VENDOR(id) == 0) 578 continue; 579 580 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 581 PCI_PRODUCT(id)); 582 583 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 584 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 585 (qd != NULL && 586 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 587 nfuncs = 8; 588 else 589 nfuncs = 1; 590 591 for (function = 0; function < nfuncs; function++) { 592 tag = pci_make_tag(pc, bus, device, function); 593 id = pci_conf_read(pc, tag, PCI_ID_REG); 594 595 /* Invalid vendor ID value? */ 596 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 597 continue; 598 /* 599 * XXX Not invalid, but we've done this 600 * ~forever. 601 */ 602 if (PCI_VENDOR(id) == 0) 603 continue; 604 (*func)(pc, tag, context); 605 } 606 } 607 } 608 } 609 610 void 611 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 612 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 613 { 614 struct pci_bridge_hook_arg bridge_hook; 615 616 bridge_hook.func = func; 617 bridge_hook.arg = ctx; 618 619 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 620 &bridge_hook); 621 } 622 623 static void 624 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 625 { 626 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 627 pcireg_t reg; 628 629 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 630 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 631 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 632 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 633 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 634 } 635 } 636
Indexes created Mon Sep 29 21:09:56 GMT 2025