pci_machdep.c revision 1.41
1 /* $NetBSD: pci_machdep.c,v 1.41 2010/03/14 20:19:06 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.41 2010/03/14 20:19:06 dyoung Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/bus_private.h> 89 90 #include <machine/pio.h> 91 #include <machine/lock.h> 92 93 #include <dev/isa/isareg.h> 94 #include <dev/isa/isavar.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcidevs.h> 98 99 #include "acpica.h" 100 #include "opt_mpbios.h" 101 #include "opt_acpi.h" 102 103 #ifdef MPBIOS 104 #include <machine/mpbiosvar.h> 105 #endif 106 107 #if NACPICA > 0 108 #include <machine/mpacpi.h> 109 #endif 110 111 #include <machine/mpconfig.h> 112 113 #include "opt_pci_conf_mode.h" 114 115 #ifdef __i386__ 116 #include "opt_xbox.h" 117 #ifdef XBOX 118 #include <machine/xbox.h> 119 #endif 120 #endif 121 122 #ifdef PCI_CONF_MODE 123 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 124 static int pci_mode = PCI_CONF_MODE; 125 #else 126 #error Invalid PCI configuration mode. 127 #endif 128 #else 129 static int pci_mode = -1; 130 #endif 131 132 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 133 struct pci_bridge_hook_arg { 134 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 135 void *arg; 136 }; 137 138 __cpu_simple_lock_t pci_conf_lock = __SIMPLELOCK_UNLOCKED; 139 140 #define PCI_CONF_LOCK(s) \ 141 do { \ 142 (s) = splhigh(); \ 143 __cpu_simple_lock(&pci_conf_lock); \ 144 } while (0) 145 146 #define PCI_CONF_UNLOCK(s) \ 147 do { \ 148 __cpu_simple_unlock(&pci_conf_lock); \ 149 splx((s)); \ 150 } while (0) 151 152 #define PCI_MODE1_ENABLE 0x80000000UL 153 #define PCI_MODE1_ADDRESS_REG 0x0cf8 154 #define PCI_MODE1_DATA_REG 0x0cfc 155 156 #define PCI_MODE2_ENABLE_REG 0x0cf8 157 #define PCI_MODE2_FORWARD_REG 0x0cfa 158 159 #define _m1tag(b, d, f) \ 160 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 161 #define _qe(bus, dev, fcn, vend, prod) \ 162 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 163 struct { 164 uint32_t tag; 165 pcireg_t id; 166 } pcim1_quirk_tbl[] = { 167 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 168 /* XXX Triflex2 not tested */ 169 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 170 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 171 /* Triton needed for Connectix Virtual PC */ 172 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 173 /* Connectix Virtual PC 5 has a 440BX */ 174 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 175 /* Parallels Desktop for Mac */ 176 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 177 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 178 /* SIS 740 */ 179 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 180 /* SIS 741 */ 181 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 182 {0, 0xffffffff} /* patchable */ 183 }; 184 #undef _m1tag 185 #undef _id 186 #undef _qe 187 188 /* 189 * PCI doesn't have any special needs; just use the generic versions 190 * of these functions. 191 */ 192 struct x86_bus_dma_tag pci_bus_dma_tag = { 193 0, /* tag_needs_free */ 194 #if defined(_LP64) || defined(PAE) 195 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 196 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 197 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 198 #else 199 0, 200 0, 201 0, 202 #endif 203 NULL, /* _may_bounce */ 204 _bus_dmamap_create, 205 _bus_dmamap_destroy, 206 _bus_dmamap_load, 207 _bus_dmamap_load_mbuf, 208 _bus_dmamap_load_uio, 209 _bus_dmamap_load_raw, 210 _bus_dmamap_unload, 211 _bus_dmamap_sync, 212 _bus_dmamem_alloc, 213 _bus_dmamem_free, 214 _bus_dmamem_map, 215 _bus_dmamem_unmap, 216 _bus_dmamem_mmap, 217 _bus_dmatag_subregion, 218 _bus_dmatag_destroy, 219 }; 220 221 #ifdef _LP64 222 struct x86_bus_dma_tag pci_bus_dma64_tag = { 223 0, /* tag_needs_free */ 224 0, 225 0, 226 0, 227 NULL, /* _may_bounce */ 228 _bus_dmamap_create, 229 _bus_dmamap_destroy, 230 _bus_dmamap_load, 231 _bus_dmamap_load_mbuf, 232 _bus_dmamap_load_uio, 233 _bus_dmamap_load_raw, 234 _bus_dmamap_unload, 235 NULL, 236 _bus_dmamem_alloc, 237 _bus_dmamem_free, 238 _bus_dmamem_map, 239 _bus_dmamem_unmap, 240 _bus_dmamem_mmap, 241 _bus_dmatag_subregion, 242 _bus_dmatag_destroy, 243 }; 244 #endif 245 246 static uint32_t 247 pci_conf_selector(pcitag_t tag, int reg) 248 { 249 static const pcitag_t mode2_mask = { 250 .mode2 = { 251 .enable = 0xff 252 , .forward = 0xff 253 } 254 }; 255 256 switch (pci_mode) { 257 case 1: 258 return tag.mode1 | reg; 259 case 2: 260 return tag.mode1 & mode2_mask.mode1; 261 default: 262 panic("%s: mode not configured", __func__); 263 } 264 } 265 266 static unsigned int 267 pci_conf_port(pcitag_t tag, int reg) 268 { 269 switch (pci_mode) { 270 case 1: 271 return PCI_MODE1_DATA_REG; 272 case 2: 273 return tag.mode2.port | reg; 274 default: 275 panic("%s: mode not configured", __func__); 276 } 277 } 278 279 static void 280 pci_conf_select(uint32_t addr) 281 { 282 pcitag_t tag; 283 284 switch (pci_mode) { 285 case 1: 286 outl(PCI_MODE1_ADDRESS_REG, addr); 287 return; 288 case 2: 289 tag.mode1 = addr; 290 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 291 if (tag.mode2.enable != 0) 292 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 293 return; 294 default: 295 panic("%s: mode not configured", __func__); 296 } 297 } 298 299 void 300 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 301 { 302 303 if (pba->pba_bus == 0) 304 aprint_normal(": configuration mode %d", pci_mode); 305 #ifdef MPBIOS 306 mpbios_pci_attach_hook(parent, self, pba); 307 #endif 308 #if NACPICA > 0 309 mpacpi_pci_attach_hook(parent, self, pba); 310 #endif 311 } 312 313 int 314 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 315 { 316 317 #if defined(__i386__) && defined(XBOX) 318 /* 319 * Scanning above the first device is fatal on the Microsoft Xbox. 320 * If busno=1, only allow for one device. 321 */ 322 if (arch_i386_is_xbox) { 323 if (busno == 1) 324 return 1; 325 else if (busno > 1) 326 return 0; 327 } 328 #endif 329 330 /* 331 * Bus number is irrelevant. If Configuration Mechanism 2 is in 332 * use, can only have devices 0-15 on any bus. If Configuration 333 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 334 * range). 335 */ 336 if (pci_mode == 2) 337 return (16); 338 else 339 return (32); 340 } 341 342 pcitag_t 343 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 344 { 345 pcitag_t tag; 346 347 if (pc != NULL) { 348 if (pc->pc_make_tag != NULL) 349 return (*pc->pc_make_tag)(pc, bus, device, function); 350 if (pc->pc_super != NULL) { 351 return pci_make_tag(pc->pc_super, bus, device, 352 function); 353 } 354 } 355 356 switch (pci_mode) { 357 case 1: 358 if (bus >= 256 || device >= 32 || function >= 8) 359 panic("%s: bad request", __func__); 360 361 tag.mode1 = PCI_MODE1_ENABLE | 362 (bus << 16) | (device << 11) | (function << 8); 363 return tag; 364 case 2: 365 if (bus >= 256 || device >= 16 || function >= 8) 366 panic("%s: bad request", __func__); 367 368 tag.mode2.port = 0xc000 | (device << 8); 369 tag.mode2.enable = 0xf0 | (function << 1); 370 tag.mode2.forward = bus; 371 return tag; 372 default: 373 panic("%s: mode not configured", __func__); 374 } 375 } 376 377 void 378 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 379 int *bp, int *dp, int *fp) 380 { 381 382 if (pc != NULL) { 383 if (pc->pc_decompose_tag != NULL) { 384 (*pc->pc_decompose_tag)(pc, tag, bp, dp, fp); 385 return; 386 } 387 if (pc->pc_super != NULL) { 388 pci_decompose_tag(pc->pc_super, tag, bp, dp, fp); 389 return; 390 } 391 } 392 393 switch (pci_mode) { 394 case 1: 395 if (bp != NULL) 396 *bp = (tag.mode1 >> 16) & 0xff; 397 if (dp != NULL) 398 *dp = (tag.mode1 >> 11) & 0x1f; 399 if (fp != NULL) 400 *fp = (tag.mode1 >> 8) & 0x7; 401 return; 402 case 2: 403 if (bp != NULL) 404 *bp = tag.mode2.forward & 0xff; 405 if (dp != NULL) 406 *dp = (tag.mode2.port >> 8) & 0xf; 407 if (fp != NULL) 408 *fp = (tag.mode2.enable >> 1) & 0x7; 409 return; 410 default: 411 panic("%s: mode not configured", __func__); 412 } 413 } 414 415 pcireg_t 416 pci_conf_read( pci_chipset_tag_t pc, pcitag_t tag, 417 int reg) 418 { 419 pcireg_t data; 420 int s; 421 422 KASSERT((reg & 0x3) == 0); 423 424 if (pc != NULL) { 425 if (pc->pc_conf_read != NULL) 426 return (*pc->pc_conf_read)(pc, tag, reg); 427 if (pc->pc_super != NULL) 428 return pci_conf_read(pc->pc_super, tag, reg); 429 } 430 431 #if defined(__i386__) && defined(XBOX) 432 if (arch_i386_is_xbox) { 433 int bus, dev, fn; 434 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 435 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 436 return (pcireg_t)-1; 437 } 438 #endif 439 440 PCI_CONF_LOCK(s); 441 pci_conf_select(pci_conf_selector(tag, reg)); 442 data = inl(pci_conf_port(tag, reg)); 443 pci_conf_select(0); 444 PCI_CONF_UNLOCK(s); 445 return data; 446 } 447 448 void 449 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, 450 pcireg_t data) 451 { 452 int s; 453 454 KASSERT((reg & 0x3) == 0); 455 456 if (pc != NULL) { 457 if (pc->pc_conf_write != NULL) { 458 (*pc->pc_conf_write)(pc, tag, reg, data); 459 return; 460 } 461 if (pc->pc_super != NULL) { 462 pci_conf_write(pc->pc_super, tag, reg, data); 463 return; 464 } 465 } 466 467 #if defined(__i386__) && defined(XBOX) 468 if (arch_i386_is_xbox) { 469 int bus, dev, fn; 470 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 471 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 472 return; 473 } 474 #endif 475 476 PCI_CONF_LOCK(s); 477 pci_conf_select(pci_conf_selector(tag, reg)); 478 outl(pci_conf_port(tag, reg), data); 479 pci_conf_select(0); 480 PCI_CONF_UNLOCK(s); 481 } 482 483 void 484 pci_mode_set(int mode) 485 { 486 KASSERT(pci_mode == -1 || pci_mode == mode); 487 488 pci_mode = mode; 489 } 490 491 int 492 pci_mode_detect(void) 493 { 494 uint32_t sav, val; 495 int i; 496 pcireg_t idreg; 497 498 if (pci_mode != -1) 499 return pci_mode; 500 501 /* 502 * We try to divine which configuration mode the host bridge wants. 503 */ 504 505 sav = inl(PCI_MODE1_ADDRESS_REG); 506 507 pci_mode = 1; /* assume this for now */ 508 /* 509 * catch some known buggy implementations of mode 1 510 */ 511 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 512 pcitag_t t; 513 514 if (!pcim1_quirk_tbl[i].tag) 515 break; 516 t.mode1 = pcim1_quirk_tbl[i].tag; 517 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 518 if (idreg == pcim1_quirk_tbl[i].id) { 519 #ifdef DEBUG 520 printf("known mode 1 PCI chipset (%08x)\n", 521 idreg); 522 #endif 523 return (pci_mode); 524 } 525 } 526 527 /* 528 * Strong check for standard compliant mode 1: 529 * 1. bit 31 ("enable") can be set 530 * 2. byte/word access does not affect register 531 */ 532 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 533 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 534 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 535 val = inl(PCI_MODE1_ADDRESS_REG); 536 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 537 #ifdef DEBUG 538 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 539 val); 540 #endif 541 goto not1; 542 } 543 outl(PCI_MODE1_ADDRESS_REG, 0); 544 val = inl(PCI_MODE1_ADDRESS_REG); 545 if ((val & 0x80fffffc) != 0) 546 goto not1; 547 return (pci_mode); 548 not1: 549 outl(PCI_MODE1_ADDRESS_REG, sav); 550 551 /* 552 * This mode 2 check is quite weak (and known to give false 553 * positives on some Compaq machines). 554 * However, this doesn't matter, because this is the 555 * last test, and simply no PCI devices will be found if 556 * this happens. 557 */ 558 outb(PCI_MODE2_ENABLE_REG, 0); 559 outb(PCI_MODE2_FORWARD_REG, 0); 560 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 561 inb(PCI_MODE2_FORWARD_REG) != 0) 562 goto not2; 563 return (pci_mode = 2); 564 not2: 565 566 return (pci_mode = 0); 567 } 568 569 /* 570 * Determine which flags should be passed to the primary PCI bus's 571 * autoconfiguration node. We use this to detect broken chipsets 572 * which cannot safely use memory-mapped device access. 573 */ 574 int 575 pci_bus_flags(void) 576 { 577 int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 578 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 579 int device, maxndevs; 580 pcitag_t tag; 581 pcireg_t id; 582 583 maxndevs = pci_bus_maxdevs(NULL, 0); 584 585 for (device = 0; device < maxndevs; device++) { 586 tag = pci_make_tag(NULL, 0, device, 0); 587 id = pci_conf_read(NULL, tag, PCI_ID_REG); 588 589 /* Invalid vendor ID value? */ 590 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 591 continue; 592 /* XXX Not invalid, but we've done this ~forever. */ 593 if (PCI_VENDOR(id) == 0) 594 continue; 595 596 switch (PCI_VENDOR(id)) { 597 case PCI_VENDOR_SIS: 598 switch (PCI_PRODUCT(id)) { 599 case PCI_PRODUCT_SIS_85C496: 600 goto disable_mem; 601 } 602 break; 603 } 604 } 605 606 return (rval); 607 608 disable_mem: 609 printf("Warning: broken PCI-Host bridge detected; " 610 "disabling memory-mapped access\n"); 611 rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 612 PCI_FLAGS_MWI_OKAY); 613 return (rval); 614 } 615 616 void 617 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 618 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 619 { 620 pci_device_foreach_min(pc, 0, maxbus, func, context); 621 } 622 623 void 624 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 625 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 626 { 627 const struct pci_quirkdata *qd; 628 int bus, device, function, maxdevs, nfuncs; 629 pcireg_t id, bhlcr; 630 pcitag_t tag; 631 632 for (bus = minbus; bus <= maxbus; bus++) { 633 maxdevs = pci_bus_maxdevs(pc, bus); 634 for (device = 0; device < maxdevs; device++) { 635 tag = pci_make_tag(pc, bus, device, 0); 636 id = pci_conf_read(pc, tag, PCI_ID_REG); 637 638 /* Invalid vendor ID value? */ 639 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 640 continue; 641 /* XXX Not invalid, but we've done this ~forever. */ 642 if (PCI_VENDOR(id) == 0) 643 continue; 644 645 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 646 PCI_PRODUCT(id)); 647 648 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 649 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 650 (qd != NULL && 651 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 652 nfuncs = 8; 653 else 654 nfuncs = 1; 655 656 for (function = 0; function < nfuncs; function++) { 657 tag = pci_make_tag(pc, bus, device, function); 658 id = pci_conf_read(pc, tag, PCI_ID_REG); 659 660 /* Invalid vendor ID value? */ 661 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 662 continue; 663 /* 664 * XXX Not invalid, but we've done this 665 * ~forever. 666 */ 667 if (PCI_VENDOR(id) == 0) 668 continue; 669 (*func)(pc, tag, context); 670 } 671 } 672 } 673 } 674 675 void 676 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 677 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 678 { 679 struct pci_bridge_hook_arg bridge_hook; 680 681 bridge_hook.func = func; 682 bridge_hook.arg = ctx; 683 684 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 685 &bridge_hook); 686 } 687 688 static void 689 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 690 { 691 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 692 pcireg_t reg; 693 694 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 695 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 696 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 697 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 698 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 699 } 700 } 701
Indexes created Wed Sep 24 22:09:59 GMT 2025