pci_machdep.c revision 1.45
1 /* $NetBSD: pci_machdep.c,v 1.45 2011/05/17 17:34:53 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.45 2011/05/17 17:34:53 dyoung Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 #include <sys/cpu.h> 86 #include <sys/kmem.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bus_private.h> 91 92 #include <machine/pio.h> 93 #include <machine/lock.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pccbbreg.h> 100 #include <dev/pci/pcidevs.h> 101 102 #include "acpica.h" 103 #include "opt_mpbios.h" 104 #include "opt_acpi.h" 105 106 #ifdef MPBIOS 107 #include <machine/mpbiosvar.h> 108 #endif 109 110 #if NACPICA > 0 111 #include <machine/mpacpi.h> 112 #endif 113 114 #include <machine/mpconfig.h> 115 116 #include "opt_pci_conf_mode.h" 117 118 #ifdef __i386__ 119 #include "opt_xbox.h" 120 #ifdef XBOX 121 #include <machine/xbox.h> 122 #endif 123 #endif 124 125 #ifdef PCI_CONF_MODE 126 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 127 static int pci_mode = PCI_CONF_MODE; 128 #else 129 #error Invalid PCI configuration mode. 130 #endif 131 #else 132 static int pci_mode = -1; 133 #endif 134 135 struct pci_conf_lock { 136 uint32_t cl_cpuno; /* 0: unlocked 137 * 1 + n: locked by CPU n (0 <= n) 138 */ 139 uint32_t cl_sel; /* the address that's being read. */ 140 }; 141 142 static void pci_conf_unlock(struct pci_conf_lock *); 143 static uint32_t pci_conf_selector(pcitag_t, int); 144 static unsigned int pci_conf_port(pcitag_t, int); 145 static void pci_conf_select(uint32_t); 146 static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 147 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 148 struct pci_bridge_hook_arg { 149 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 150 void *arg; 151 }; 152 153 #define PCI_MODE1_ENABLE 0x80000000UL 154 #define PCI_MODE1_ADDRESS_REG 0x0cf8 155 #define PCI_MODE1_DATA_REG 0x0cfc 156 157 #define PCI_MODE2_ENABLE_REG 0x0cf8 158 #define PCI_MODE2_FORWARD_REG 0x0cfa 159 160 #define _m1tag(b, d, f) \ 161 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 162 #define _qe(bus, dev, fcn, vend, prod) \ 163 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 164 struct { 165 uint32_t tag; 166 pcireg_t id; 167 } pcim1_quirk_tbl[] = { 168 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 169 /* XXX Triflex2 not tested */ 170 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 171 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 172 /* Triton needed for Connectix Virtual PC */ 173 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 174 /* Connectix Virtual PC 5 has a 440BX */ 175 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 176 /* Parallels Desktop for Mac */ 177 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 178 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 179 /* SIS 740 */ 180 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 181 /* SIS 741 */ 182 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 183 {0, 0xffffffff} /* patchable */ 184 }; 185 #undef _m1tag 186 #undef _id 187 #undef _qe 188 189 /* 190 * PCI doesn't have any special needs; just use the generic versions 191 * of these functions. 192 */ 193 struct x86_bus_dma_tag pci_bus_dma_tag = { 194 0, /* tag_needs_free */ 195 #if defined(_LP64) || defined(PAE) 196 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_thresh */ 197 ISA_DMA_BOUNCE_THRESHOLD, /* bounce_alloclo */ 198 PCI32_DMA_BOUNCE_THRESHOLD, /* bounce_allochi */ 199 #else 200 0, 201 0, 202 0, 203 #endif 204 NULL, /* _may_bounce */ 205 _bus_dmamap_create, 206 _bus_dmamap_destroy, 207 _bus_dmamap_load, 208 _bus_dmamap_load_mbuf, 209 _bus_dmamap_load_uio, 210 _bus_dmamap_load_raw, 211 _bus_dmamap_unload, 212 _bus_dmamap_sync, 213 _bus_dmamem_alloc, 214 _bus_dmamem_free, 215 _bus_dmamem_map, 216 _bus_dmamem_unmap, 217 _bus_dmamem_mmap, 218 _bus_dmatag_subregion, 219 _bus_dmatag_destroy, 220 }; 221 222 #ifdef _LP64 223 struct x86_bus_dma_tag pci_bus_dma64_tag = { 224 0, /* tag_needs_free */ 225 0, 226 0, 227 0, 228 NULL, /* _may_bounce */ 229 _bus_dmamap_create, 230 _bus_dmamap_destroy, 231 _bus_dmamap_load, 232 _bus_dmamap_load_mbuf, 233 _bus_dmamap_load_uio, 234 _bus_dmamap_load_raw, 235 _bus_dmamap_unload, 236 NULL, 237 _bus_dmamem_alloc, 238 _bus_dmamem_free, 239 _bus_dmamem_map, 240 _bus_dmamem_unmap, 241 _bus_dmamem_mmap, 242 _bus_dmatag_subregion, 243 _bus_dmatag_destroy, 244 }; 245 #endif 246 247 static struct pci_conf_lock cl0 = { 248 .cl_cpuno = 0UL 249 , .cl_sel = 0UL 250 }; 251 252 static struct pci_conf_lock * const cl = &cl0; 253 254 static void 255 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 256 { 257 uint32_t cpuno; 258 259 KASSERT(sel != 0); 260 261 kpreempt_disable(); 262 cpuno = cpu_number() + 1; 263 /* If the kernel enters pci_conf_lock() through an interrupt 264 * handler, then the CPU may already hold the lock. 265 * 266 * If the CPU does not already hold the lock, spin until 267 * we can acquire it. 268 */ 269 if (cpuno == cl->cl_cpuno) { 270 ocl->cl_cpuno = cpuno; 271 } else { 272 u_int spins; 273 274 ocl->cl_cpuno = 0; 275 276 spins = SPINLOCK_BACKOFF_MIN; 277 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 278 SPINLOCK_BACKOFF(spins); 279 #ifdef LOCKDEBUG 280 if (SPINLOCK_SPINOUT(spins)) { 281 panic("%s: cpu %" PRId32 282 " spun out waiting for cpu %" PRId32, 283 __func__, cpuno, cl->cl_cpuno); 284 } 285 #endif /* LOCKDEBUG */ 286 } 287 } 288 289 /* Only one CPU can be here, so an interlocked atomic_swap(3) 290 * is not necessary. 291 * 292 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 293 * and applying atomic_cas_32_ni() is not an atomic operation, 294 * however, any interrupt that, in the middle of the 295 * operation, modifies cl->cl_sel, will also restore 296 * cl->cl_sel. So cl->cl_sel will have the same value when 297 * we apply atomic_cas_32_ni() as when we evaluated it, 298 * before. 299 */ 300 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 301 pci_conf_select(sel); 302 } 303 304 static void 305 pci_conf_unlock(struct pci_conf_lock *ocl) 306 { 307 uint32_t sel; 308 309 sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 310 pci_conf_select(ocl->cl_sel); 311 if (ocl->cl_cpuno != cl->cl_cpuno) 312 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 313 kpreempt_enable(); 314 } 315 316 static uint32_t 317 pci_conf_selector(pcitag_t tag, int reg) 318 { 319 static const pcitag_t mode2_mask = { 320 .mode2 = { 321 .enable = 0xff 322 , .forward = 0xff 323 } 324 }; 325 326 switch (pci_mode) { 327 case 1: 328 return tag.mode1 | reg; 329 case 2: 330 return tag.mode1 & mode2_mask.mode1; 331 default: 332 panic("%s: mode not configured", __func__); 333 } 334 } 335 336 static unsigned int 337 pci_conf_port(pcitag_t tag, int reg) 338 { 339 switch (pci_mode) { 340 case 1: 341 return PCI_MODE1_DATA_REG; 342 case 2: 343 return tag.mode2.port | reg; 344 default: 345 panic("%s: mode not configured", __func__); 346 } 347 } 348 349 static void 350 pci_conf_select(uint32_t sel) 351 { 352 pcitag_t tag; 353 354 switch (pci_mode) { 355 case 1: 356 outl(PCI_MODE1_ADDRESS_REG, sel); 357 return; 358 case 2: 359 tag.mode1 = sel; 360 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 361 if (tag.mode2.enable != 0) 362 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 363 return; 364 default: 365 panic("%s: mode not configured", __func__); 366 } 367 } 368 369 void 370 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 371 { 372 373 if (pba->pba_bus == 0) 374 aprint_normal(": configuration mode %d", pci_mode); 375 #ifdef MPBIOS 376 mpbios_pci_attach_hook(parent, self, pba); 377 #endif 378 #if NACPICA > 0 379 mpacpi_pci_attach_hook(parent, self, pba); 380 #endif 381 } 382 383 int 384 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 385 { 386 387 #if defined(__i386__) && defined(XBOX) 388 /* 389 * Scanning above the first device is fatal on the Microsoft Xbox. 390 * If busno=1, only allow for one device. 391 */ 392 if (arch_i386_is_xbox) { 393 if (busno == 1) 394 return 1; 395 else if (busno > 1) 396 return 0; 397 } 398 #endif 399 400 /* 401 * Bus number is irrelevant. If Configuration Mechanism 2 is in 402 * use, can only have devices 0-15 on any bus. If Configuration 403 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 404 * range). 405 */ 406 if (pci_mode == 2) 407 return (16); 408 else 409 return (32); 410 } 411 412 pcitag_t 413 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 414 { 415 pcitag_t tag; 416 417 if (pc != NULL) { 418 if ((pc->pc_present & PCI_OVERRIDE_MAKE_TAG) != 0) { 419 return (*pc->pc_ov->ov_make_tag)(pc->pc_ctx, 420 pc, bus, device, function); 421 } 422 if (pc->pc_super != NULL) { 423 return pci_make_tag(pc->pc_super, bus, device, 424 function); 425 } 426 } 427 428 switch (pci_mode) { 429 case 1: 430 if (bus >= 256 || device >= 32 || function >= 8) 431 panic("%s: bad request", __func__); 432 433 tag.mode1 = PCI_MODE1_ENABLE | 434 (bus << 16) | (device << 11) | (function << 8); 435 return tag; 436 case 2: 437 if (bus >= 256 || device >= 16 || function >= 8) 438 panic("%s: bad request", __func__); 439 440 tag.mode2.port = 0xc000 | (device << 8); 441 tag.mode2.enable = 0xf0 | (function << 1); 442 tag.mode2.forward = bus; 443 return tag; 444 default: 445 panic("%s: mode not configured", __func__); 446 } 447 } 448 449 void 450 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 451 int *bp, int *dp, int *fp) 452 { 453 454 if (pc != NULL) { 455 if ((pc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) != 0) { 456 (*pc->pc_ov->ov_decompose_tag)(pc->pc_ctx, 457 pc, tag, bp, dp, fp); 458 return; 459 } 460 if (pc->pc_super != NULL) { 461 pci_decompose_tag(pc->pc_super, tag, bp, dp, fp); 462 return; 463 } 464 } 465 466 switch (pci_mode) { 467 case 1: 468 if (bp != NULL) 469 *bp = (tag.mode1 >> 16) & 0xff; 470 if (dp != NULL) 471 *dp = (tag.mode1 >> 11) & 0x1f; 472 if (fp != NULL) 473 *fp = (tag.mode1 >> 8) & 0x7; 474 return; 475 case 2: 476 if (bp != NULL) 477 *bp = tag.mode2.forward & 0xff; 478 if (dp != NULL) 479 *dp = (tag.mode2.port >> 8) & 0xf; 480 if (fp != NULL) 481 *fp = (tag.mode2.enable >> 1) & 0x7; 482 return; 483 default: 484 panic("%s: mode not configured", __func__); 485 } 486 } 487 488 pcireg_t 489 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 490 { 491 pcireg_t data; 492 struct pci_conf_lock ocl; 493 494 KASSERT((reg & 0x3) == 0); 495 496 if (pc != NULL) { 497 if ((pc->pc_present & PCI_OVERRIDE_CONF_READ) != 0) { 498 return (*pc->pc_ov->ov_conf_read)(pc->pc_ctx, 499 pc, tag, reg); 500 } 501 if (pc->pc_super != NULL) 502 return pci_conf_read(pc->pc_super, tag, reg); 503 } 504 505 #if defined(__i386__) && defined(XBOX) 506 if (arch_i386_is_xbox) { 507 int bus, dev, fn; 508 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 509 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 510 return (pcireg_t)-1; 511 } 512 #endif 513 514 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 515 data = inl(pci_conf_port(tag, reg)); 516 pci_conf_unlock(&ocl); 517 return data; 518 } 519 520 void 521 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 522 { 523 struct pci_conf_lock ocl; 524 525 KASSERT((reg & 0x3) == 0); 526 527 if (pc != NULL) { 528 if ((pc->pc_present & PCI_OVERRIDE_CONF_WRITE) != 0) { 529 (*pc->pc_ov->ov_conf_write)(pc->pc_ctx, pc, tag, reg, 530 data); 531 return; 532 } 533 if (pc->pc_super != NULL) { 534 pci_conf_write(pc->pc_super, tag, reg, data); 535 return; 536 } 537 } 538 539 #if defined(__i386__) && defined(XBOX) 540 if (arch_i386_is_xbox) { 541 int bus, dev, fn; 542 pci_decompose_tag(pc, tag, &bus, &dev, &fn); 543 if (bus == 0 && dev == 0 && (fn == 1 || fn == 2)) 544 return; 545 } 546 #endif 547 548 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 549 outl(pci_conf_port(tag, reg), data); 550 pci_conf_unlock(&ocl); 551 } 552 553 void 554 pci_mode_set(int mode) 555 { 556 KASSERT(pci_mode == -1 || pci_mode == mode); 557 558 pci_mode = mode; 559 } 560 561 int 562 pci_mode_detect(void) 563 { 564 uint32_t sav, val; 565 int i; 566 pcireg_t idreg; 567 568 if (pci_mode != -1) 569 return pci_mode; 570 571 /* 572 * We try to divine which configuration mode the host bridge wants. 573 */ 574 575 sav = inl(PCI_MODE1_ADDRESS_REG); 576 577 pci_mode = 1; /* assume this for now */ 578 /* 579 * catch some known buggy implementations of mode 1 580 */ 581 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 582 pcitag_t t; 583 584 if (!pcim1_quirk_tbl[i].tag) 585 break; 586 t.mode1 = pcim1_quirk_tbl[i].tag; 587 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 588 if (idreg == pcim1_quirk_tbl[i].id) { 589 #ifdef DEBUG 590 printf("known mode 1 PCI chipset (%08x)\n", 591 idreg); 592 #endif 593 return (pci_mode); 594 } 595 } 596 597 /* 598 * Strong check for standard compliant mode 1: 599 * 1. bit 31 ("enable") can be set 600 * 2. byte/word access does not affect register 601 */ 602 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 603 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 604 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 605 val = inl(PCI_MODE1_ADDRESS_REG); 606 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 607 #ifdef DEBUG 608 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 609 val); 610 #endif 611 goto not1; 612 } 613 outl(PCI_MODE1_ADDRESS_REG, 0); 614 val = inl(PCI_MODE1_ADDRESS_REG); 615 if ((val & 0x80fffffc) != 0) 616 goto not1; 617 return (pci_mode); 618 not1: 619 outl(PCI_MODE1_ADDRESS_REG, sav); 620 621 /* 622 * This mode 2 check is quite weak (and known to give false 623 * positives on some Compaq machines). 624 * However, this doesn't matter, because this is the 625 * last test, and simply no PCI devices will be found if 626 * this happens. 627 */ 628 outb(PCI_MODE2_ENABLE_REG, 0); 629 outb(PCI_MODE2_FORWARD_REG, 0); 630 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 631 inb(PCI_MODE2_FORWARD_REG) != 0) 632 goto not2; 633 return (pci_mode = 2); 634 not2: 635 636 return (pci_mode = 0); 637 } 638 639 /* 640 * Determine which flags should be passed to the primary PCI bus's 641 * autoconfiguration node. We use this to detect broken chipsets 642 * which cannot safely use memory-mapped device access. 643 */ 644 int 645 pci_bus_flags(void) 646 { 647 int rval = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 648 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 649 int device, maxndevs; 650 pcitag_t tag; 651 pcireg_t id; 652 653 maxndevs = pci_bus_maxdevs(NULL, 0); 654 655 for (device = 0; device < maxndevs; device++) { 656 tag = pci_make_tag(NULL, 0, device, 0); 657 id = pci_conf_read(NULL, tag, PCI_ID_REG); 658 659 /* Invalid vendor ID value? */ 660 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 661 continue; 662 /* XXX Not invalid, but we've done this ~forever. */ 663 if (PCI_VENDOR(id) == 0) 664 continue; 665 666 switch (PCI_VENDOR(id)) { 667 case PCI_VENDOR_SIS: 668 switch (PCI_PRODUCT(id)) { 669 case PCI_PRODUCT_SIS_85C496: 670 goto disable_mem; 671 } 672 break; 673 } 674 } 675 676 return (rval); 677 678 disable_mem: 679 printf("Warning: broken PCI-Host bridge detected; " 680 "disabling memory-mapped access\n"); 681 rval &= ~(PCI_FLAGS_MEM_OKAY|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 682 PCI_FLAGS_MWI_OKAY); 683 return (rval); 684 } 685 686 void 687 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 688 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 689 { 690 pci_device_foreach_min(pc, 0, maxbus, func, context); 691 } 692 693 void 694 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 695 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 696 { 697 const struct pci_quirkdata *qd; 698 int bus, device, function, maxdevs, nfuncs; 699 pcireg_t id, bhlcr; 700 pcitag_t tag; 701 702 for (bus = minbus; bus <= maxbus; bus++) { 703 maxdevs = pci_bus_maxdevs(pc, bus); 704 for (device = 0; device < maxdevs; device++) { 705 tag = pci_make_tag(pc, bus, device, 0); 706 id = pci_conf_read(pc, tag, PCI_ID_REG); 707 708 /* Invalid vendor ID value? */ 709 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 710 continue; 711 /* XXX Not invalid, but we've done this ~forever. */ 712 if (PCI_VENDOR(id) == 0) 713 continue; 714 715 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 716 PCI_PRODUCT(id)); 717 718 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 719 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 720 (qd != NULL && 721 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 722 nfuncs = 8; 723 else 724 nfuncs = 1; 725 726 for (function = 0; function < nfuncs; function++) { 727 tag = pci_make_tag(pc, bus, device, function); 728 id = pci_conf_read(pc, tag, PCI_ID_REG); 729 730 /* Invalid vendor ID value? */ 731 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 732 continue; 733 /* 734 * XXX Not invalid, but we've done this 735 * ~forever. 736 */ 737 if (PCI_VENDOR(id) == 0) 738 continue; 739 (*func)(pc, tag, context); 740 } 741 } 742 } 743 } 744 745 void 746 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 747 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 748 { 749 struct pci_bridge_hook_arg bridge_hook; 750 751 bridge_hook.func = func; 752 bridge_hook.arg = ctx; 753 754 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 755 &bridge_hook); 756 } 757 758 static void 759 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 760 { 761 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 762 pcireg_t reg; 763 764 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 765 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 766 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 767 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 768 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 769 } 770 } 771 772 static const void * 773 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 774 { 775 switch (bit) { 776 case PCI_OVERRIDE_CONF_READ: 777 return ov->ov_conf_read; 778 case PCI_OVERRIDE_CONF_WRITE: 779 return ov->ov_conf_write; 780 case PCI_OVERRIDE_INTR_MAP: 781 return ov->ov_intr_map; 782 case PCI_OVERRIDE_INTR_STRING: 783 return ov->ov_intr_string; 784 case PCI_OVERRIDE_INTR_EVCNT: 785 return ov->ov_intr_evcnt; 786 case PCI_OVERRIDE_INTR_ESTABLISH: 787 return ov->ov_intr_establish; 788 case PCI_OVERRIDE_INTR_DISESTABLISH: 789 return ov->ov_intr_disestablish; 790 case PCI_OVERRIDE_MAKE_TAG: 791 return ov->ov_make_tag; 792 case PCI_OVERRIDE_DECOMPOSE_TAG: 793 return ov->ov_decompose_tag; 794 default: 795 return NULL; 796 } 797 } 798 799 void 800 pci_chipset_tag_destroy(pci_chipset_tag_t pc) 801 { 802 kmem_free(pc, sizeof(struct pci_chipset_tag)); 803 } 804 805 int 806 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 807 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 808 { 809 uint64_t bit, bits, nbits; 810 pci_chipset_tag_t pc; 811 const void *fp; 812 813 if (ov == NULL || present == 0) 814 return EINVAL; 815 816 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 817 818 if (pc == NULL) 819 return ENOMEM; 820 821 pc->pc_super = opc; 822 823 for (bits = present; bits != 0; bits = nbits) { 824 nbits = bits & (bits - 1); 825 bit = nbits ^ bits; 826 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 827 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 828 goto einval; 829 } 830 } 831 832 pc->pc_ov = ov; 833 pc->pc_present = present; 834 pc->pc_ctx = ctx; 835 836 *pcp = pc; 837 838 return 0; 839 einval: 840 kmem_free(pc, sizeof(struct pci_chipset_tag)); 841 return EINVAL; 842 } 843
Indexes created Thu Sep 25 02:09:54 GMT 2025