pci_machdep.c revision 1.56
1 /* $NetBSD: pci_machdep.c,v 1.56 2012/03/01 20:16:27 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined in section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.56 2012/03/01 20:16:27 jakllsch Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 #include <sys/cpu.h> 86 #include <sys/kmem.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bus_private.h> 91 92 #include <machine/pio.h> 93 #include <machine/lock.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pccbbreg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/genfb_pcivar.h> 102 103 #include <dev/wsfb/genfbvar.h> 104 #include <arch/x86/include/genfb_machdep.h> 105 #include <dev/ic/vgareg.h> 106 107 #include "acpica.h" 108 #include "genfb.h" 109 #include "isa.h" 110 #include "opt_acpi.h" 111 #include "opt_ddb.h" 112 #include "opt_mpbios.h" 113 #include "opt_vga.h" 114 #include "pci.h" 115 #include "wsdisplay.h" 116 117 #ifdef DDB 118 #include <machine/db_machdep.h> 119 #include <ddb/db_sym.h> 120 #include <ddb/db_extern.h> 121 #endif 122 123 #ifdef VGA_POST 124 #include <x86/vga_post.h> 125 #endif 126 127 #include <machine/autoconf.h> 128 #include <machine/bootinfo.h> 129 130 #ifdef MPBIOS 131 #include <machine/mpbiosvar.h> 132 #endif 133 134 #if NACPICA > 0 135 #include <machine/mpacpi.h> 136 #endif 137 138 #include <machine/mpconfig.h> 139 140 #include "opt_pci_conf_mode.h" 141 142 #ifdef PCI_CONF_MODE 143 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 144 static int pci_mode = PCI_CONF_MODE; 145 #else 146 #error Invalid PCI configuration mode. 147 #endif 148 #else 149 static int pci_mode = -1; 150 #endif 151 152 struct pci_conf_lock { 153 uint32_t cl_cpuno; /* 0: unlocked 154 * 1 + n: locked by CPU n (0 <= n) 155 */ 156 uint32_t cl_sel; /* the address that's being read. */ 157 }; 158 159 static void pci_conf_unlock(struct pci_conf_lock *); 160 static uint32_t pci_conf_selector(pcitag_t, int); 161 static unsigned int pci_conf_port(pcitag_t, int); 162 static void pci_conf_select(uint32_t); 163 static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 164 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 165 struct pci_bridge_hook_arg { 166 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 167 void *arg; 168 }; 169 170 #define PCI_MODE1_ENABLE 0x80000000UL 171 #define PCI_MODE1_ADDRESS_REG 0x0cf8 172 #define PCI_MODE1_DATA_REG 0x0cfc 173 174 #define PCI_MODE2_ENABLE_REG 0x0cf8 175 #define PCI_MODE2_FORWARD_REG 0x0cfa 176 177 #define _tag(b, d, f) \ 178 {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)} 179 #define _qe(bus, dev, fcn, vend, prod) \ 180 {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 181 const struct { 182 pcitag_t tag; 183 pcireg_t id; 184 } pcim1_quirk_tbl[] = { 185 _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */ 186 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 187 /* XXX Triflex2 not tested */ 188 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 189 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 190 /* Triton needed for Connectix Virtual PC */ 191 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 192 /* Connectix Virtual PC 5 has a 440BX */ 193 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 194 /* Parallels Desktop for Mac */ 195 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 196 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 197 /* SIS 740 */ 198 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 199 /* SIS 741 */ 200 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 201 /* VIA Technologies VX900 */ 202 _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB) 203 }; 204 #undef _tag 205 #undef _qe 206 207 /* 208 * PCI doesn't have any special needs; just use the generic versions 209 * of these functions. 210 */ 211 struct x86_bus_dma_tag pci_bus_dma_tag = { 212 ._tag_needs_free = 0, 213 #if defined(_LP64) || defined(PAE) 214 ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD, 215 ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD, 216 ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD, 217 #else 218 ._bounce_thresh = 0, 219 ._bounce_alloc_lo = 0, 220 ._bounce_alloc_hi = 0, 221 #endif 222 ._may_bounce = NULL, 223 }; 224 225 #ifdef _LP64 226 struct x86_bus_dma_tag pci_bus_dma64_tag = { 227 ._tag_needs_free = 0, 228 ._bounce_thresh = 0, 229 ._bounce_alloc_lo = 0, 230 ._bounce_alloc_hi = 0, 231 ._may_bounce = NULL, 232 }; 233 #endif 234 235 static struct pci_conf_lock cl0 = { 236 .cl_cpuno = 0UL 237 , .cl_sel = 0UL 238 }; 239 240 static struct pci_conf_lock * const cl = &cl0; 241 242 #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST) 243 extern int acpi_md_vbios_reset; 244 extern int acpi_md_vesa_modenum; 245 #endif 246 247 static struct genfb_colormap_callback gfb_cb; 248 static struct genfb_pmf_callback pmf_cb; 249 static struct genfb_mode_callback mode_cb; 250 #ifdef VGA_POST 251 static struct vga_post *vga_posth = NULL; 252 #endif 253 254 static void 255 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 256 { 257 uint32_t cpuno; 258 259 KASSERT(sel != 0); 260 261 kpreempt_disable(); 262 cpuno = cpu_number() + 1; 263 /* If the kernel enters pci_conf_lock() through an interrupt 264 * handler, then the CPU may already hold the lock. 265 * 266 * If the CPU does not already hold the lock, spin until 267 * we can acquire it. 268 */ 269 if (cpuno == cl->cl_cpuno) { 270 ocl->cl_cpuno = cpuno; 271 } else { 272 u_int spins; 273 274 ocl->cl_cpuno = 0; 275 276 spins = SPINLOCK_BACKOFF_MIN; 277 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 278 SPINLOCK_BACKOFF(spins); 279 #ifdef LOCKDEBUG 280 if (SPINLOCK_SPINOUT(spins)) { 281 panic("%s: cpu %" PRId32 282 " spun out waiting for cpu %" PRId32, 283 __func__, cpuno, cl->cl_cpuno); 284 } 285 #endif /* LOCKDEBUG */ 286 } 287 } 288 289 /* Only one CPU can be here, so an interlocked atomic_swap(3) 290 * is not necessary. 291 * 292 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 293 * and applying atomic_cas_32_ni() is not an atomic operation, 294 * however, any interrupt that, in the middle of the 295 * operation, modifies cl->cl_sel, will also restore 296 * cl->cl_sel. So cl->cl_sel will have the same value when 297 * we apply atomic_cas_32_ni() as when we evaluated it, 298 * before. 299 */ 300 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 301 pci_conf_select(sel); 302 } 303 304 static void 305 pci_conf_unlock(struct pci_conf_lock *ocl) 306 { 307 uint32_t sel; 308 309 sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 310 pci_conf_select(ocl->cl_sel); 311 if (ocl->cl_cpuno != cl->cl_cpuno) 312 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 313 kpreempt_enable(); 314 } 315 316 static uint32_t 317 pci_conf_selector(pcitag_t tag, int reg) 318 { 319 static const pcitag_t mode2_mask = { 320 .mode2 = { 321 .enable = 0xff 322 , .forward = 0xff 323 } 324 }; 325 326 switch (pci_mode) { 327 case 1: 328 return tag.mode1 | reg; 329 case 2: 330 return tag.mode1 & mode2_mask.mode1; 331 default: 332 panic("%s: mode not configured", __func__); 333 } 334 } 335 336 static unsigned int 337 pci_conf_port(pcitag_t tag, int reg) 338 { 339 switch (pci_mode) { 340 case 1: 341 return PCI_MODE1_DATA_REG; 342 case 2: 343 return tag.mode2.port | reg; 344 default: 345 panic("%s: mode not configured", __func__); 346 } 347 } 348 349 static void 350 pci_conf_select(uint32_t sel) 351 { 352 pcitag_t tag; 353 354 switch (pci_mode) { 355 case 1: 356 outl(PCI_MODE1_ADDRESS_REG, sel); 357 return; 358 case 2: 359 tag.mode1 = sel; 360 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 361 if (tag.mode2.enable != 0) 362 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 363 return; 364 default: 365 panic("%s: mode not configured", __func__); 366 } 367 } 368 369 void 370 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 371 { 372 373 if (pba->pba_bus == 0) 374 aprint_normal(": configuration mode %d", pci_mode); 375 #ifdef MPBIOS 376 mpbios_pci_attach_hook(parent, self, pba); 377 #endif 378 #if NACPICA > 0 379 mpacpi_pci_attach_hook(parent, self, pba); 380 #endif 381 } 382 383 int 384 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 385 { 386 /* 387 * Bus number is irrelevant. If Configuration Mechanism 2 is in 388 * use, can only have devices 0-15 on any bus. If Configuration 389 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 390 * range). 391 */ 392 if (pci_mode == 2) 393 return (16); 394 else 395 return (32); 396 } 397 398 pcitag_t 399 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 400 { 401 pci_chipset_tag_t ipc; 402 pcitag_t tag; 403 404 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 405 if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0) 406 continue; 407 return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx, 408 pc, bus, device, function); 409 } 410 411 switch (pci_mode) { 412 case 1: 413 if (bus >= 256 || device >= 32 || function >= 8) 414 panic("%s: bad request", __func__); 415 416 tag.mode1 = PCI_MODE1_ENABLE | 417 (bus << 16) | (device << 11) | (function << 8); 418 return tag; 419 case 2: 420 if (bus >= 256 || device >= 16 || function >= 8) 421 panic("%s: bad request", __func__); 422 423 tag.mode2.port = 0xc000 | (device << 8); 424 tag.mode2.enable = 0xf0 | (function << 1); 425 tag.mode2.forward = bus; 426 return tag; 427 default: 428 panic("%s: mode not configured", __func__); 429 } 430 } 431 432 void 433 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 434 int *bp, int *dp, int *fp) 435 { 436 pci_chipset_tag_t ipc; 437 438 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 439 if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0) 440 continue; 441 (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx, 442 pc, tag, bp, dp, fp); 443 return; 444 } 445 446 switch (pci_mode) { 447 case 1: 448 if (bp != NULL) 449 *bp = (tag.mode1 >> 16) & 0xff; 450 if (dp != NULL) 451 *dp = (tag.mode1 >> 11) & 0x1f; 452 if (fp != NULL) 453 *fp = (tag.mode1 >> 8) & 0x7; 454 return; 455 case 2: 456 if (bp != NULL) 457 *bp = tag.mode2.forward & 0xff; 458 if (dp != NULL) 459 *dp = (tag.mode2.port >> 8) & 0xf; 460 if (fp != NULL) 461 *fp = (tag.mode2.enable >> 1) & 0x7; 462 return; 463 default: 464 panic("%s: mode not configured", __func__); 465 } 466 } 467 468 pcireg_t 469 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 470 { 471 pci_chipset_tag_t ipc; 472 pcireg_t data; 473 struct pci_conf_lock ocl; 474 475 KASSERT((reg & 0x3) == 0); 476 477 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 478 if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0) 479 continue; 480 return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg); 481 } 482 483 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 484 data = inl(pci_conf_port(tag, reg)); 485 pci_conf_unlock(&ocl); 486 return data; 487 } 488 489 void 490 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 491 { 492 pci_chipset_tag_t ipc; 493 struct pci_conf_lock ocl; 494 495 KASSERT((reg & 0x3) == 0); 496 497 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 498 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 499 continue; 500 (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg, 501 data); 502 return; 503 } 504 505 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 506 outl(pci_conf_port(tag, reg), data); 507 pci_conf_unlock(&ocl); 508 } 509 510 void 511 pci_mode_set(int mode) 512 { 513 KASSERT(pci_mode == -1 || pci_mode == mode); 514 515 pci_mode = mode; 516 } 517 518 int 519 pci_mode_detect(void) 520 { 521 uint32_t sav, val; 522 int i; 523 pcireg_t idreg; 524 525 if (pci_mode != -1) 526 return pci_mode; 527 528 /* 529 * We try to divine which configuration mode the host bridge wants. 530 */ 531 532 sav = inl(PCI_MODE1_ADDRESS_REG); 533 534 pci_mode = 1; /* assume this for now */ 535 /* 536 * catch some known buggy implementations of mode 1 537 */ 538 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 539 pcitag_t t; 540 541 if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID) 542 continue; 543 t.mode1 = pcim1_quirk_tbl[i].tag.mode1; 544 idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */ 545 if (idreg == pcim1_quirk_tbl[i].id) { 546 #ifdef DEBUG 547 printf("known mode 1 PCI chipset (%08x)\n", 548 idreg); 549 #endif 550 return (pci_mode); 551 } 552 } 553 554 /* 555 * Strong check for standard compliant mode 1: 556 * 1. bit 31 ("enable") can be set 557 * 2. byte/word access does not affect register 558 */ 559 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 560 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 561 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 562 val = inl(PCI_MODE1_ADDRESS_REG); 563 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 564 #ifdef DEBUG 565 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 566 val); 567 #endif 568 goto not1; 569 } 570 outl(PCI_MODE1_ADDRESS_REG, 0); 571 val = inl(PCI_MODE1_ADDRESS_REG); 572 if ((val & 0x80fffffc) != 0) 573 goto not1; 574 return (pci_mode); 575 not1: 576 outl(PCI_MODE1_ADDRESS_REG, sav); 577 578 /* 579 * This mode 2 check is quite weak (and known to give false 580 * positives on some Compaq machines). 581 * However, this doesn't matter, because this is the 582 * last test, and simply no PCI devices will be found if 583 * this happens. 584 */ 585 outb(PCI_MODE2_ENABLE_REG, 0); 586 outb(PCI_MODE2_FORWARD_REG, 0); 587 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 588 inb(PCI_MODE2_FORWARD_REG) != 0) 589 goto not2; 590 return (pci_mode = 2); 591 not2: 592 593 return (pci_mode = 0); 594 } 595 596 /* 597 * Determine which flags should be passed to the primary PCI bus's 598 * autoconfiguration node. We use this to detect broken chipsets 599 * which cannot safely use memory-mapped device access. 600 */ 601 int 602 pci_bus_flags(void) 603 { 604 int rval = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 605 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 606 int device, maxndevs; 607 pcitag_t tag; 608 pcireg_t id; 609 610 maxndevs = pci_bus_maxdevs(NULL, 0); 611 612 for (device = 0; device < maxndevs; device++) { 613 tag = pci_make_tag(NULL, 0, device, 0); 614 id = pci_conf_read(NULL, tag, PCI_ID_REG); 615 616 /* Invalid vendor ID value? */ 617 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 618 continue; 619 /* XXX Not invalid, but we've done this ~forever. */ 620 if (PCI_VENDOR(id) == 0) 621 continue; 622 623 switch (PCI_VENDOR(id)) { 624 case PCI_VENDOR_SIS: 625 switch (PCI_PRODUCT(id)) { 626 case PCI_PRODUCT_SIS_85C496: 627 goto disable_mem; 628 } 629 break; 630 } 631 } 632 633 return (rval); 634 635 disable_mem: 636 printf("Warning: broken PCI-Host bridge detected; " 637 "disabling memory-mapped access\n"); 638 rval &= ~(PCI_FLAGS_MEM_OKAY|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 639 PCI_FLAGS_MWI_OKAY); 640 return (rval); 641 } 642 643 void 644 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 645 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 646 { 647 pci_device_foreach_min(pc, 0, maxbus, func, context); 648 } 649 650 void 651 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 652 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 653 { 654 const struct pci_quirkdata *qd; 655 int bus, device, function, maxdevs, nfuncs; 656 pcireg_t id, bhlcr; 657 pcitag_t tag; 658 659 for (bus = minbus; bus <= maxbus; bus++) { 660 maxdevs = pci_bus_maxdevs(pc, bus); 661 for (device = 0; device < maxdevs; device++) { 662 tag = pci_make_tag(pc, bus, device, 0); 663 id = pci_conf_read(pc, tag, PCI_ID_REG); 664 665 /* Invalid vendor ID value? */ 666 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 667 continue; 668 /* XXX Not invalid, but we've done this ~forever. */ 669 if (PCI_VENDOR(id) == 0) 670 continue; 671 672 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 673 PCI_PRODUCT(id)); 674 675 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 676 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 677 (qd != NULL && 678 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 679 nfuncs = 8; 680 else 681 nfuncs = 1; 682 683 for (function = 0; function < nfuncs; function++) { 684 tag = pci_make_tag(pc, bus, device, function); 685 id = pci_conf_read(pc, tag, PCI_ID_REG); 686 687 /* Invalid vendor ID value? */ 688 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 689 continue; 690 /* 691 * XXX Not invalid, but we've done this 692 * ~forever. 693 */ 694 if (PCI_VENDOR(id) == 0) 695 continue; 696 (*func)(pc, tag, context); 697 } 698 } 699 } 700 } 701 702 void 703 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 704 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 705 { 706 struct pci_bridge_hook_arg bridge_hook; 707 708 bridge_hook.func = func; 709 bridge_hook.arg = ctx; 710 711 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 712 &bridge_hook); 713 } 714 715 static void 716 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 717 { 718 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 719 pcireg_t reg; 720 721 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 722 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 723 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 724 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 725 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 726 } 727 } 728 729 static const void * 730 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 731 { 732 switch (bit) { 733 case PCI_OVERRIDE_CONF_READ: 734 return ov->ov_conf_read; 735 case PCI_OVERRIDE_CONF_WRITE: 736 return ov->ov_conf_write; 737 case PCI_OVERRIDE_INTR_MAP: 738 return ov->ov_intr_map; 739 case PCI_OVERRIDE_INTR_STRING: 740 return ov->ov_intr_string; 741 case PCI_OVERRIDE_INTR_EVCNT: 742 return ov->ov_intr_evcnt; 743 case PCI_OVERRIDE_INTR_ESTABLISH: 744 return ov->ov_intr_establish; 745 case PCI_OVERRIDE_INTR_DISESTABLISH: 746 return ov->ov_intr_disestablish; 747 case PCI_OVERRIDE_MAKE_TAG: 748 return ov->ov_make_tag; 749 case PCI_OVERRIDE_DECOMPOSE_TAG: 750 return ov->ov_decompose_tag; 751 default: 752 return NULL; 753 } 754 } 755 756 void 757 pci_chipset_tag_destroy(pci_chipset_tag_t pc) 758 { 759 kmem_free(pc, sizeof(struct pci_chipset_tag)); 760 } 761 762 int 763 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 764 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 765 { 766 uint64_t bit, bits, nbits; 767 pci_chipset_tag_t pc; 768 const void *fp; 769 770 if (ov == NULL || present == 0) 771 return EINVAL; 772 773 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 774 775 if (pc == NULL) 776 return ENOMEM; 777 778 pc->pc_super = opc; 779 780 for (bits = present; bits != 0; bits = nbits) { 781 nbits = bits & (bits - 1); 782 bit = nbits ^ bits; 783 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 784 #ifdef DEBUG 785 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 786 #endif 787 goto einval; 788 } 789 } 790 791 pc->pc_ov = ov; 792 pc->pc_present = present; 793 pc->pc_ctx = ctx; 794 795 *pcp = pc; 796 797 return 0; 798 einval: 799 kmem_free(pc, sizeof(struct pci_chipset_tag)); 800 return EINVAL; 801 } 802 803 static void 804 x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b) 805 { 806 outb(0x3c0 + VGA_DAC_ADDRW, index); 807 outb(0x3c0 + VGA_DAC_PALETTE, (uint8_t)r >> 2); 808 outb(0x3c0 + VGA_DAC_PALETTE, (uint8_t)g >> 2); 809 outb(0x3c0 + VGA_DAC_PALETTE, (uint8_t)b >> 2); 810 } 811 812 static bool 813 x86_genfb_setmode(struct genfb_softc *sc, int newmode) 814 { 815 #if NGENFB > 0 816 static int curmode = WSDISPLAYIO_MODE_EMUL; 817 818 switch (newmode) { 819 case WSDISPLAYIO_MODE_EMUL: 820 x86_genfb_mtrr_init(sc->sc_fboffset, 821 sc->sc_height * sc->sc_stride); 822 #if NACPICA > 0 && defined(VGA_POST) 823 if (curmode != newmode) { 824 if (vga_posth != NULL && acpi_md_vesa_modenum != 0) { 825 vga_post_set_vbe(vga_posth, 826 acpi_md_vesa_modenum); 827 } 828 } 829 #endif 830 break; 831 } 832 833 curmode = newmode; 834 #endif 835 return true; 836 } 837 838 static bool 839 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual) 840 { 841 return true; 842 } 843 844 static bool 845 x86_genfb_resume(device_t dev, const pmf_qual_t *qual) 846 { 847 #if NGENFB > 0 848 struct pci_genfb_softc *psc = device_private(dev); 849 850 #if NACPICA > 0 && defined(VGA_POST) 851 if (vga_posth != NULL && acpi_md_vbios_reset == 2) { 852 vga_post_call(vga_posth); 853 if (acpi_md_vesa_modenum != 0) 854 vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum); 855 } 856 #endif 857 genfb_restore_palette(&psc->sc_gen); 858 #endif 859 860 return true; 861 } 862 863 device_t 864 device_pci_register(device_t dev, void *aux) 865 { 866 static bool found_console = false; 867 868 device_pci_props_register(dev, aux); 869 870 /* 871 * Handle network interfaces here, the attachment information is 872 * not available driver-independently later. 873 * 874 * For disks, there is nothing useful available at attach time. 875 */ 876 if (device_class(dev) == DV_IFNET) { 877 struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF); 878 if (bin == NULL) 879 return NULL; 880 881 /* 882 * We don't check the driver name against the device name 883 * passed by the boot ROM. The ROM should stay usable if 884 * the driver becomes obsolete. The physical attachment 885 * information (checked below) must be sufficient to 886 * identify the device. 887 */ 888 if (bin->bus == BI_BUS_PCI && 889 device_is_a(device_parent(dev), "pci")) { 890 struct pci_attach_args *paa = aux; 891 int b, d, f; 892 893 /* 894 * Calculate BIOS representation of: 895 * 896 * <bus,device,function> 897 * 898 * and compare. 899 */ 900 pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f); 901 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 902 return dev; 903 } 904 } 905 if (device_parent(dev) && device_is_a(device_parent(dev), "pci") && 906 found_console == false) { 907 struct btinfo_framebuffer *fbinfo; 908 struct pci_attach_args *pa = aux; 909 prop_dictionary_t dict; 910 911 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 912 #if NWSDISPLAY > 0 && NGENFB > 0 913 extern struct vcons_screen x86_genfb_console_screen; 914 struct rasops_info *ri; 915 916 ri = &x86_genfb_console_screen.scr_ri; 917 #endif 918 919 fbinfo = lookup_bootinfo(BTINFO_FRAMEBUFFER); 920 dict = device_properties(dev); 921 /* 922 * framebuffer drivers other than genfb can work 923 * without the address property 924 */ 925 if (fbinfo != NULL) { 926 if (fbinfo->physaddr != 0) { 927 prop_dictionary_set_uint32(dict, "width", 928 fbinfo->width); 929 prop_dictionary_set_uint32(dict, "height", 930 fbinfo->height); 931 prop_dictionary_set_uint8(dict, "depth", 932 fbinfo->depth); 933 prop_dictionary_set_uint16(dict, "linebytes", 934 fbinfo->stride); 935 936 prop_dictionary_set_uint64(dict, "address", 937 fbinfo->physaddr); 938 #if NWSDISPLAY > 0 && NGENFB > 0 939 if (ri->ri_bits != NULL) { 940 prop_dictionary_set_uint64(dict, 941 "virtual_address", 942 (vaddr_t)ri->ri_bits); 943 } 944 #endif 945 } 946 #if notyet 947 prop_dictionary_set_bool(dict, "splash", 948 fbinfo->flags & BI_FB_SPLASH ? 949 true : false); 950 #endif 951 if (fbinfo->depth == 8) { 952 gfb_cb.gcc_cookie = NULL; 953 gfb_cb.gcc_set_mapreg = 954 x86_genfb_set_mapreg; 955 prop_dictionary_set_uint64(dict, 956 "cmap_callback", 957 (uint64_t)(uintptr_t)&gfb_cb); 958 } 959 if (fbinfo->physaddr != 0) { 960 mode_cb.gmc_setmode = x86_genfb_setmode; 961 prop_dictionary_set_uint64(dict, 962 "mode_callback", 963 (uint64_t)(uintptr_t)&mode_cb); 964 } 965 966 #if NWSDISPLAY > 0 && NGENFB > 0 967 if (device_is_a(dev, "genfb")) { 968 x86_genfb_set_console_dev(dev); 969 #ifdef DDB 970 db_trap_callback = 971 x86_genfb_ddb_trap_callback; 972 #endif 973 } 974 #endif 975 } 976 prop_dictionary_set_bool(dict, "is_console", true); 977 prop_dictionary_set_bool(dict, "clear-screen", false); 978 #if NWSDISPLAY > 0 && NGENFB > 0 979 prop_dictionary_set_uint16(dict, "cursor-row", 980 x86_genfb_console_screen.scr_ri.ri_crow); 981 #endif 982 #if notyet 983 prop_dictionary_set_bool(dict, "splash", 984 fbinfo->flags & BI_FB_SPLASH ? true : false); 985 #endif 986 pmf_cb.gpc_suspend = x86_genfb_suspend; 987 pmf_cb.gpc_resume = x86_genfb_resume; 988 prop_dictionary_set_uint64(dict, 989 "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb); 990 #ifdef VGA_POST 991 vga_posth = vga_post_init(pa->pa_bus, pa->pa_device, 992 pa->pa_function); 993 #endif 994 found_console = true; 995 return NULL; 996 } 997 } 998 return NULL; 999 } 1000
Indexes created Fri Sep 26 20:09:58 GMT 2025