pci_machdep.c revision 1.61
1 /* $NetBSD: pci_machdep.c,v 1.61 2013/10/05 11:20:34 gson Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined in section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.61 2013/10/05 11:20:34 gson Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 #include <sys/cpu.h> 86 #include <sys/kmem.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bus_private.h> 91 92 #include <machine/pio.h> 93 #include <machine/lock.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pccbbreg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/genfb_pcivar.h> 102 103 #include <dev/wsfb/genfbvar.h> 104 #include <arch/x86/include/genfb_machdep.h> 105 #include <dev/ic/vgareg.h> 106 107 #include "acpica.h" 108 #include "genfb.h" 109 #include "isa.h" 110 #include "opt_acpi.h" 111 #include "opt_ddb.h" 112 #include "opt_mpbios.h" 113 #include "opt_vga.h" 114 #include "pci.h" 115 #include "wsdisplay.h" 116 #include "com.h" 117 118 #ifdef DDB 119 #include <machine/db_machdep.h> 120 #include <ddb/db_sym.h> 121 #include <ddb/db_extern.h> 122 #endif 123 124 #ifdef VGA_POST 125 #include <x86/vga_post.h> 126 #endif 127 128 #include <machine/autoconf.h> 129 #include <machine/bootinfo.h> 130 131 #ifdef MPBIOS 132 #include <machine/mpbiosvar.h> 133 #endif 134 135 #if NACPICA > 0 136 #include <machine/mpacpi.h> 137 #endif 138 139 #include <machine/mpconfig.h> 140 141 #if NCOM > 0 142 #include <dev/pci/puccn.h> 143 #endif 144 145 #include "opt_pci_conf_mode.h" 146 147 #ifdef PCI_CONF_MODE 148 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 149 static int pci_mode = PCI_CONF_MODE; 150 #else 151 #error Invalid PCI configuration mode. 152 #endif 153 #else 154 static int pci_mode = -1; 155 #endif 156 157 struct pci_conf_lock { 158 uint32_t cl_cpuno; /* 0: unlocked 159 * 1 + n: locked by CPU n (0 <= n) 160 */ 161 uint32_t cl_sel; /* the address that's being read. */ 162 }; 163 164 static void pci_conf_unlock(struct pci_conf_lock *); 165 static uint32_t pci_conf_selector(pcitag_t, int); 166 static unsigned int pci_conf_port(pcitag_t, int); 167 static void pci_conf_select(uint32_t); 168 static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 169 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 170 struct pci_bridge_hook_arg { 171 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 172 void *arg; 173 }; 174 175 #define PCI_MODE1_ENABLE 0x80000000UL 176 #define PCI_MODE1_ADDRESS_REG 0x0cf8 177 #define PCI_MODE1_DATA_REG 0x0cfc 178 179 #define PCI_MODE2_ENABLE_REG 0x0cf8 180 #define PCI_MODE2_FORWARD_REG 0x0cfa 181 182 #define _tag(b, d, f) \ 183 {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)} 184 #define _qe(bus, dev, fcn, vend, prod) \ 185 {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 186 const struct { 187 pcitag_t tag; 188 pcireg_t id; 189 } pcim1_quirk_tbl[] = { 190 _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */ 191 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 192 /* XXX Triflex2 not tested */ 193 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 194 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 195 /* Triton needed for Connectix Virtual PC */ 196 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 197 /* Connectix Virtual PC 5 has a 440BX */ 198 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 199 /* Parallels Desktop for Mac */ 200 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 201 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 202 /* SIS 740 */ 203 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 204 /* SIS 741 */ 205 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 206 /* VIA Technologies VX900 */ 207 _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB) 208 }; 209 #undef _tag 210 #undef _qe 211 212 /* 213 * PCI doesn't have any special needs; just use the generic versions 214 * of these functions. 215 */ 216 struct x86_bus_dma_tag pci_bus_dma_tag = { 217 ._tag_needs_free = 0, 218 #if defined(_LP64) || defined(PAE) 219 ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD, 220 ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD, 221 ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD, 222 #else 223 ._bounce_thresh = 0, 224 ._bounce_alloc_lo = 0, 225 ._bounce_alloc_hi = 0, 226 #endif 227 ._may_bounce = NULL, 228 }; 229 230 #ifdef _LP64 231 struct x86_bus_dma_tag pci_bus_dma64_tag = { 232 ._tag_needs_free = 0, 233 ._bounce_thresh = 0, 234 ._bounce_alloc_lo = 0, 235 ._bounce_alloc_hi = 0, 236 ._may_bounce = NULL, 237 }; 238 #endif 239 240 static struct pci_conf_lock cl0 = { 241 .cl_cpuno = 0UL 242 , .cl_sel = 0UL 243 }; 244 245 static struct pci_conf_lock * const cl = &cl0; 246 247 #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST) 248 extern int acpi_md_vbios_reset; 249 extern int acpi_md_vesa_modenum; 250 #endif 251 252 static struct genfb_colormap_callback gfb_cb; 253 static struct genfb_pmf_callback pmf_cb; 254 static struct genfb_mode_callback mode_cb; 255 #ifdef VGA_POST 256 static struct vga_post *vga_posth = NULL; 257 #endif 258 259 static void 260 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 261 { 262 uint32_t cpuno; 263 264 KASSERT(sel != 0); 265 266 kpreempt_disable(); 267 cpuno = cpu_number() + 1; 268 /* If the kernel enters pci_conf_lock() through an interrupt 269 * handler, then the CPU may already hold the lock. 270 * 271 * If the CPU does not already hold the lock, spin until 272 * we can acquire it. 273 */ 274 if (cpuno == cl->cl_cpuno) { 275 ocl->cl_cpuno = cpuno; 276 } else { 277 u_int spins; 278 279 ocl->cl_cpuno = 0; 280 281 spins = SPINLOCK_BACKOFF_MIN; 282 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 283 SPINLOCK_BACKOFF(spins); 284 #ifdef LOCKDEBUG 285 if (SPINLOCK_SPINOUT(spins)) { 286 panic("%s: cpu %" PRId32 287 " spun out waiting for cpu %" PRId32, 288 __func__, cpuno, cl->cl_cpuno); 289 } 290 #endif /* LOCKDEBUG */ 291 } 292 } 293 294 /* Only one CPU can be here, so an interlocked atomic_swap(3) 295 * is not necessary. 296 * 297 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 298 * and applying atomic_cas_32_ni() is not an atomic operation, 299 * however, any interrupt that, in the middle of the 300 * operation, modifies cl->cl_sel, will also restore 301 * cl->cl_sel. So cl->cl_sel will have the same value when 302 * we apply atomic_cas_32_ni() as when we evaluated it, 303 * before. 304 */ 305 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 306 pci_conf_select(sel); 307 } 308 309 static void 310 pci_conf_unlock(struct pci_conf_lock *ocl) 311 { 312 uint32_t sel; 313 314 sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 315 pci_conf_select(ocl->cl_sel); 316 if (ocl->cl_cpuno != cl->cl_cpuno) 317 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 318 kpreempt_enable(); 319 } 320 321 static uint32_t 322 pci_conf_selector(pcitag_t tag, int reg) 323 { 324 static const pcitag_t mode2_mask = { 325 .mode2 = { 326 .enable = 0xff 327 , .forward = 0xff 328 } 329 }; 330 331 switch (pci_mode) { 332 case 1: 333 return tag.mode1 | reg; 334 case 2: 335 return tag.mode1 & mode2_mask.mode1; 336 default: 337 panic("%s: mode not configured", __func__); 338 } 339 } 340 341 static unsigned int 342 pci_conf_port(pcitag_t tag, int reg) 343 { 344 switch (pci_mode) { 345 case 1: 346 return PCI_MODE1_DATA_REG; 347 case 2: 348 return tag.mode2.port | reg; 349 default: 350 panic("%s: mode not configured", __func__); 351 } 352 } 353 354 static void 355 pci_conf_select(uint32_t sel) 356 { 357 pcitag_t tag; 358 359 switch (pci_mode) { 360 case 1: 361 outl(PCI_MODE1_ADDRESS_REG, sel); 362 return; 363 case 2: 364 tag.mode1 = sel; 365 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 366 if (tag.mode2.enable != 0) 367 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 368 return; 369 default: 370 panic("%s: mode not configured", __func__); 371 } 372 } 373 374 void 375 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 376 { 377 378 if (pba->pba_bus == 0) 379 aprint_normal(": configuration mode %d", pci_mode); 380 #ifdef MPBIOS 381 mpbios_pci_attach_hook(parent, self, pba); 382 #endif 383 #if NACPICA > 0 384 mpacpi_pci_attach_hook(parent, self, pba); 385 #endif 386 } 387 388 int 389 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 390 { 391 /* 392 * Bus number is irrelevant. If Configuration Mechanism 2 is in 393 * use, can only have devices 0-15 on any bus. If Configuration 394 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 395 * range). 396 */ 397 if (pci_mode == 2) 398 return (16); 399 else 400 return (32); 401 } 402 403 pcitag_t 404 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 405 { 406 pci_chipset_tag_t ipc; 407 pcitag_t tag; 408 409 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 410 if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0) 411 continue; 412 return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx, 413 pc, bus, device, function); 414 } 415 416 switch (pci_mode) { 417 case 1: 418 if (bus >= 256 || device >= 32 || function >= 8) 419 panic("%s: bad request", __func__); 420 421 tag.mode1 = PCI_MODE1_ENABLE | 422 (bus << 16) | (device << 11) | (function << 8); 423 return tag; 424 case 2: 425 if (bus >= 256 || device >= 16 || function >= 8) 426 panic("%s: bad request", __func__); 427 428 tag.mode2.port = 0xc000 | (device << 8); 429 tag.mode2.enable = 0xf0 | (function << 1); 430 tag.mode2.forward = bus; 431 return tag; 432 default: 433 panic("%s: mode not configured", __func__); 434 } 435 } 436 437 void 438 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 439 int *bp, int *dp, int *fp) 440 { 441 pci_chipset_tag_t ipc; 442 443 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 444 if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0) 445 continue; 446 (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx, 447 pc, tag, bp, dp, fp); 448 return; 449 } 450 451 switch (pci_mode) { 452 case 1: 453 if (bp != NULL) 454 *bp = (tag.mode1 >> 16) & 0xff; 455 if (dp != NULL) 456 *dp = (tag.mode1 >> 11) & 0x1f; 457 if (fp != NULL) 458 *fp = (tag.mode1 >> 8) & 0x7; 459 return; 460 case 2: 461 if (bp != NULL) 462 *bp = tag.mode2.forward & 0xff; 463 if (dp != NULL) 464 *dp = (tag.mode2.port >> 8) & 0xf; 465 if (fp != NULL) 466 *fp = (tag.mode2.enable >> 1) & 0x7; 467 return; 468 default: 469 panic("%s: mode not configured", __func__); 470 } 471 } 472 473 pcireg_t 474 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 475 { 476 pci_chipset_tag_t ipc; 477 pcireg_t data; 478 struct pci_conf_lock ocl; 479 480 KASSERT((reg & 0x3) == 0); 481 482 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 483 if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0) 484 continue; 485 return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg); 486 } 487 488 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 489 data = inl(pci_conf_port(tag, reg)); 490 pci_conf_unlock(&ocl); 491 return data; 492 } 493 494 void 495 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 496 { 497 pci_chipset_tag_t ipc; 498 struct pci_conf_lock ocl; 499 500 KASSERT((reg & 0x3) == 0); 501 502 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 503 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 504 continue; 505 (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg, 506 data); 507 return; 508 } 509 510 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 511 outl(pci_conf_port(tag, reg), data); 512 pci_conf_unlock(&ocl); 513 } 514 515 void 516 pci_mode_set(int mode) 517 { 518 KASSERT(pci_mode == -1 || pci_mode == mode); 519 520 pci_mode = mode; 521 } 522 523 int 524 pci_mode_detect(void) 525 { 526 uint32_t sav, val; 527 int i; 528 pcireg_t idreg; 529 extern char cpu_brand_string[]; 530 531 if (pci_mode != -1) 532 return pci_mode; 533 534 /* 535 * We try to divine which configuration mode the host bridge wants. 536 */ 537 538 sav = inl(PCI_MODE1_ADDRESS_REG); 539 540 pci_mode = 1; /* assume this for now */ 541 /* 542 * catch some known buggy implementations of mode 1 543 */ 544 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 545 pcitag_t t; 546 547 if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID) 548 continue; 549 t.mode1 = pcim1_quirk_tbl[i].tag.mode1; 550 idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */ 551 if (idreg == pcim1_quirk_tbl[i].id) { 552 #ifdef DEBUG 553 printf("known mode 1 PCI chipset (%08x)\n", 554 idreg); 555 #endif 556 return (pci_mode); 557 } 558 } 559 if (memcmp(cpu_brand_string, "QEMU", 4) == 0) { 560 /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */ 561 #ifdef DEBUG 562 printf("forcing PCI mode 1 for QEMU\n"); 563 #endif 564 return (pci_mode); 565 } 566 567 /* 568 * Strong check for standard compliant mode 1: 569 * 1. bit 31 ("enable") can be set 570 * 2. byte/word access does not affect register 571 */ 572 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 573 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 574 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 575 val = inl(PCI_MODE1_ADDRESS_REG); 576 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 577 #ifdef DEBUG 578 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 579 val); 580 #endif 581 goto not1; 582 } 583 outl(PCI_MODE1_ADDRESS_REG, 0); 584 val = inl(PCI_MODE1_ADDRESS_REG); 585 if ((val & 0x80fffffc) != 0) 586 goto not1; 587 return (pci_mode); 588 not1: 589 outl(PCI_MODE1_ADDRESS_REG, sav); 590 591 /* 592 * This mode 2 check is quite weak (and known to give false 593 * positives on some Compaq machines). 594 * However, this doesn't matter, because this is the 595 * last test, and simply no PCI devices will be found if 596 * this happens. 597 */ 598 outb(PCI_MODE2_ENABLE_REG, 0); 599 outb(PCI_MODE2_FORWARD_REG, 0); 600 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 601 inb(PCI_MODE2_FORWARD_REG) != 0) 602 goto not2; 603 return (pci_mode = 2); 604 not2: 605 606 return (pci_mode = 0); 607 } 608 609 void 610 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 611 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 612 { 613 pci_device_foreach_min(pc, 0, maxbus, func, context); 614 } 615 616 void 617 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 618 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 619 { 620 const struct pci_quirkdata *qd; 621 int bus, device, function, maxdevs, nfuncs; 622 pcireg_t id, bhlcr; 623 pcitag_t tag; 624 625 for (bus = minbus; bus <= maxbus; bus++) { 626 maxdevs = pci_bus_maxdevs(pc, bus); 627 for (device = 0; device < maxdevs; device++) { 628 tag = pci_make_tag(pc, bus, device, 0); 629 id = pci_conf_read(pc, tag, PCI_ID_REG); 630 631 /* Invalid vendor ID value? */ 632 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 633 continue; 634 /* XXX Not invalid, but we've done this ~forever. */ 635 if (PCI_VENDOR(id) == 0) 636 continue; 637 638 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 639 PCI_PRODUCT(id)); 640 641 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 642 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 643 (qd != NULL && 644 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 645 nfuncs = 8; 646 else 647 nfuncs = 1; 648 649 for (function = 0; function < nfuncs; function++) { 650 tag = pci_make_tag(pc, bus, device, function); 651 id = pci_conf_read(pc, tag, PCI_ID_REG); 652 653 /* Invalid vendor ID value? */ 654 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 655 continue; 656 /* 657 * XXX Not invalid, but we've done this 658 * ~forever. 659 */ 660 if (PCI_VENDOR(id) == 0) 661 continue; 662 (*func)(pc, tag, context); 663 } 664 } 665 } 666 } 667 668 void 669 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 670 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 671 { 672 struct pci_bridge_hook_arg bridge_hook; 673 674 bridge_hook.func = func; 675 bridge_hook.arg = ctx; 676 677 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 678 &bridge_hook); 679 } 680 681 static void 682 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 683 { 684 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 685 pcireg_t reg; 686 687 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 688 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 689 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 690 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 691 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 692 } 693 } 694 695 static const void * 696 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 697 { 698 switch (bit) { 699 case PCI_OVERRIDE_CONF_READ: 700 return ov->ov_conf_read; 701 case PCI_OVERRIDE_CONF_WRITE: 702 return ov->ov_conf_write; 703 case PCI_OVERRIDE_INTR_MAP: 704 return ov->ov_intr_map; 705 case PCI_OVERRIDE_INTR_STRING: 706 return ov->ov_intr_string; 707 case PCI_OVERRIDE_INTR_EVCNT: 708 return ov->ov_intr_evcnt; 709 case PCI_OVERRIDE_INTR_ESTABLISH: 710 return ov->ov_intr_establish; 711 case PCI_OVERRIDE_INTR_DISESTABLISH: 712 return ov->ov_intr_disestablish; 713 case PCI_OVERRIDE_MAKE_TAG: 714 return ov->ov_make_tag; 715 case PCI_OVERRIDE_DECOMPOSE_TAG: 716 return ov->ov_decompose_tag; 717 default: 718 return NULL; 719 } 720 } 721 722 void 723 pci_chipset_tag_destroy(pci_chipset_tag_t pc) 724 { 725 kmem_free(pc, sizeof(struct pci_chipset_tag)); 726 } 727 728 int 729 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 730 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 731 { 732 uint64_t bit, bits, nbits; 733 pci_chipset_tag_t pc; 734 const void *fp; 735 736 if (ov == NULL || present == 0) 737 return EINVAL; 738 739 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 740 741 if (pc == NULL) 742 return ENOMEM; 743 744 pc->pc_super = opc; 745 746 for (bits = present; bits != 0; bits = nbits) { 747 nbits = bits & (bits - 1); 748 bit = nbits ^ bits; 749 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 750 #ifdef DEBUG 751 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 752 #endif 753 goto einval; 754 } 755 } 756 757 pc->pc_ov = ov; 758 pc->pc_present = present; 759 pc->pc_ctx = ctx; 760 761 *pcp = pc; 762 763 return 0; 764 einval: 765 kmem_free(pc, sizeof(struct pci_chipset_tag)); 766 return EINVAL; 767 } 768 769 static void 770 x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b) 771 { 772 outb(IO_VGA + VGA_DAC_ADDRW, index); 773 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2); 774 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2); 775 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2); 776 } 777 778 static bool 779 x86_genfb_setmode(struct genfb_softc *sc, int newmode) 780 { 781 #if NGENFB > 0 782 static int curmode = WSDISPLAYIO_MODE_EMUL; 783 784 switch (newmode) { 785 case WSDISPLAYIO_MODE_EMUL: 786 x86_genfb_mtrr_init(sc->sc_fboffset, 787 sc->sc_height * sc->sc_stride); 788 #if NACPICA > 0 && defined(VGA_POST) 789 if (curmode != newmode) { 790 if (vga_posth != NULL && acpi_md_vesa_modenum != 0) { 791 vga_post_set_vbe(vga_posth, 792 acpi_md_vesa_modenum); 793 } 794 } 795 #endif 796 break; 797 } 798 799 curmode = newmode; 800 #endif 801 return true; 802 } 803 804 static bool 805 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual) 806 { 807 return true; 808 } 809 810 static bool 811 x86_genfb_resume(device_t dev, const pmf_qual_t *qual) 812 { 813 #if NGENFB > 0 814 struct pci_genfb_softc *psc = device_private(dev); 815 816 #if NACPICA > 0 && defined(VGA_POST) 817 if (vga_posth != NULL && acpi_md_vbios_reset == 2) { 818 vga_post_call(vga_posth); 819 if (acpi_md_vesa_modenum != 0) 820 vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum); 821 } 822 #endif 823 genfb_restore_palette(&psc->sc_gen); 824 #endif 825 826 return true; 827 } 828 829 device_t 830 device_pci_register(device_t dev, void *aux) 831 { 832 static bool found_console = false; 833 834 device_pci_props_register(dev, aux); 835 836 /* 837 * Handle network interfaces here, the attachment information is 838 * not available driver-independently later. 839 * 840 * For disks, there is nothing useful available at attach time. 841 */ 842 if (device_class(dev) == DV_IFNET) { 843 struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF); 844 if (bin == NULL) 845 return NULL; 846 847 /* 848 * We don't check the driver name against the device name 849 * passed by the boot ROM. The ROM should stay usable if 850 * the driver becomes obsolete. The physical attachment 851 * information (checked below) must be sufficient to 852 * identify the device. 853 */ 854 if (bin->bus == BI_BUS_PCI && 855 device_is_a(device_parent(dev), "pci")) { 856 struct pci_attach_args *paa = aux; 857 int b, d, f; 858 859 /* 860 * Calculate BIOS representation of: 861 * 862 * <bus,device,function> 863 * 864 * and compare. 865 */ 866 pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f); 867 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 868 return dev; 869 } 870 } 871 if (device_parent(dev) && device_is_a(device_parent(dev), "pci") && 872 found_console == false) { 873 struct btinfo_framebuffer *fbinfo; 874 struct pci_attach_args *pa = aux; 875 prop_dictionary_t dict; 876 877 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 878 #if NWSDISPLAY > 0 && NGENFB > 0 879 extern struct vcons_screen x86_genfb_console_screen; 880 struct rasops_info *ri; 881 882 ri = &x86_genfb_console_screen.scr_ri; 883 #endif 884 885 fbinfo = lookup_bootinfo(BTINFO_FRAMEBUFFER); 886 dict = device_properties(dev); 887 /* 888 * framebuffer drivers other than genfb can work 889 * without the address property 890 */ 891 if (fbinfo != NULL) { 892 if (fbinfo->physaddr != 0) { 893 prop_dictionary_set_uint32(dict, "width", 894 fbinfo->width); 895 prop_dictionary_set_uint32(dict, "height", 896 fbinfo->height); 897 prop_dictionary_set_uint8(dict, "depth", 898 fbinfo->depth); 899 prop_dictionary_set_uint16(dict, "linebytes", 900 fbinfo->stride); 901 902 prop_dictionary_set_uint64(dict, "address", 903 fbinfo->physaddr); 904 #if NWSDISPLAY > 0 && NGENFB > 0 905 if (ri->ri_bits != NULL) { 906 prop_dictionary_set_uint64(dict, 907 "virtual_address", 908 (vaddr_t)ri->ri_origbits); 909 } 910 #endif 911 } 912 #if notyet 913 prop_dictionary_set_bool(dict, "splash", 914 fbinfo->flags & BI_FB_SPLASH ? 915 true : false); 916 #endif 917 if (fbinfo->depth == 8) { 918 gfb_cb.gcc_cookie = NULL; 919 gfb_cb.gcc_set_mapreg = 920 x86_genfb_set_mapreg; 921 prop_dictionary_set_uint64(dict, 922 "cmap_callback", 923 (uint64_t)(uintptr_t)&gfb_cb); 924 } 925 if (fbinfo->physaddr != 0) { 926 mode_cb.gmc_setmode = x86_genfb_setmode; 927 prop_dictionary_set_uint64(dict, 928 "mode_callback", 929 (uint64_t)(uintptr_t)&mode_cb); 930 } 931 932 #if NWSDISPLAY > 0 && NGENFB > 0 933 if (device_is_a(dev, "genfb")) { 934 x86_genfb_set_console_dev(dev); 935 #ifdef DDB 936 db_trap_callback = 937 x86_genfb_ddb_trap_callback; 938 #endif 939 } 940 #endif 941 } 942 prop_dictionary_set_bool(dict, "is_console", true); 943 944 prop_dictionary_set_bool(dict, "clear-screen", false); 945 #if NWSDISPLAY > 0 && NGENFB > 0 946 prop_dictionary_set_uint16(dict, "cursor-row", 947 x86_genfb_console_screen.scr_ri.ri_crow); 948 #endif 949 #if notyet 950 prop_dictionary_set_bool(dict, "splash", 951 fbinfo->flags & BI_FB_SPLASH ? true : false); 952 #endif 953 pmf_cb.gpc_suspend = x86_genfb_suspend; 954 pmf_cb.gpc_resume = x86_genfb_resume; 955 prop_dictionary_set_uint64(dict, 956 "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb); 957 #ifdef VGA_POST 958 vga_posth = vga_post_init(pa->pa_bus, pa->pa_device, 959 pa->pa_function); 960 #endif 961 found_console = true; 962 return NULL; 963 } 964 } 965 return NULL; 966 } 967 968 #if NCOM > 0 969 int 970 cpu_comcnprobe(struct consdev *cn, struct pci_attach_args *pa) 971 { 972 pci_mode_detect(); 973 pa->pa_iot = x86_bus_space_io; 974 pa->pa_pc = 0; 975 pa->pa_tag = pci_make_tag(0, 0, 31, 0); 976 return 0; 977 } 978 #endif 979
Indexes created Sun Sep 28 16:09:52 GMT 2025