pci_machdep.c revision 1.69
1 /* $NetBSD: pci_machdep.c,v 1.69 2014/11/07 12:48:21 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined in section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.69 2014/11/07 12:48:21 christos Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 #include <sys/cpu.h> 86 #include <sys/kmem.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bus_private.h> 91 92 #include <machine/pio.h> 93 #include <machine/lock.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pccbbreg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/genfb_pcivar.h> 102 103 #include <dev/wsfb/genfbvar.h> 104 #include <arch/x86/include/genfb_machdep.h> 105 #include <dev/ic/vgareg.h> 106 107 #include "acpica.h" 108 #include "genfb.h" 109 #include "isa.h" 110 #include "opt_acpi.h" 111 #include "opt_ddb.h" 112 #include "opt_mpbios.h" 113 #include "opt_puc.h" 114 #include "opt_vga.h" 115 #include "pci.h" 116 #include "wsdisplay.h" 117 #include "com.h" 118 119 #ifdef DDB 120 #include <machine/db_machdep.h> 121 #include <ddb/db_sym.h> 122 #include <ddb/db_extern.h> 123 #endif 124 125 #ifdef VGA_POST 126 #include <x86/vga_post.h> 127 #endif 128 129 #include <machine/autoconf.h> 130 #include <machine/bootinfo.h> 131 132 #ifdef MPBIOS 133 #include <machine/mpbiosvar.h> 134 #endif 135 136 #if NACPICA > 0 137 #include <machine/mpacpi.h> 138 #endif 139 140 #include <machine/mpconfig.h> 141 142 #if NCOM > 0 143 #include <dev/pci/puccn.h> 144 #endif 145 146 #include "opt_pci_conf_mode.h" 147 148 #ifdef PCI_CONF_MODE 149 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 150 static int pci_mode = PCI_CONF_MODE; 151 #else 152 #error Invalid PCI configuration mode. 153 #endif 154 #else 155 static int pci_mode = -1; 156 #endif 157 158 struct pci_conf_lock { 159 uint32_t cl_cpuno; /* 0: unlocked 160 * 1 + n: locked by CPU n (0 <= n) 161 */ 162 uint32_t cl_sel; /* the address that's being read. */ 163 }; 164 165 static void pci_conf_unlock(struct pci_conf_lock *); 166 static uint32_t pci_conf_selector(pcitag_t, int); 167 static unsigned int pci_conf_port(pcitag_t, int); 168 static void pci_conf_select(uint32_t); 169 static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 170 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 171 struct pci_bridge_hook_arg { 172 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 173 void *arg; 174 }; 175 176 #define PCI_MODE1_ENABLE 0x80000000UL 177 #define PCI_MODE1_ADDRESS_REG 0x0cf8 178 #define PCI_MODE1_DATA_REG 0x0cfc 179 180 #define PCI_MODE2_ENABLE_REG 0x0cf8 181 #define PCI_MODE2_FORWARD_REG 0x0cfa 182 183 #define _tag(b, d, f) \ 184 {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)} 185 #define _qe(bus, dev, fcn, vend, prod) \ 186 {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 187 const struct { 188 pcitag_t tag; 189 pcireg_t id; 190 } pcim1_quirk_tbl[] = { 191 _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */ 192 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 193 /* XXX Triflex2 not tested */ 194 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 195 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 196 /* Triton needed for Connectix Virtual PC */ 197 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 198 /* Connectix Virtual PC 5 has a 440BX */ 199 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 200 /* Parallels Desktop for Mac */ 201 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 202 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 203 /* SIS 740 */ 204 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 205 /* SIS 741 */ 206 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 207 /* VIA Technologies VX900 */ 208 _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB) 209 }; 210 #undef _tag 211 #undef _qe 212 213 /* 214 * PCI doesn't have any special needs; just use the generic versions 215 * of these functions. 216 */ 217 struct x86_bus_dma_tag pci_bus_dma_tag = { 218 ._tag_needs_free = 0, 219 #if defined(_LP64) || defined(PAE) 220 ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD, 221 ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD, 222 ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD, 223 #else 224 ._bounce_thresh = 0, 225 ._bounce_alloc_lo = 0, 226 ._bounce_alloc_hi = 0, 227 #endif 228 ._may_bounce = NULL, 229 }; 230 231 #ifdef _LP64 232 struct x86_bus_dma_tag pci_bus_dma64_tag = { 233 ._tag_needs_free = 0, 234 ._bounce_thresh = 0, 235 ._bounce_alloc_lo = 0, 236 ._bounce_alloc_hi = 0, 237 ._may_bounce = NULL, 238 }; 239 #endif 240 241 static struct pci_conf_lock cl0 = { 242 .cl_cpuno = 0UL 243 , .cl_sel = 0UL 244 }; 245 246 static struct pci_conf_lock * const cl = &cl0; 247 248 #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST) 249 extern int acpi_md_vbios_reset; 250 extern int acpi_md_vesa_modenum; 251 #endif 252 253 static struct genfb_colormap_callback gfb_cb; 254 static struct genfb_pmf_callback pmf_cb; 255 static struct genfb_mode_callback mode_cb; 256 #ifdef VGA_POST 257 static struct vga_post *vga_posth = NULL; 258 #endif 259 260 static void 261 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 262 { 263 uint32_t cpuno; 264 265 KASSERT(sel != 0); 266 267 kpreempt_disable(); 268 cpuno = cpu_number() + 1; 269 /* If the kernel enters pci_conf_lock() through an interrupt 270 * handler, then the CPU may already hold the lock. 271 * 272 * If the CPU does not already hold the lock, spin until 273 * we can acquire it. 274 */ 275 if (cpuno == cl->cl_cpuno) { 276 ocl->cl_cpuno = cpuno; 277 } else { 278 u_int spins; 279 280 ocl->cl_cpuno = 0; 281 282 spins = SPINLOCK_BACKOFF_MIN; 283 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 284 SPINLOCK_BACKOFF(spins); 285 #ifdef LOCKDEBUG 286 if (SPINLOCK_SPINOUT(spins)) { 287 panic("%s: cpu %" PRId32 288 " spun out waiting for cpu %" PRId32, 289 __func__, cpuno, cl->cl_cpuno); 290 } 291 #endif /* LOCKDEBUG */ 292 } 293 } 294 295 /* Only one CPU can be here, so an interlocked atomic_swap(3) 296 * is not necessary. 297 * 298 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 299 * and applying atomic_cas_32_ni() is not an atomic operation, 300 * however, any interrupt that, in the middle of the 301 * operation, modifies cl->cl_sel, will also restore 302 * cl->cl_sel. So cl->cl_sel will have the same value when 303 * we apply atomic_cas_32_ni() as when we evaluated it, 304 * before. 305 */ 306 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 307 pci_conf_select(sel); 308 } 309 310 static void 311 pci_conf_unlock(struct pci_conf_lock *ocl) 312 { 313 atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 314 pci_conf_select(ocl->cl_sel); 315 if (ocl->cl_cpuno != cl->cl_cpuno) 316 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 317 kpreempt_enable(); 318 } 319 320 static uint32_t 321 pci_conf_selector(pcitag_t tag, int reg) 322 { 323 static const pcitag_t mode2_mask = { 324 .mode2 = { 325 .enable = 0xff 326 , .forward = 0xff 327 } 328 }; 329 330 switch (pci_mode) { 331 case 1: 332 return tag.mode1 | reg; 333 case 2: 334 return tag.mode1 & mode2_mask.mode1; 335 default: 336 panic("%s: mode %d not configured", __func__, pci_mode); 337 } 338 } 339 340 static unsigned int 341 pci_conf_port(pcitag_t tag, int reg) 342 { 343 switch (pci_mode) { 344 case 1: 345 return PCI_MODE1_DATA_REG; 346 case 2: 347 return tag.mode2.port | reg; 348 default: 349 panic("%s: mode %d not configured", __func__, pci_mode); 350 } 351 } 352 353 static void 354 pci_conf_select(uint32_t sel) 355 { 356 pcitag_t tag; 357 358 switch (pci_mode) { 359 case 1: 360 outl(PCI_MODE1_ADDRESS_REG, sel); 361 return; 362 case 2: 363 tag.mode1 = sel; 364 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 365 if (tag.mode2.enable != 0) 366 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 367 return; 368 default: 369 panic("%s: mode %d not configured", __func__, pci_mode); 370 } 371 } 372 373 void 374 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 375 { 376 377 if (pba->pba_bus == 0) 378 aprint_normal(": configuration mode %d", pci_mode); 379 #ifdef MPBIOS 380 mpbios_pci_attach_hook(parent, self, pba); 381 #endif 382 #if NACPICA > 0 383 mpacpi_pci_attach_hook(parent, self, pba); 384 #endif 385 } 386 387 int 388 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 389 { 390 /* 391 * Bus number is irrelevant. If Configuration Mechanism 2 is in 392 * use, can only have devices 0-15 on any bus. If Configuration 393 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 394 * range). 395 */ 396 if (pci_mode == 2) 397 return (16); 398 else 399 return (32); 400 } 401 402 pcitag_t 403 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 404 { 405 pci_chipset_tag_t ipc; 406 pcitag_t tag; 407 408 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 409 if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0) 410 continue; 411 return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx, 412 pc, bus, device, function); 413 } 414 415 switch (pci_mode) { 416 case 1: 417 if (bus >= 256 || device >= 32 || function >= 8) 418 panic("%s: bad request(%d, %d, %d)", __func__, 419 bus, device, function); 420 421 tag.mode1 = PCI_MODE1_ENABLE | 422 (bus << 16) | (device << 11) | (function << 8); 423 return tag; 424 case 2: 425 if (bus >= 256 || device >= 16 || function >= 8) 426 panic("%s: bad request(%d, %d, %d)", __func__, 427 bus, device, function); 428 429 tag.mode2.port = 0xc000 | (device << 8); 430 tag.mode2.enable = 0xf0 | (function << 1); 431 tag.mode2.forward = bus; 432 return tag; 433 default: 434 panic("%s: mode %d not configured", __func__, pci_mode); 435 } 436 } 437 438 void 439 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 440 int *bp, int *dp, int *fp) 441 { 442 pci_chipset_tag_t ipc; 443 444 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 445 if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0) 446 continue; 447 (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx, 448 pc, tag, bp, dp, fp); 449 return; 450 } 451 452 switch (pci_mode) { 453 case 1: 454 if (bp != NULL) 455 *bp = (tag.mode1 >> 16) & 0xff; 456 if (dp != NULL) 457 *dp = (tag.mode1 >> 11) & 0x1f; 458 if (fp != NULL) 459 *fp = (tag.mode1 >> 8) & 0x7; 460 return; 461 case 2: 462 if (bp != NULL) 463 *bp = tag.mode2.forward & 0xff; 464 if (dp != NULL) 465 *dp = (tag.mode2.port >> 8) & 0xf; 466 if (fp != NULL) 467 *fp = (tag.mode2.enable >> 1) & 0x7; 468 return; 469 default: 470 panic("%s: mode %d not configured", __func__, pci_mode); 471 } 472 } 473 474 pcireg_t 475 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 476 { 477 pci_chipset_tag_t ipc; 478 pcireg_t data; 479 struct pci_conf_lock ocl; 480 481 KASSERT((reg & 0x3) == 0); 482 483 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 484 if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0) 485 continue; 486 return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg); 487 } 488 489 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 490 data = inl(pci_conf_port(tag, reg)); 491 pci_conf_unlock(&ocl); 492 return data; 493 } 494 495 void 496 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 497 { 498 pci_chipset_tag_t ipc; 499 struct pci_conf_lock ocl; 500 501 KASSERT((reg & 0x3) == 0); 502 503 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 504 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 505 continue; 506 (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg, 507 data); 508 return; 509 } 510 511 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 512 outl(pci_conf_port(tag, reg), data); 513 pci_conf_unlock(&ocl); 514 } 515 516 void 517 pci_mode_set(int mode) 518 { 519 KASSERT(pci_mode == -1 || pci_mode == mode); 520 521 pci_mode = mode; 522 } 523 524 int 525 pci_mode_detect(void) 526 { 527 uint32_t sav, val; 528 int i; 529 pcireg_t idreg; 530 extern char cpu_brand_string[]; 531 532 if (pci_mode != -1) 533 return pci_mode; 534 535 /* 536 * We try to divine which configuration mode the host bridge wants. 537 */ 538 539 sav = inl(PCI_MODE1_ADDRESS_REG); 540 541 pci_mode = 1; /* assume this for now */ 542 /* 543 * catch some known buggy implementations of mode 1 544 */ 545 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 546 pcitag_t t; 547 548 if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID) 549 continue; 550 t.mode1 = pcim1_quirk_tbl[i].tag.mode1; 551 idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */ 552 if (idreg == pcim1_quirk_tbl[i].id) { 553 #ifdef DEBUG 554 printf("%s: known mode 1 PCI chipset (%08x)\n", 555 __func__, idreg); 556 #endif 557 return (pci_mode); 558 } 559 } 560 561 const char *reason, *system_vendor, *system_product; 562 if (memcmp(cpu_brand_string, "QEMU", 4) == 0) 563 /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */ 564 reason = "QEMU"; 565 else if ((system_vendor = pmf_get_platform("system-vendor")) != NULL && 566 strcmp(system_vendor, "Xen") == 0 && 567 (system_product = pmf_get_platform("system-product")) != NULL && 568 strcmp(system_product, "HVM domU") == 0) 569 reason = "Xen"; 570 else 571 reason = NULL; 572 573 if (reason) { 574 #ifdef DEBUG 575 printf("%s: forcing PCI mode 1 for %s\n", __func__, reason); 576 #endif 577 return (pci_mode); 578 } 579 580 /* 581 * Strong check for standard compliant mode 1: 582 * 1. bit 31 ("enable") can be set 583 * 2. byte/word access does not affect register 584 */ 585 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 586 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 587 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 588 val = inl(PCI_MODE1_ADDRESS_REG); 589 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 590 #ifdef DEBUG 591 printf("%s: mode 1 enable failed (%x)\n", __func__, val); 592 #endif 593 goto not1; 594 } 595 outl(PCI_MODE1_ADDRESS_REG, 0); 596 val = inl(PCI_MODE1_ADDRESS_REG); 597 if ((val & 0x80fffffc) != 0) 598 goto not1; 599 return (pci_mode); 600 not1: 601 outl(PCI_MODE1_ADDRESS_REG, sav); 602 603 /* 604 * This mode 2 check is quite weak (and known to give false 605 * positives on some Compaq machines). 606 * However, this doesn't matter, because this is the 607 * last test, and simply no PCI devices will be found if 608 * this happens. 609 */ 610 outb(PCI_MODE2_ENABLE_REG, 0); 611 outb(PCI_MODE2_FORWARD_REG, 0); 612 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 613 inb(PCI_MODE2_FORWARD_REG) != 0) 614 goto not2; 615 return (pci_mode = 2); 616 not2: 617 618 return (pci_mode = 0); 619 } 620 621 void 622 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 623 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 624 { 625 pci_device_foreach_min(pc, 0, maxbus, func, context); 626 } 627 628 void 629 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 630 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 631 { 632 const struct pci_quirkdata *qd; 633 int bus, device, function, maxdevs, nfuncs; 634 pcireg_t id, bhlcr; 635 pcitag_t tag; 636 637 for (bus = minbus; bus <= maxbus; bus++) { 638 maxdevs = pci_bus_maxdevs(pc, bus); 639 for (device = 0; device < maxdevs; device++) { 640 tag = pci_make_tag(pc, bus, device, 0); 641 id = pci_conf_read(pc, tag, PCI_ID_REG); 642 643 /* Invalid vendor ID value? */ 644 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 645 continue; 646 /* XXX Not invalid, but we've done this ~forever. */ 647 if (PCI_VENDOR(id) == 0) 648 continue; 649 650 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 651 PCI_PRODUCT(id)); 652 653 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 654 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 655 (qd != NULL && 656 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 657 nfuncs = 8; 658 else 659 nfuncs = 1; 660 661 for (function = 0; function < nfuncs; function++) { 662 tag = pci_make_tag(pc, bus, device, function); 663 id = pci_conf_read(pc, tag, PCI_ID_REG); 664 665 /* Invalid vendor ID value? */ 666 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 667 continue; 668 /* 669 * XXX Not invalid, but we've done this 670 * ~forever. 671 */ 672 if (PCI_VENDOR(id) == 0) 673 continue; 674 (*func)(pc, tag, context); 675 } 676 } 677 } 678 } 679 680 void 681 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 682 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 683 { 684 struct pci_bridge_hook_arg bridge_hook; 685 686 bridge_hook.func = func; 687 bridge_hook.arg = ctx; 688 689 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 690 &bridge_hook); 691 } 692 693 static void 694 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 695 { 696 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 697 pcireg_t reg; 698 699 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 700 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 701 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 702 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 703 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 704 } 705 } 706 707 static const void * 708 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 709 { 710 switch (bit) { 711 case PCI_OVERRIDE_CONF_READ: 712 return ov->ov_conf_read; 713 case PCI_OVERRIDE_CONF_WRITE: 714 return ov->ov_conf_write; 715 case PCI_OVERRIDE_INTR_MAP: 716 return ov->ov_intr_map; 717 case PCI_OVERRIDE_INTR_STRING: 718 return ov->ov_intr_string; 719 case PCI_OVERRIDE_INTR_EVCNT: 720 return ov->ov_intr_evcnt; 721 case PCI_OVERRIDE_INTR_ESTABLISH: 722 return ov->ov_intr_establish; 723 case PCI_OVERRIDE_INTR_DISESTABLISH: 724 return ov->ov_intr_disestablish; 725 case PCI_OVERRIDE_MAKE_TAG: 726 return ov->ov_make_tag; 727 case PCI_OVERRIDE_DECOMPOSE_TAG: 728 return ov->ov_decompose_tag; 729 default: 730 return NULL; 731 } 732 } 733 734 void 735 pci_chipset_tag_destroy(pci_chipset_tag_t pc) 736 { 737 kmem_free(pc, sizeof(struct pci_chipset_tag)); 738 } 739 740 int 741 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 742 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 743 { 744 uint64_t bit, bits, nbits; 745 pci_chipset_tag_t pc; 746 const void *fp; 747 748 if (ov == NULL || present == 0) 749 return EINVAL; 750 751 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 752 753 if (pc == NULL) 754 return ENOMEM; 755 756 pc->pc_super = opc; 757 758 for (bits = present; bits != 0; bits = nbits) { 759 nbits = bits & (bits - 1); 760 bit = nbits ^ bits; 761 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 762 #ifdef DEBUG 763 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 764 #endif 765 goto einval; 766 } 767 } 768 769 pc->pc_ov = ov; 770 pc->pc_present = present; 771 pc->pc_ctx = ctx; 772 773 *pcp = pc; 774 775 return 0; 776 einval: 777 kmem_free(pc, sizeof(struct pci_chipset_tag)); 778 return EINVAL; 779 } 780 781 static void 782 x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b) 783 { 784 outb(IO_VGA + VGA_DAC_ADDRW, index); 785 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2); 786 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2); 787 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2); 788 } 789 790 static bool 791 x86_genfb_setmode(struct genfb_softc *sc, int newmode) 792 { 793 #if NGENFB > 0 794 # if NACPICA > 0 && defined(VGA_POST) 795 static int curmode = WSDISPLAYIO_MODE_EMUL; 796 # endif 797 798 switch (newmode) { 799 case WSDISPLAYIO_MODE_EMUL: 800 x86_genfb_mtrr_init(sc->sc_fboffset, 801 sc->sc_height * sc->sc_stride); 802 # if NACPICA > 0 && defined(VGA_POST) 803 if (curmode != newmode) { 804 if (vga_posth != NULL && acpi_md_vesa_modenum != 0) { 805 vga_post_set_vbe(vga_posth, 806 acpi_md_vesa_modenum); 807 } 808 } 809 # endif 810 break; 811 } 812 813 # if NACPICA > 0 && defined(VGA_POST) 814 curmode = newmode; 815 # endif 816 #endif 817 return true; 818 } 819 820 static bool 821 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual) 822 { 823 return true; 824 } 825 826 static bool 827 x86_genfb_resume(device_t dev, const pmf_qual_t *qual) 828 { 829 #if NGENFB > 0 830 struct pci_genfb_softc *psc = device_private(dev); 831 832 #if NACPICA > 0 && defined(VGA_POST) 833 if (vga_posth != NULL && acpi_md_vbios_reset == 2) { 834 vga_post_call(vga_posth); 835 if (acpi_md_vesa_modenum != 0) 836 vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum); 837 } 838 #endif 839 genfb_restore_palette(&psc->sc_gen); 840 #endif 841 842 return true; 843 } 844 845 device_t 846 device_pci_register(device_t dev, void *aux) 847 { 848 static bool found_console = false; 849 850 device_pci_props_register(dev, aux); 851 852 /* 853 * Handle network interfaces here, the attachment information is 854 * not available driver-independently later. 855 * 856 * For disks, there is nothing useful available at attach time. 857 */ 858 if (device_class(dev) == DV_IFNET) { 859 struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF); 860 if (bin == NULL) 861 return NULL; 862 863 /* 864 * We don't check the driver name against the device name 865 * passed by the boot ROM. The ROM should stay usable if 866 * the driver becomes obsolete. The physical attachment 867 * information (checked below) must be sufficient to 868 * identify the device. 869 */ 870 if (bin->bus == BI_BUS_PCI && 871 device_is_a(device_parent(dev), "pci")) { 872 struct pci_attach_args *paa = aux; 873 int b, d, f; 874 875 /* 876 * Calculate BIOS representation of: 877 * 878 * <bus,device,function> 879 * 880 * and compare. 881 */ 882 pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f); 883 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 884 return dev; 885 } 886 } 887 if (device_parent(dev) && device_is_a(device_parent(dev), "pci") && 888 found_console == false) { 889 struct btinfo_framebuffer *fbinfo; 890 struct pci_attach_args *pa = aux; 891 prop_dictionary_t dict; 892 893 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 894 #if NWSDISPLAY > 0 && NGENFB > 0 895 extern struct vcons_screen x86_genfb_console_screen; 896 struct rasops_info *ri; 897 898 ri = &x86_genfb_console_screen.scr_ri; 899 #endif 900 901 fbinfo = lookup_bootinfo(BTINFO_FRAMEBUFFER); 902 dict = device_properties(dev); 903 /* 904 * framebuffer drivers other than genfb can work 905 * without the address property 906 */ 907 if (fbinfo != NULL) { 908 if (fbinfo->physaddr != 0) { 909 prop_dictionary_set_uint32(dict, "width", 910 fbinfo->width); 911 prop_dictionary_set_uint32(dict, "height", 912 fbinfo->height); 913 prop_dictionary_set_uint8(dict, "depth", 914 fbinfo->depth); 915 prop_dictionary_set_uint16(dict, "linebytes", 916 fbinfo->stride); 917 918 prop_dictionary_set_uint64(dict, "address", 919 fbinfo->physaddr); 920 #if NWSDISPLAY > 0 && NGENFB > 0 921 if (ri->ri_bits != NULL) { 922 prop_dictionary_set_uint64(dict, 923 "virtual_address", 924 (vaddr_t)ri->ri_origbits); 925 } 926 #endif 927 } 928 #if notyet 929 prop_dictionary_set_bool(dict, "splash", 930 fbinfo->flags & BI_FB_SPLASH ? 931 true : false); 932 #endif 933 if (fbinfo->depth == 8) { 934 gfb_cb.gcc_cookie = NULL; 935 gfb_cb.gcc_set_mapreg = 936 x86_genfb_set_mapreg; 937 prop_dictionary_set_uint64(dict, 938 "cmap_callback", 939 (uint64_t)(uintptr_t)&gfb_cb); 940 } 941 if (fbinfo->physaddr != 0) { 942 mode_cb.gmc_setmode = x86_genfb_setmode; 943 prop_dictionary_set_uint64(dict, 944 "mode_callback", 945 (uint64_t)(uintptr_t)&mode_cb); 946 } 947 948 #if NWSDISPLAY > 0 && NGENFB > 0 949 if (device_is_a(dev, "genfb")) { 950 x86_genfb_set_console_dev(dev); 951 #ifdef DDB 952 db_trap_callback = 953 x86_genfb_ddb_trap_callback; 954 #endif 955 } 956 #endif 957 } 958 #if 1 && NWSDISPLAY > 0 && NGENFB > 0 959 /* XXX */ 960 if (device_is_a(dev, "genfb")) { 961 prop_dictionary_set_bool(dict, "is_console", 962 genfb_is_console()); 963 } else 964 #endif 965 prop_dictionary_set_bool(dict, "is_console", true); 966 967 prop_dictionary_set_bool(dict, "clear-screen", false); 968 #if NWSDISPLAY > 0 && NGENFB > 0 969 prop_dictionary_set_uint16(dict, "cursor-row", 970 x86_genfb_console_screen.scr_ri.ri_crow); 971 #endif 972 #if notyet 973 prop_dictionary_set_bool(dict, "splash", 974 fbinfo->flags & BI_FB_SPLASH ? true : false); 975 #endif 976 pmf_cb.gpc_suspend = x86_genfb_suspend; 977 pmf_cb.gpc_resume = x86_genfb_resume; 978 prop_dictionary_set_uint64(dict, 979 "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb); 980 #ifdef VGA_POST 981 vga_posth = vga_post_init(pa->pa_bus, pa->pa_device, 982 pa->pa_function); 983 #endif 984 found_console = true; 985 return NULL; 986 } 987 } 988 return NULL; 989 } 990 991 #ifndef PUC_CNBUS 992 #define PUC_CNBUS 0 993 #endif 994 995 #if NCOM > 0 996 int 997 cpu_puc_cnprobe(struct consdev *cn, struct pci_attach_args *pa) 998 { 999 pci_mode_detect(); 1000 pa->pa_iot = x86_bus_space_io; 1001 pa->pa_memt = x86_bus_space_mem; 1002 pa->pa_pc = 0; 1003 pa->pa_tag = pci_make_tag(0, PUC_CNBUS, pci_bus_maxdevs(NULL, 0) - 1, 1004 0); 1005 1006 return 0; 1007 } 1008 #endif 1009
Indexes created Sat Sep 27 22:09:54 GMT 2025