pci_machdep.c revision 1.73
1 /* $NetBSD: pci_machdep.c,v 1.73 2015/11/26 16:27:05 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined in section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.73 2015/11/26 16:27:05 jakllsch Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/bus.h> 85 #include <sys/cpu.h> 86 #include <sys/kmem.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bus_private.h> 91 92 #include <machine/pio.h> 93 #include <machine/lock.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pccbbreg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/genfb_pcivar.h> 102 103 #include <dev/wsfb/genfbvar.h> 104 #include <arch/x86/include/genfb_machdep.h> 105 #include <dev/ic/vgareg.h> 106 107 #include "acpica.h" 108 #include "genfb.h" 109 #include "isa.h" 110 #include "opt_acpi.h" 111 #include "opt_ddb.h" 112 #include "opt_mpbios.h" 113 #include "opt_puc.h" 114 #include "opt_vga.h" 115 #include "pci.h" 116 #include "wsdisplay.h" 117 #include "com.h" 118 119 #ifdef DDB 120 #include <machine/db_machdep.h> 121 #include <ddb/db_sym.h> 122 #include <ddb/db_extern.h> 123 #endif 124 125 #ifdef VGA_POST 126 #include <x86/vga_post.h> 127 #endif 128 129 #include <x86/cpuvar.h> 130 131 #include <machine/autoconf.h> 132 #include <machine/bootinfo.h> 133 134 #ifdef MPBIOS 135 #include <machine/mpbiosvar.h> 136 #endif 137 138 #if NACPICA > 0 139 #include <machine/mpacpi.h> 140 #if !defined(NO_PCI_EXTENDED_CONFIG) 141 #include <dev/acpi/acpivar.h> 142 #include <dev/acpi/acpi_mcfg.h> 143 #endif 144 #endif 145 146 #include <machine/mpconfig.h> 147 148 #if NCOM > 0 149 #include <dev/pci/puccn.h> 150 #endif 151 152 #include "opt_pci_conf_mode.h" 153 154 #ifdef PCI_CONF_MODE 155 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 156 static int pci_mode = PCI_CONF_MODE; 157 #else 158 #error Invalid PCI configuration mode. 159 #endif 160 #else 161 static int pci_mode = -1; 162 #endif 163 164 struct pci_conf_lock { 165 uint32_t cl_cpuno; /* 0: unlocked 166 * 1 + n: locked by CPU n (0 <= n) 167 */ 168 uint32_t cl_sel; /* the address that's being read. */ 169 }; 170 171 static void pci_conf_unlock(struct pci_conf_lock *); 172 static uint32_t pci_conf_selector(pcitag_t, int); 173 static unsigned int pci_conf_port(pcitag_t, int); 174 static void pci_conf_select(uint32_t); 175 static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 176 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 177 struct pci_bridge_hook_arg { 178 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 179 void *arg; 180 }; 181 182 #define PCI_MODE1_ENABLE 0x80000000UL 183 #define PCI_MODE1_ADDRESS_REG 0x0cf8 184 #define PCI_MODE1_DATA_REG 0x0cfc 185 186 #define PCI_MODE2_ENABLE_REG 0x0cf8 187 #define PCI_MODE2_FORWARD_REG 0x0cfa 188 189 #define _tag(b, d, f) \ 190 {.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)} 191 #define _qe(bus, dev, fcn, vend, prod) \ 192 {_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 193 const struct { 194 pcitag_t tag; 195 pcireg_t id; 196 } pcim1_quirk_tbl[] = { 197 _qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */ 198 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 199 /* XXX Triflex2 not tested */ 200 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 201 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 202 /* Triton needed for Connectix Virtual PC */ 203 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 204 /* Connectix Virtual PC 5 has a 440BX */ 205 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 206 /* Parallels Desktop for Mac */ 207 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 208 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 209 /* SIS 740 */ 210 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 211 /* SIS 741 */ 212 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 213 /* VIA Technologies VX900 */ 214 _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB) 215 }; 216 #undef _tag 217 #undef _qe 218 219 /* arch/xen does not support MSI/MSI-X yet. */ 220 #ifdef __HAVE_PCI_MSI_MSIX 221 #define PCI_QUIRK_DISABLE_MSI 1 /* Neigher MSI nor MSI-X work */ 222 #define PCI_QUIRK_DISABLE_MSIX 2 /* MSI-X does not work */ 223 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI and MSI-X works */ 224 225 #define _dme(vend, prod) \ 226 { PCI_QUIRK_DISABLE_MSI, PCI_ID_CODE(vend, prod) } 227 #define _dmxe(vend, prod) \ 228 { PCI_QUIRK_DISABLE_MSIX, PCI_ID_CODE(vend, prod) } 229 #define _emve(vend, prod) \ 230 { PCI_QUIRK_ENABLE_MSI_VM, PCI_ID_CODE(vend, prod) } 231 const struct { 232 int type; 233 pcireg_t id; 234 } pci_msi_quirk_tbl[] = { 235 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCMC), 236 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 237 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437MX), 238 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437VX), 239 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439HX), 240 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439TX), 241 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX), 242 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_AGP), 243 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX), 244 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), 245 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), 246 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_AGP), 247 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 248 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_NOAGP), 249 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX), 250 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX_AGP), 251 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810_MCH), 252 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810E_MCH), 253 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82815_FULL_HUB), 254 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82820_MCH), 255 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82830MP_IO_1), 256 _dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82840_HB), 257 _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_PCHB), 258 _dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_PCHB), 259 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC751_SC), 260 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC761_SC), 261 _dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC762_NB), 262 263 _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), /* QEMU */ 264 _emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), /* VMWare */ 265 }; 266 #undef _dme 267 #undef _dmxe 268 #undef _emve 269 #endif /* __HAVE_PCI_MSI_MSIX */ 270 271 /* 272 * PCI doesn't have any special needs; just use the generic versions 273 * of these functions. 274 */ 275 struct x86_bus_dma_tag pci_bus_dma_tag = { 276 ._tag_needs_free = 0, 277 #if defined(_LP64) || defined(PAE) 278 ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD, 279 ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD, 280 ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD, 281 #else 282 ._bounce_thresh = 0, 283 ._bounce_alloc_lo = 0, 284 ._bounce_alloc_hi = 0, 285 #endif 286 ._may_bounce = NULL, 287 }; 288 289 #ifdef _LP64 290 struct x86_bus_dma_tag pci_bus_dma64_tag = { 291 ._tag_needs_free = 0, 292 ._bounce_thresh = 0, 293 ._bounce_alloc_lo = 0, 294 ._bounce_alloc_hi = 0, 295 ._may_bounce = NULL, 296 }; 297 #endif 298 299 static struct pci_conf_lock cl0 = { 300 .cl_cpuno = 0UL 301 , .cl_sel = 0UL 302 }; 303 304 static struct pci_conf_lock * const cl = &cl0; 305 306 #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST) 307 extern int acpi_md_vbios_reset; 308 extern int acpi_md_vesa_modenum; 309 #endif 310 311 static struct genfb_colormap_callback gfb_cb; 312 static struct genfb_pmf_callback pmf_cb; 313 static struct genfb_mode_callback mode_cb; 314 #ifdef VGA_POST 315 static struct vga_post *vga_posth = NULL; 316 #endif 317 318 static void 319 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 320 { 321 uint32_t cpuno; 322 323 KASSERT(sel != 0); 324 325 kpreempt_disable(); 326 cpuno = cpu_number() + 1; 327 /* If the kernel enters pci_conf_lock() through an interrupt 328 * handler, then the CPU may already hold the lock. 329 * 330 * If the CPU does not already hold the lock, spin until 331 * we can acquire it. 332 */ 333 if (cpuno == cl->cl_cpuno) { 334 ocl->cl_cpuno = cpuno; 335 } else { 336 u_int spins; 337 338 ocl->cl_cpuno = 0; 339 340 spins = SPINLOCK_BACKOFF_MIN; 341 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 342 SPINLOCK_BACKOFF(spins); 343 #ifdef LOCKDEBUG 344 if (SPINLOCK_SPINOUT(spins)) { 345 panic("%s: cpu %" PRId32 346 " spun out waiting for cpu %" PRId32, 347 __func__, cpuno, cl->cl_cpuno); 348 } 349 #endif /* LOCKDEBUG */ 350 } 351 } 352 353 /* Only one CPU can be here, so an interlocked atomic_swap(3) 354 * is not necessary. 355 * 356 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 357 * and applying atomic_cas_32_ni() is not an atomic operation, 358 * however, any interrupt that, in the middle of the 359 * operation, modifies cl->cl_sel, will also restore 360 * cl->cl_sel. So cl->cl_sel will have the same value when 361 * we apply atomic_cas_32_ni() as when we evaluated it, 362 * before. 363 */ 364 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 365 pci_conf_select(sel); 366 } 367 368 static void 369 pci_conf_unlock(struct pci_conf_lock *ocl) 370 { 371 atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 372 pci_conf_select(ocl->cl_sel); 373 if (ocl->cl_cpuno != cl->cl_cpuno) 374 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 375 kpreempt_enable(); 376 } 377 378 static uint32_t 379 pci_conf_selector(pcitag_t tag, int reg) 380 { 381 static const pcitag_t mode2_mask = { 382 .mode2 = { 383 .enable = 0xff 384 , .forward = 0xff 385 } 386 }; 387 388 switch (pci_mode) { 389 case 1: 390 return tag.mode1 | reg; 391 case 2: 392 return tag.mode1 & mode2_mask.mode1; 393 default: 394 panic("%s: mode %d not configured", __func__, pci_mode); 395 } 396 } 397 398 static unsigned int 399 pci_conf_port(pcitag_t tag, int reg) 400 { 401 switch (pci_mode) { 402 case 1: 403 return PCI_MODE1_DATA_REG; 404 case 2: 405 return tag.mode2.port | reg; 406 default: 407 panic("%s: mode %d not configured", __func__, pci_mode); 408 } 409 } 410 411 static void 412 pci_conf_select(uint32_t sel) 413 { 414 pcitag_t tag; 415 416 switch (pci_mode) { 417 case 1: 418 outl(PCI_MODE1_ADDRESS_REG, sel); 419 return; 420 case 2: 421 tag.mode1 = sel; 422 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 423 if (tag.mode2.enable != 0) 424 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 425 return; 426 default: 427 panic("%s: mode %d not configured", __func__, pci_mode); 428 } 429 } 430 431 #ifdef __HAVE_PCI_MSI_MSIX 432 static int 433 pci_has_msi_quirk(pcireg_t id, int type) 434 { 435 int i; 436 437 for (i = 0; i < __arraycount(pci_msi_quirk_tbl); i++) { 438 if (id == pci_msi_quirk_tbl[i].id && 439 type == pci_msi_quirk_tbl[i].type) 440 return 1; 441 } 442 443 return 0; 444 } 445 #endif 446 447 void 448 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 449 { 450 #ifdef __HAVE_PCI_MSI_MSIX 451 pci_chipset_tag_t pc = pba->pba_pc; 452 pcitag_t tag; 453 pcireg_t id, class; 454 #endif 455 456 if (pba->pba_bus == 0) 457 aprint_normal(": configuration mode %d", pci_mode); 458 #ifdef MPBIOS 459 mpbios_pci_attach_hook(parent, self, pba); 460 #endif 461 #if NACPICA > 0 462 mpacpi_pci_attach_hook(parent, self, pba); 463 #endif 464 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 465 acpimcfg_map_bus(self, pba->pba_pc, pba->pba_bus); 466 #endif 467 468 #ifdef __HAVE_PCI_MSI_MSIX 469 /* 470 * In order to decide whether the system supports MSI we look 471 * at the host bridge, which should be device 0 function 0 on 472 * bus 0. It is better to not enable MSI on systems that 473 * support it than the other way around, so be conservative 474 * here. So we don't enable MSI if we don't find a host 475 * bridge there. We also deliberately don't enable MSI on 476 * chipsets from low-end manifacturers like VIA and SiS. 477 */ 478 tag = pci_make_tag(pc, 0, 0, 0); 479 id = pci_conf_read(pc, tag, PCI_ID_REG); 480 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 481 482 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 483 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST) 484 return; 485 486 if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSI)) { 487 pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY; 488 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 489 aprint_verbose_dev(self, "This pci host supports neither MSI nor MSI-X.\n"); 490 } else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSIX)) { 491 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 492 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 493 aprint_verbose_dev(self, "This pci host does not support MSI-X.\n"); 494 } else { 495 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 496 pba->pba_flags |= PCI_FLAGS_MSIX_OKAY; 497 } 498 499 /* VMware and KVM use old chipset, but they can use MSI/MSI-X */ 500 if (cpu_feature[1] & CPUID2_RAZ) { 501 if (pci_has_msi_quirk(id, PCI_QUIRK_ENABLE_MSI_VM)) { 502 pba->pba_flags |= PCI_FLAGS_MSI_OKAY; 503 pba->pba_flags |= PCI_FLAGS_MSIX_OKAY; 504 } 505 } 506 507 /* 508 * Don't enable MSI on a HyperTransport bus. In order to 509 * determine that bus 0 is a HyperTransport bus, we look at 510 * device 24 function 0, which is the HyperTransport 511 * host/primary interface integrated on most 64-bit AMD CPUs. 512 * If that device has a HyperTransport capability, bus 0 must 513 * be a HyperTransport bus and we disable MSI. 514 */ 515 tag = pci_make_tag(pc, 0, 24, 0); 516 if (pci_get_capability(pc, tag, PCI_CAP_LDT, NULL, NULL)) { 517 pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY; 518 pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY; 519 } 520 #endif /* __HAVE_PCI_MSI_MSIX */ 521 } 522 523 int 524 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 525 { 526 /* 527 * Bus number is irrelevant. If Configuration Mechanism 2 is in 528 * use, can only have devices 0-15 on any bus. If Configuration 529 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 530 * range). 531 */ 532 if (pci_mode == 2) 533 return (16); 534 else 535 return (32); 536 } 537 538 pcitag_t 539 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 540 { 541 pci_chipset_tag_t ipc; 542 pcitag_t tag; 543 544 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 545 if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0) 546 continue; 547 return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx, 548 pc, bus, device, function); 549 } 550 551 switch (pci_mode) { 552 case 1: 553 if (bus >= 256 || device >= 32 || function >= 8) 554 panic("%s: bad request(%d, %d, %d)", __func__, 555 bus, device, function); 556 557 tag.mode1 = PCI_MODE1_ENABLE | 558 (bus << 16) | (device << 11) | (function << 8); 559 return tag; 560 case 2: 561 if (bus >= 256 || device >= 16 || function >= 8) 562 panic("%s: bad request(%d, %d, %d)", __func__, 563 bus, device, function); 564 565 tag.mode2.port = 0xc000 | (device << 8); 566 tag.mode2.enable = 0xf0 | (function << 1); 567 tag.mode2.forward = bus; 568 return tag; 569 default: 570 panic("%s: mode %d not configured", __func__, pci_mode); 571 } 572 } 573 574 void 575 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 576 int *bp, int *dp, int *fp) 577 { 578 pci_chipset_tag_t ipc; 579 580 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 581 if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0) 582 continue; 583 (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx, 584 pc, tag, bp, dp, fp); 585 return; 586 } 587 588 switch (pci_mode) { 589 case 1: 590 if (bp != NULL) 591 *bp = (tag.mode1 >> 16) & 0xff; 592 if (dp != NULL) 593 *dp = (tag.mode1 >> 11) & 0x1f; 594 if (fp != NULL) 595 *fp = (tag.mode1 >> 8) & 0x7; 596 return; 597 case 2: 598 if (bp != NULL) 599 *bp = tag.mode2.forward & 0xff; 600 if (dp != NULL) 601 *dp = (tag.mode2.port >> 8) & 0xf; 602 if (fp != NULL) 603 *fp = (tag.mode2.enable >> 1) & 0x7; 604 return; 605 default: 606 panic("%s: mode %d not configured", __func__, pci_mode); 607 } 608 } 609 610 pcireg_t 611 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 612 { 613 pci_chipset_tag_t ipc; 614 pcireg_t data; 615 struct pci_conf_lock ocl; 616 int dev; 617 618 KASSERT((reg & 0x3) == 0); 619 620 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 621 if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0) 622 continue; 623 return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg); 624 } 625 626 pci_decompose_tag(pc, tag, NULL, &dev, NULL); 627 if (__predict_false(pci_mode == 2 && dev >= 16)) 628 return (pcireg_t) -1; 629 630 if (reg < 0) 631 return (pcireg_t) -1; 632 if (reg >= PCI_CONF_SIZE) { 633 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 634 if (reg >= PCI_EXTCONF_SIZE) 635 return (pcireg_t) -1; 636 acpimcfg_conf_read(pc, tag, reg, &data); 637 return data; 638 #else 639 return (pcireg_t) -1; 640 #endif 641 } 642 643 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 644 data = inl(pci_conf_port(tag, reg)); 645 pci_conf_unlock(&ocl); 646 return data; 647 } 648 649 void 650 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 651 { 652 pci_chipset_tag_t ipc; 653 struct pci_conf_lock ocl; 654 int dev; 655 656 KASSERT((reg & 0x3) == 0); 657 658 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 659 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 660 continue; 661 (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg, 662 data); 663 return; 664 } 665 666 pci_decompose_tag(pc, tag, NULL, &dev, NULL); 667 if (__predict_false(pci_mode == 2 && dev >= 16)) { 668 return; 669 } 670 671 if (reg < 0) 672 return; 673 if (reg >= PCI_CONF_SIZE) { 674 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG) 675 if (reg >= PCI_EXTCONF_SIZE) 676 return; 677 acpimcfg_conf_write(pc, tag, reg, data); 678 #endif 679 return; 680 } 681 682 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 683 outl(pci_conf_port(tag, reg), data); 684 pci_conf_unlock(&ocl); 685 } 686 687 void 688 pci_mode_set(int mode) 689 { 690 KASSERT(pci_mode == -1 || pci_mode == mode); 691 692 pci_mode = mode; 693 } 694 695 int 696 pci_mode_detect(void) 697 { 698 uint32_t sav, val; 699 int i; 700 pcireg_t idreg; 701 extern char cpu_brand_string[]; 702 703 if (pci_mode != -1) 704 return pci_mode; 705 706 /* 707 * We try to divine which configuration mode the host bridge wants. 708 */ 709 710 sav = inl(PCI_MODE1_ADDRESS_REG); 711 712 pci_mode = 1; /* assume this for now */ 713 /* 714 * catch some known buggy implementations of mode 1 715 */ 716 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 717 pcitag_t t; 718 719 if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID) 720 continue; 721 t.mode1 = pcim1_quirk_tbl[i].tag.mode1; 722 idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */ 723 if (idreg == pcim1_quirk_tbl[i].id) { 724 #ifdef DEBUG 725 printf("%s: known mode 1 PCI chipset (%08x)\n", 726 __func__, idreg); 727 #endif 728 return (pci_mode); 729 } 730 } 731 732 const char *reason, *system_vendor, *system_product; 733 if (memcmp(cpu_brand_string, "QEMU", 4) == 0) 734 /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */ 735 reason = "QEMU"; 736 else if ((system_vendor = pmf_get_platform("system-vendor")) != NULL && 737 strcmp(system_vendor, "Xen") == 0 && 738 (system_product = pmf_get_platform("system-product")) != NULL && 739 strcmp(system_product, "HVM domU") == 0) 740 reason = "Xen"; 741 else 742 reason = NULL; 743 744 if (reason) { 745 #ifdef DEBUG 746 printf("%s: forcing PCI mode 1 for %s\n", __func__, reason); 747 #endif 748 return (pci_mode); 749 } 750 751 /* 752 * Strong check for standard compliant mode 1: 753 * 1. bit 31 ("enable") can be set 754 * 2. byte/word access does not affect register 755 */ 756 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 757 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 758 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 759 val = inl(PCI_MODE1_ADDRESS_REG); 760 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 761 #ifdef DEBUG 762 printf("%s: mode 1 enable failed (%x)\n", __func__, val); 763 #endif 764 goto not1; 765 } 766 outl(PCI_MODE1_ADDRESS_REG, 0); 767 val = inl(PCI_MODE1_ADDRESS_REG); 768 if ((val & 0x80fffffc) != 0) 769 goto not1; 770 return (pci_mode); 771 not1: 772 outl(PCI_MODE1_ADDRESS_REG, sav); 773 774 /* 775 * This mode 2 check is quite weak (and known to give false 776 * positives on some Compaq machines). 777 * However, this doesn't matter, because this is the 778 * last test, and simply no PCI devices will be found if 779 * this happens. 780 */ 781 outb(PCI_MODE2_ENABLE_REG, 0); 782 outb(PCI_MODE2_FORWARD_REG, 0); 783 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 784 inb(PCI_MODE2_FORWARD_REG) != 0) 785 goto not2; 786 return (pci_mode = 2); 787 not2: 788 789 return (pci_mode = 0); 790 } 791 792 void 793 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 794 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 795 { 796 pci_device_foreach_min(pc, 0, maxbus, func, context); 797 } 798 799 void 800 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 801 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 802 { 803 const struct pci_quirkdata *qd; 804 int bus, device, function, maxdevs, nfuncs; 805 pcireg_t id, bhlcr; 806 pcitag_t tag; 807 808 for (bus = minbus; bus <= maxbus; bus++) { 809 maxdevs = pci_bus_maxdevs(pc, bus); 810 for (device = 0; device < maxdevs; device++) { 811 tag = pci_make_tag(pc, bus, device, 0); 812 id = pci_conf_read(pc, tag, PCI_ID_REG); 813 814 /* Invalid vendor ID value? */ 815 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 816 continue; 817 /* XXX Not invalid, but we've done this ~forever. */ 818 if (PCI_VENDOR(id) == 0) 819 continue; 820 821 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 822 PCI_PRODUCT(id)); 823 824 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 825 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 826 (qd != NULL && 827 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 828 nfuncs = 8; 829 else 830 nfuncs = 1; 831 832 for (function = 0; function < nfuncs; function++) { 833 tag = pci_make_tag(pc, bus, device, function); 834 id = pci_conf_read(pc, tag, PCI_ID_REG); 835 836 /* Invalid vendor ID value? */ 837 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 838 continue; 839 /* 840 * XXX Not invalid, but we've done this 841 * ~forever. 842 */ 843 if (PCI_VENDOR(id) == 0) 844 continue; 845 (*func)(pc, tag, context); 846 } 847 } 848 } 849 } 850 851 void 852 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 853 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 854 { 855 struct pci_bridge_hook_arg bridge_hook; 856 857 bridge_hook.func = func; 858 bridge_hook.arg = ctx; 859 860 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 861 &bridge_hook); 862 } 863 864 static void 865 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 866 { 867 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 868 pcireg_t reg; 869 870 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 871 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 872 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 873 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 874 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 875 } 876 } 877 878 static const void * 879 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 880 { 881 switch (bit) { 882 case PCI_OVERRIDE_CONF_READ: 883 return ov->ov_conf_read; 884 case PCI_OVERRIDE_CONF_WRITE: 885 return ov->ov_conf_write; 886 case PCI_OVERRIDE_INTR_MAP: 887 return ov->ov_intr_map; 888 case PCI_OVERRIDE_INTR_STRING: 889 return ov->ov_intr_string; 890 case PCI_OVERRIDE_INTR_EVCNT: 891 return ov->ov_intr_evcnt; 892 case PCI_OVERRIDE_INTR_ESTABLISH: 893 return ov->ov_intr_establish; 894 case PCI_OVERRIDE_INTR_DISESTABLISH: 895 return ov->ov_intr_disestablish; 896 case PCI_OVERRIDE_MAKE_TAG: 897 return ov->ov_make_tag; 898 case PCI_OVERRIDE_DECOMPOSE_TAG: 899 return ov->ov_decompose_tag; 900 default: 901 return NULL; 902 } 903 } 904 905 void 906 pci_chipset_tag_destroy(pci_chipset_tag_t pc) 907 { 908 kmem_free(pc, sizeof(struct pci_chipset_tag)); 909 } 910 911 int 912 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 913 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 914 { 915 uint64_t bit, bits, nbits; 916 pci_chipset_tag_t pc; 917 const void *fp; 918 919 if (ov == NULL || present == 0) 920 return EINVAL; 921 922 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 923 924 if (pc == NULL) 925 return ENOMEM; 926 927 pc->pc_super = opc; 928 929 for (bits = present; bits != 0; bits = nbits) { 930 nbits = bits & (bits - 1); 931 bit = nbits ^ bits; 932 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 933 #ifdef DEBUG 934 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 935 #endif 936 goto einval; 937 } 938 } 939 940 pc->pc_ov = ov; 941 pc->pc_present = present; 942 pc->pc_ctx = ctx; 943 944 *pcp = pc; 945 946 return 0; 947 einval: 948 kmem_free(pc, sizeof(struct pci_chipset_tag)); 949 return EINVAL; 950 } 951 952 static void 953 x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b) 954 { 955 outb(IO_VGA + VGA_DAC_ADDRW, index); 956 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2); 957 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2); 958 outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2); 959 } 960 961 static bool 962 x86_genfb_setmode(struct genfb_softc *sc, int newmode) 963 { 964 #if NGENFB > 0 965 # if NACPICA > 0 && defined(VGA_POST) 966 static int curmode = WSDISPLAYIO_MODE_EMUL; 967 # endif 968 969 switch (newmode) { 970 case WSDISPLAYIO_MODE_EMUL: 971 x86_genfb_mtrr_init(sc->sc_fboffset, 972 sc->sc_height * sc->sc_stride); 973 # if NACPICA > 0 && defined(VGA_POST) 974 if (curmode != newmode) { 975 if (vga_posth != NULL && acpi_md_vesa_modenum != 0) { 976 vga_post_set_vbe(vga_posth, 977 acpi_md_vesa_modenum); 978 } 979 } 980 # endif 981 break; 982 } 983 984 # if NACPICA > 0 && defined(VGA_POST) 985 curmode = newmode; 986 # endif 987 #endif 988 return true; 989 } 990 991 static bool 992 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual) 993 { 994 return true; 995 } 996 997 static bool 998 x86_genfb_resume(device_t dev, const pmf_qual_t *qual) 999 { 1000 #if NGENFB > 0 1001 struct pci_genfb_softc *psc = device_private(dev); 1002 1003 #if NACPICA > 0 && defined(VGA_POST) 1004 if (vga_posth != NULL && acpi_md_vbios_reset == 2) { 1005 vga_post_call(vga_posth); 1006 if (acpi_md_vesa_modenum != 0) 1007 vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum); 1008 } 1009 #endif 1010 genfb_restore_palette(&psc->sc_gen); 1011 #endif 1012 1013 return true; 1014 } 1015 1016 device_t 1017 device_pci_register(device_t dev, void *aux) 1018 { 1019 static bool found_console = false; 1020 1021 device_pci_props_register(dev, aux); 1022 1023 /* 1024 * Handle network interfaces here, the attachment information is 1025 * not available driver-independently later. 1026 * 1027 * For disks, there is nothing useful available at attach time. 1028 */ 1029 if (device_class(dev) == DV_IFNET) { 1030 struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF); 1031 if (bin == NULL) 1032 return NULL; 1033 1034 /* 1035 * We don't check the driver name against the device name 1036 * passed by the boot ROM. The ROM should stay usable if 1037 * the driver becomes obsolete. The physical attachment 1038 * information (checked below) must be sufficient to 1039 * identify the device. 1040 */ 1041 if (bin->bus == BI_BUS_PCI && 1042 device_is_a(device_parent(dev), "pci")) { 1043 struct pci_attach_args *paa = aux; 1044 int b, d, f; 1045 1046 /* 1047 * Calculate BIOS representation of: 1048 * 1049 * <bus,device,function> 1050 * 1051 * and compare. 1052 */ 1053 pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f); 1054 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 1055 return dev; 1056 } 1057 } 1058 if (device_parent(dev) && device_is_a(device_parent(dev), "pci") && 1059 found_console == false) { 1060 struct btinfo_framebuffer *fbinfo; 1061 struct pci_attach_args *pa = aux; 1062 prop_dictionary_t dict; 1063 1064 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 1065 #if NWSDISPLAY > 0 && NGENFB > 0 1066 extern struct vcons_screen x86_genfb_console_screen; 1067 struct rasops_info *ri; 1068 1069 ri = &x86_genfb_console_screen.scr_ri; 1070 #endif 1071 1072 fbinfo = lookup_bootinfo(BTINFO_FRAMEBUFFER); 1073 dict = device_properties(dev); 1074 /* 1075 * framebuffer drivers other than genfb can work 1076 * without the address property 1077 */ 1078 if (fbinfo != NULL) { 1079 if (fbinfo->physaddr != 0) { 1080 prop_dictionary_set_uint32(dict, "width", 1081 fbinfo->width); 1082 prop_dictionary_set_uint32(dict, "height", 1083 fbinfo->height); 1084 prop_dictionary_set_uint8(dict, "depth", 1085 fbinfo->depth); 1086 prop_dictionary_set_uint16(dict, "linebytes", 1087 fbinfo->stride); 1088 1089 prop_dictionary_set_uint64(dict, "address", 1090 fbinfo->physaddr); 1091 #if NWSDISPLAY > 0 && NGENFB > 0 1092 if (ri->ri_bits != NULL) { 1093 prop_dictionary_set_uint64(dict, 1094 "virtual_address", 1095 (vaddr_t)ri->ri_origbits); 1096 } 1097 #endif 1098 } 1099 #if notyet 1100 prop_dictionary_set_bool(dict, "splash", 1101 fbinfo->flags & BI_FB_SPLASH ? 1102 true : false); 1103 #endif 1104 if (fbinfo->depth == 8) { 1105 gfb_cb.gcc_cookie = NULL; 1106 gfb_cb.gcc_set_mapreg = 1107 x86_genfb_set_mapreg; 1108 prop_dictionary_set_uint64(dict, 1109 "cmap_callback", 1110 (uint64_t)(uintptr_t)&gfb_cb); 1111 } 1112 if (fbinfo->physaddr != 0) { 1113 mode_cb.gmc_setmode = x86_genfb_setmode; 1114 prop_dictionary_set_uint64(dict, 1115 "mode_callback", 1116 (uint64_t)(uintptr_t)&mode_cb); 1117 } 1118 1119 #if NWSDISPLAY > 0 && NGENFB > 0 1120 if (device_is_a(dev, "genfb")) { 1121 x86_genfb_set_console_dev(dev); 1122 #ifdef DDB 1123 db_trap_callback = 1124 x86_genfb_ddb_trap_callback; 1125 #endif 1126 } 1127 #endif 1128 } 1129 #if 1 && NWSDISPLAY > 0 && NGENFB > 0 1130 /* XXX */ 1131 if (device_is_a(dev, "genfb")) { 1132 prop_dictionary_set_bool(dict, "is_console", 1133 genfb_is_console()); 1134 } else 1135 #endif 1136 prop_dictionary_set_bool(dict, "is_console", true); 1137 1138 prop_dictionary_set_bool(dict, "clear-screen", false); 1139 #if NWSDISPLAY > 0 && NGENFB > 0 1140 prop_dictionary_set_uint16(dict, "cursor-row", 1141 x86_genfb_console_screen.scr_ri.ri_crow); 1142 #endif 1143 #if notyet 1144 prop_dictionary_set_bool(dict, "splash", 1145 fbinfo->flags & BI_FB_SPLASH ? true : false); 1146 #endif 1147 pmf_cb.gpc_suspend = x86_genfb_suspend; 1148 pmf_cb.gpc_resume = x86_genfb_resume; 1149 prop_dictionary_set_uint64(dict, 1150 "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb); 1151 #ifdef VGA_POST 1152 vga_posth = vga_post_init(pa->pa_bus, pa->pa_device, 1153 pa->pa_function); 1154 #endif 1155 found_console = true; 1156 return NULL; 1157 } 1158 } 1159 return NULL; 1160 } 1161 1162 #ifndef PUC_CNBUS 1163 #define PUC_CNBUS 0 1164 #endif 1165 1166 #if NCOM > 0 1167 int 1168 cpu_puc_cnprobe(struct consdev *cn, struct pci_attach_args *pa) 1169 { 1170 pci_mode_detect(); 1171 pa->pa_iot = x86_bus_space_io; 1172 pa->pa_memt = x86_bus_space_mem; 1173 pa->pa_pc = 0; 1174 pa->pa_tag = pci_make_tag(0, PUC_CNBUS, pci_bus_maxdevs(NULL, 0) - 1, 1175 0); 1176 1177 return 0; 1178 } 1179 #endif 1180
Indexes created Wed Sep 24 22:09:59 GMT 2025