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cpu.c revision 1.11
      1  1.11    ad /*	$NetBSD: cpu.c,v 1.11 2007/12/04 16:05:34 ad Exp $	*/
      2   1.2    ad 
      3   1.2    ad /*-
      4   1.7    ad  * Copyright (c) 2000, 2006, 2007 The NetBSD Foundation, Inc.
      5   1.2    ad  * All rights reserved.
      6   1.2    ad  *
      7   1.2    ad  * This code is derived from software contributed to The NetBSD Foundation
      8  1.11    ad  * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran.
      9   1.2    ad  *
     10   1.2    ad  * Redistribution and use in source and binary forms, with or without
     11   1.2    ad  * modification, are permitted provided that the following conditions
     12   1.2    ad  * are met:
     13   1.2    ad  * 1. Redistributions of source code must retain the above copyright
     14   1.2    ad  *    notice, this list of conditions and the following disclaimer.
     15   1.2    ad  * 2. Redistributions in binary form must reproduce the above copyright
     16   1.2    ad  *    notice, this list of conditions and the following disclaimer in the
     17   1.2    ad  *    documentation and/or other materials provided with the distribution.
     18   1.2    ad  * 3. All advertising materials mentioning features or use of this software
     19   1.2    ad  *    must display the following acknowledgement:
     20   1.2    ad  *        This product includes software developed by the NetBSD
     21   1.2    ad  *        Foundation, Inc. and its contributors.
     22   1.2    ad  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23   1.2    ad  *    contributors may be used to endorse or promote products derived
     24   1.2    ad  *    from this software without specific prior written permission.
     25   1.2    ad  *
     26   1.2    ad  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27   1.2    ad  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28   1.2    ad  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29   1.2    ad  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30   1.2    ad  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31   1.2    ad  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32   1.2    ad  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33   1.2    ad  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34   1.2    ad  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35   1.2    ad  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36   1.2    ad  * POSSIBILITY OF SUCH DAMAGE.
     37   1.2    ad  */
     38   1.2    ad 
     39   1.2    ad /*
     40   1.2    ad  * Copyright (c) 1999 Stefan Grefen
     41   1.2    ad  *
     42   1.2    ad  * Redistribution and use in source and binary forms, with or without
     43   1.2    ad  * modification, are permitted provided that the following conditions
     44   1.2    ad  * are met:
     45   1.2    ad  * 1. Redistributions of source code must retain the above copyright
     46   1.2    ad  *    notice, this list of conditions and the following disclaimer.
     47   1.2    ad  * 2. Redistributions in binary form must reproduce the above copyright
     48   1.2    ad  *    notice, this list of conditions and the following disclaimer in the
     49   1.2    ad  *    documentation and/or other materials provided with the distribution.
     50   1.2    ad  * 3. All advertising materials mentioning features or use of this software
     51   1.2    ad  *    must display the following acknowledgement:
     52   1.2    ad  *      This product includes software developed by the NetBSD
     53   1.2    ad  *      Foundation, Inc. and its contributors.
     54   1.2    ad  * 4. Neither the name of The NetBSD Foundation nor the names of its
     55   1.2    ad  *    contributors may be used to endorse or promote products derived
     56   1.2    ad  *    from this software without specific prior written permission.
     57   1.2    ad  *
     58   1.2    ad  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
     59   1.2    ad  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     60   1.2    ad  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     61   1.2    ad  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
     62   1.2    ad  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     63   1.2    ad  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     64   1.2    ad  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     65   1.2    ad  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     66   1.2    ad  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     67   1.2    ad  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     68   1.2    ad  * SUCH DAMAGE.
     69   1.2    ad  */
     70   1.2    ad 
     71   1.2    ad #include <sys/cdefs.h>
     72  1.11    ad __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.11 2007/12/04 16:05:34 ad Exp $");
     73   1.2    ad 
     74   1.2    ad #include "opt_ddb.h"
     75   1.2    ad #include "opt_multiprocessor.h"
     76   1.2    ad #include "opt_mpbios.h"		/* for MPDEBUG */
     77   1.2    ad #include "opt_mtrr.h"
     78   1.2    ad 
     79   1.2    ad #include "lapic.h"
     80   1.2    ad #include "ioapic.h"
     81   1.2    ad 
     82   1.2    ad #include <sys/param.h>
     83   1.2    ad #include <sys/proc.h>
     84   1.2    ad #include <sys/user.h>
     85   1.2    ad #include <sys/systm.h>
     86   1.2    ad #include <sys/device.h>
     87   1.2    ad #include <sys/malloc.h>
     88   1.9    ad #include <sys/cpu.h>
     89   1.9    ad #include <sys/atomic.h>
     90   1.2    ad 
     91   1.2    ad #include <uvm/uvm_extern.h>
     92   1.2    ad 
     93   1.2    ad #include <machine/cpufunc.h>
     94   1.2    ad #include <machine/cpuvar.h>
     95   1.2    ad #include <machine/pmap.h>
     96   1.2    ad #include <machine/vmparam.h>
     97   1.2    ad #include <machine/mpbiosvar.h>
     98   1.2    ad #include <machine/pcb.h>
     99   1.2    ad #include <machine/specialreg.h>
    100   1.2    ad #include <machine/segments.h>
    101   1.2    ad #include <machine/gdt.h>
    102   1.2    ad #include <machine/mtrr.h>
    103   1.2    ad #include <machine/pio.h>
    104   1.2    ad 
    105   1.2    ad #ifdef i386
    106   1.2    ad #include <machine/tlog.h>
    107   1.2    ad #endif
    108   1.2    ad 
    109   1.2    ad #if NLAPIC > 0
    110   1.2    ad #include <machine/apicvar.h>
    111   1.2    ad #include <machine/i82489reg.h>
    112   1.2    ad #include <machine/i82489var.h>
    113   1.2    ad #endif
    114   1.2    ad 
    115   1.2    ad #if NIOAPIC > 0
    116   1.2    ad #include <machine/i82093var.h>
    117   1.2    ad #endif
    118   1.2    ad 
    119   1.2    ad #include <dev/ic/mc146818reg.h>
    120   1.2    ad #include <i386/isa/nvram.h>
    121   1.2    ad #include <dev/isa/isareg.h>
    122   1.2    ad 
    123   1.2    ad int     cpu_match(struct device *, struct cfdata *, void *);
    124   1.2    ad void    cpu_attach(struct device *, struct device *, void *);
    125   1.2    ad 
    126   1.2    ad struct cpu_softc {
    127   1.2    ad 	struct device sc_dev;		/* device tree glue */
    128   1.2    ad 	struct cpu_info *sc_info;	/* pointer to CPU info */
    129   1.2    ad };
    130   1.2    ad 
    131   1.2    ad int mp_cpu_start(struct cpu_info *);
    132   1.2    ad void mp_cpu_start_cleanup(struct cpu_info *);
    133   1.2    ad const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL,
    134   1.2    ad 					    mp_cpu_start_cleanup };
    135   1.2    ad 
    136   1.2    ad 
    137   1.2    ad CFATTACH_DECL(cpu, sizeof(struct cpu_softc),
    138   1.2    ad     cpu_match, cpu_attach, NULL, NULL);
    139   1.2    ad 
    140   1.2    ad /*
    141   1.2    ad  * Statically-allocated CPU info for the primary CPU (or the only
    142   1.2    ad  * CPU, on uniprocessors).  The CPU info list is initialized to
    143   1.2    ad  * point at it.
    144   1.2    ad  */
    145   1.2    ad #ifdef TRAPLOG
    146   1.2    ad struct tlog tlog_primary;
    147   1.2    ad #endif
    148   1.2    ad struct cpu_info cpu_info_primary = {
    149   1.2    ad 	.ci_dev = 0,
    150   1.2    ad 	.ci_self = &cpu_info_primary,
    151   1.2    ad 	.ci_idepth = -1,
    152   1.2    ad 	.ci_curlwp = &lwp0,
    153   1.2    ad #ifdef TRAPLOG
    154   1.2    ad 	.ci_tlog_base = &tlog_primary,
    155   1.2    ad #endif /* !TRAPLOG */
    156   1.2    ad };
    157   1.2    ad 
    158   1.2    ad struct cpu_info *cpu_info_list = &cpu_info_primary;
    159   1.2    ad 
    160   1.2    ad static void	cpu_set_tss_gates(struct cpu_info *ci);
    161   1.2    ad 
    162   1.2    ad #ifdef i386
    163   1.2    ad static void	cpu_init_tss(struct i386tss *, void *, void *);
    164   1.2    ad #endif
    165   1.2    ad 
    166   1.2    ad uint32_t cpus_attached = 0;
    167   1.9    ad uint32_t cpus_running = 0;
    168   1.2    ad 
    169   1.2    ad extern char x86_64_doubleflt_stack[];
    170   1.2    ad 
    171   1.2    ad #ifdef MULTIPROCESSOR
    172   1.2    ad /*
    173   1.2    ad  * Array of CPU info structures.  Must be statically-allocated because
    174   1.2    ad  * curproc, etc. are used early.
    175   1.2    ad  */
    176   1.2    ad struct cpu_info *cpu_info[X86_MAXPROCS] = { &cpu_info_primary, };
    177   1.2    ad 
    178   1.2    ad void    	cpu_hatch(void *);
    179   1.2    ad static void    	cpu_boot_secondary(struct cpu_info *ci);
    180   1.2    ad static void    	cpu_start_secondary(struct cpu_info *ci);
    181   1.2    ad static void	cpu_copy_trampoline(void);
    182   1.2    ad 
    183   1.2    ad /*
    184   1.2    ad  * Runs once per boot once multiprocessor goo has been detected and
    185   1.2    ad  * the local APIC on the boot processor has been mapped.
    186   1.2    ad  *
    187   1.2    ad  * Called from lapic_boot_init() (from mpbios_scan()).
    188   1.2    ad  */
    189   1.2    ad void
    190   1.9    ad cpu_init_first(void)
    191   1.2    ad {
    192   1.2    ad 	int cpunum = lapic_cpu_number();
    193   1.2    ad 
    194   1.2    ad 	if (cpunum != 0) {
    195   1.2    ad 		cpu_info[0] = NULL;
    196   1.2    ad 		cpu_info[cpunum] = &cpu_info_primary;
    197   1.2    ad 	}
    198   1.2    ad 
    199   1.2    ad 	cpu_info_primary.ci_cpuid = cpunum;
    200   1.2    ad 	cpu_copy_trampoline();
    201   1.2    ad }
    202   1.2    ad #endif
    203   1.2    ad 
    204   1.2    ad int
    205   1.2    ad cpu_match(struct device *parent, struct cfdata *match,
    206   1.2    ad     void *aux)
    207   1.2    ad {
    208   1.2    ad 
    209   1.2    ad 	return 1;
    210   1.2    ad }
    211   1.2    ad 
    212   1.2    ad static void
    213   1.2    ad cpu_vm_init(struct cpu_info *ci)
    214   1.2    ad {
    215   1.2    ad 	int ncolors = 2, i;
    216   1.2    ad 
    217   1.2    ad 	for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) {
    218   1.2    ad 		struct x86_cache_info *cai;
    219   1.2    ad 		int tcolors;
    220   1.2    ad 
    221   1.2    ad 		cai = &ci->ci_cinfo[i];
    222   1.2    ad 
    223   1.2    ad 		tcolors = atop(cai->cai_totalsize);
    224   1.2    ad 		switch(cai->cai_associativity) {
    225   1.2    ad 		case 0xff:
    226   1.2    ad 			tcolors = 1; /* fully associative */
    227   1.2    ad 			break;
    228   1.2    ad 		case 0:
    229   1.2    ad 		case 1:
    230   1.2    ad 			break;
    231   1.2    ad 		default:
    232   1.2    ad 			tcolors /= cai->cai_associativity;
    233   1.2    ad 		}
    234   1.2    ad 		ncolors = max(ncolors, tcolors);
    235   1.2    ad 	}
    236   1.2    ad 
    237   1.2    ad 	/*
    238   1.2    ad 	 * Knowing the size of the largest cache on this CPU, re-color
    239   1.2    ad 	 * our pages.
    240   1.2    ad 	 */
    241   1.2    ad 	if (ncolors <= uvmexp.ncolors)
    242   1.2    ad 		return;
    243   1.2    ad 	aprint_verbose("%s: %d page colors\n", ci->ci_dev->dv_xname, ncolors);
    244   1.2    ad 	uvm_page_recolor(ncolors);
    245   1.2    ad }
    246   1.2    ad 
    247   1.2    ad 
    248   1.2    ad void
    249   1.2    ad cpu_attach(struct device *parent, struct device *self, void *aux)
    250   1.2    ad {
    251   1.2    ad 	struct cpu_softc *sc = (void *) self;
    252   1.2    ad 	struct cpu_attach_args *caa = aux;
    253   1.2    ad 	struct cpu_info *ci;
    254   1.2    ad #if defined(MULTIPROCESSOR)
    255   1.2    ad 	int cpunum = caa->cpu_number;
    256   1.2    ad #endif
    257   1.2    ad 
    258   1.2    ad 	/*
    259   1.2    ad 	 * If we're an Application Processor, allocate a cpu_info
    260   1.2    ad 	 * structure, otherwise use the primary's.
    261   1.2    ad 	 */
    262   1.2    ad 	if (caa->cpu_role == CPU_ROLE_AP) {
    263   1.2    ad 		aprint_naive(": Application Processor\n");
    264   1.2    ad 		ci = malloc(sizeof(*ci), M_DEVBUF, M_WAITOK);
    265   1.2    ad 		memset(ci, 0, sizeof(*ci));
    266   1.2    ad #if defined(MULTIPROCESSOR)
    267   1.2    ad 		if (cpu_info[cpunum] != NULL) {
    268   1.2    ad 			printf("\n");
    269   1.2    ad 			panic("cpu at apic id %d already attached?", cpunum);
    270   1.2    ad 		}
    271   1.2    ad 		cpu_info[cpunum] = ci;
    272   1.2    ad #endif
    273   1.2    ad #ifdef TRAPLOG
    274   1.2    ad 		ci->ci_tlog_base = malloc(sizeof(struct tlog),
    275   1.2    ad 		    M_DEVBUF, M_WAITOK);
    276   1.2    ad #endif
    277   1.2    ad 	} else {
    278   1.2    ad 		aprint_naive(": %s Processor\n",
    279   1.2    ad 		    caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot");
    280   1.2    ad 		ci = &cpu_info_primary;
    281   1.2    ad #if defined(MULTIPROCESSOR)
    282   1.2    ad 		if (cpunum != lapic_cpu_number()) {
    283   1.2    ad 			printf("\n");
    284   1.2    ad 			panic("%s: running CPU is at apic %d"
    285   1.2    ad 			    " instead of at expected %d",
    286   1.2    ad 			    sc->sc_dev.dv_xname, lapic_cpu_number(), cpunum);
    287   1.2    ad 		}
    288   1.2    ad #endif
    289   1.2    ad 	}
    290   1.2    ad 
    291   1.2    ad 	ci->ci_self = ci;
    292   1.2    ad 	sc->sc_info = ci;
    293   1.2    ad 
    294   1.2    ad 	ci->ci_dev = self;
    295   1.2    ad 	ci->ci_apicid = caa->cpu_number;
    296   1.2    ad #ifdef MULTIPROCESSOR
    297   1.2    ad 	ci->ci_cpuid = ci->ci_apicid;
    298   1.2    ad #else
    299   1.2    ad 	ci->ci_cpuid = 0;	/* False for APs, but they're not used anyway */
    300   1.2    ad #endif
    301   1.2    ad 	ci->ci_cpumask = (1 << ci->ci_cpuid);
    302   1.2    ad 	ci->ci_func = caa->cpu_func;
    303   1.2    ad 
    304   1.2    ad 	if (caa->cpu_role == CPU_ROLE_AP) {
    305   1.2    ad #ifdef MULTIPROCESSOR
    306   1.2    ad 		int error;
    307   1.2    ad 
    308   1.2    ad 		error = mi_cpu_attach(ci);
    309   1.2    ad 		if (error != 0) {
    310   1.2    ad 			aprint_normal("\n");
    311   1.2    ad 			aprint_error("%s: mi_cpu_attach failed with %d\n",
    312   1.2    ad 			    sc->sc_dev.dv_xname, error);
    313   1.2    ad 			return;
    314   1.2    ad 		}
    315   1.2    ad #endif
    316   1.2    ad 	} else {
    317   1.2    ad 		KASSERT(ci->ci_data.cpu_idlelwp != NULL);
    318   1.2    ad 	}
    319   1.2    ad 
    320   1.2    ad 	pmap_reference(pmap_kernel());
    321   1.2    ad 	ci->ci_pmap = pmap_kernel();
    322   1.2    ad 	ci->ci_tlbstate = TLBSTATE_STALE;
    323   1.2    ad 
    324   1.2    ad 	/* further PCB init done later. */
    325   1.2    ad 
    326   1.2    ad 	switch (caa->cpu_role) {
    327   1.2    ad 	case CPU_ROLE_SP:
    328   1.2    ad 		aprint_normal(": (uniprocessor)\n");
    329   1.9    ad 		atomic_or_32(&ci->ci_flags,
    330   1.9    ad 		    CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY);
    331   1.2    ad 		cpu_intr_init(ci);
    332   1.2    ad 		identifycpu(ci);
    333   1.2    ad 		cpu_init(ci);
    334   1.2    ad 		cpu_set_tss_gates(ci);
    335   1.2    ad 		pmap_cpu_init_late(ci);
    336   1.6    ad 		x86_errata();
    337   1.2    ad 		break;
    338   1.2    ad 
    339   1.2    ad 	case CPU_ROLE_BP:
    340   1.2    ad 		aprint_normal(": (boot processor)\n");
    341   1.9    ad 		atomic_or_32(&ci->ci_flags,
    342   1.9    ad 		    CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY);
    343   1.2    ad 		cpu_intr_init(ci);
    344   1.2    ad 		identifycpu(ci);
    345   1.2    ad 		cpu_init(ci);
    346   1.2    ad 		cpu_set_tss_gates(ci);
    347   1.2    ad 		pmap_cpu_init_late(ci);
    348   1.2    ad #if NLAPIC > 0
    349   1.2    ad 		/*
    350   1.2    ad 		 * Enable local apic
    351   1.2    ad 		 */
    352   1.2    ad 		lapic_enable();
    353   1.2    ad 		lapic_calibrate_timer(ci);
    354   1.2    ad #endif
    355   1.2    ad #if NIOAPIC > 0
    356   1.2    ad 		ioapic_bsp_id = caa->cpu_number;
    357   1.2    ad #endif
    358   1.6    ad 		x86_errata();
    359   1.2    ad 		break;
    360   1.2    ad 
    361   1.2    ad 	case CPU_ROLE_AP:
    362   1.2    ad 		/*
    363   1.2    ad 		 * report on an AP
    364   1.2    ad 		 */
    365   1.2    ad 		aprint_normal(": (application processor)\n");
    366   1.2    ad 
    367   1.2    ad #if defined(MULTIPROCESSOR)
    368   1.2    ad 		cpu_intr_init(ci);
    369   1.2    ad 		gdt_alloc_cpu(ci);
    370   1.2    ad 		cpu_set_tss_gates(ci);
    371   1.2    ad 		pmap_cpu_init_early(ci);
    372   1.2    ad 		pmap_cpu_init_late(ci);
    373   1.2    ad 		cpu_start_secondary(ci);
    374   1.2    ad 		if (ci->ci_flags & CPUF_PRESENT) {
    375   1.2    ad 			identifycpu(ci);
    376   1.2    ad 			ci->ci_next = cpu_info_list->ci_next;
    377   1.2    ad 			cpu_info_list->ci_next = ci;
    378   1.2    ad 		}
    379   1.2    ad #else
    380   1.2    ad 		aprint_normal("%s: not started\n", sc->sc_dev.dv_xname);
    381   1.2    ad #endif
    382   1.2    ad 		break;
    383   1.2    ad 
    384   1.2    ad 	default:
    385   1.2    ad 		printf("\n");
    386   1.2    ad 		panic("unknown processor type??\n");
    387   1.2    ad 	}
    388   1.2    ad 	cpu_vm_init(ci);
    389   1.2    ad 
    390   1.2    ad 	cpus_attached |= ci->ci_cpumask;
    391   1.2    ad 
    392   1.2    ad #if defined(MULTIPROCESSOR)
    393   1.2    ad 	if (mp_verbose) {
    394   1.2    ad 		struct lwp *l = ci->ci_data.cpu_idlelwp;
    395   1.2    ad 
    396   1.2    ad 		aprint_verbose(
    397   1.2    ad 		    "%s: idle lwp at %p, idle sp at %p\n",
    398   1.2    ad 		    sc->sc_dev.dv_xname, l,
    399   1.2    ad #ifdef i386
    400   1.2    ad 		    (void *)l->l_addr->u_pcb.pcb_esp
    401   1.2    ad #else
    402   1.2    ad 		    (void *)l->l_addr->u_pcb.pcb_rsp
    403   1.2    ad #endif
    404   1.2    ad 		);
    405   1.2    ad 	}
    406   1.2    ad #endif
    407   1.2    ad }
    408   1.2    ad 
    409   1.2    ad /*
    410   1.2    ad  * Initialize the processor appropriately.
    411   1.2    ad  */
    412   1.2    ad 
    413   1.2    ad void
    414   1.9    ad cpu_init(struct cpu_info *ci)
    415   1.2    ad {
    416   1.2    ad 	/* configure the CPU if needed */
    417   1.2    ad 	if (ci->cpu_setup != NULL)
    418   1.2    ad 		(*ci->cpu_setup)(ci);
    419   1.2    ad 
    420   1.2    ad #ifdef i386
    421   1.2    ad 	/*
    422   1.2    ad 	 * On a 486 or above, enable ring 0 write protection.
    423   1.2    ad 	 */
    424   1.2    ad 	if (ci->ci_cpu_class >= CPUCLASS_486)
    425   1.2    ad 		lcr0(rcr0() | CR0_WP);
    426   1.2    ad #else
    427   1.2    ad 	lcr0(rcr0() | CR0_WP);
    428   1.2    ad #endif
    429   1.2    ad 
    430   1.2    ad 	/*
    431   1.2    ad 	 * On a P6 or above, enable global TLB caching if the
    432   1.2    ad 	 * hardware supports it.
    433   1.2    ad 	 */
    434   1.2    ad 	if (cpu_feature & CPUID_PGE)
    435   1.2    ad 		lcr4(rcr4() | CR4_PGE);	/* enable global TLB caching */
    436   1.2    ad 
    437   1.2    ad 	/*
    438   1.2    ad 	 * If we have FXSAVE/FXRESTOR, use them.
    439   1.2    ad 	 */
    440   1.2    ad 	if (cpu_feature & CPUID_FXSR) {
    441   1.2    ad 		lcr4(rcr4() | CR4_OSFXSR);
    442   1.2    ad 
    443   1.2    ad 		/*
    444   1.2    ad 		 * If we have SSE/SSE2, enable XMM exceptions.
    445   1.2    ad 		 */
    446   1.2    ad 		if (cpu_feature & (CPUID_SSE|CPUID_SSE2))
    447   1.2    ad 			lcr4(rcr4() | CR4_OSXMMEXCPT);
    448   1.2    ad 	}
    449   1.2    ad 
    450   1.2    ad #ifdef MTRR
    451   1.2    ad 	/*
    452   1.2    ad 	 * On a P6 or above, initialize MTRR's if the hardware supports them.
    453   1.2    ad 	 */
    454   1.2    ad 	if (cpu_feature & CPUID_MTRR) {
    455   1.2    ad 		if ((ci->ci_flags & CPUF_AP) == 0)
    456   1.2    ad 			i686_mtrr_init_first();
    457   1.2    ad 		mtrr_init_cpu(ci);
    458   1.2    ad 	}
    459   1.2    ad 
    460   1.2    ad #ifdef i386
    461   1.2    ad 	if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) {
    462   1.2    ad 		/*
    463   1.2    ad 		 * Must be a K6-2 Step >= 7 or a K6-III.
    464   1.2    ad 		 */
    465   1.2    ad 		if (CPUID2FAMILY(ci->ci_signature) == 5) {
    466   1.2    ad 			if (CPUID2MODEL(ci->ci_signature) > 8 ||
    467   1.2    ad 			    (CPUID2MODEL(ci->ci_signature) == 8 &&
    468   1.2    ad 			     CPUID2STEPPING(ci->ci_signature) >= 7)) {
    469   1.2    ad 				mtrr_funcs = &k6_mtrr_funcs;
    470   1.2    ad 				k6_mtrr_init_first();
    471   1.2    ad 				mtrr_init_cpu(ci);
    472   1.2    ad 			}
    473   1.2    ad 		}
    474   1.2    ad 	}
    475   1.2    ad #endif	/* i386 */
    476   1.2    ad #endif /* MTRR */
    477   1.2    ad 
    478   1.9    ad 	atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
    479   1.9    ad 	atomic_or_32(&cpus_running, ci->ci_cpumask);
    480   1.9    ad 
    481   1.9    ad #ifndef MULTIPROCESSOR
    482   1.5    ad 	/* XXX */
    483   1.5    ad 	x86_patch();
    484   1.2    ad #endif
    485   1.2    ad }
    486   1.2    ad 
    487   1.2    ad bool x86_mp_online;
    488   1.2    ad 
    489   1.2    ad #ifdef MULTIPROCESSOR
    490   1.2    ad void
    491   1.2    ad cpu_boot_secondary_processors()
    492   1.2    ad {
    493   1.2    ad 	struct cpu_info *ci;
    494   1.2    ad 	u_long i;
    495   1.2    ad 
    496   1.5    ad 	/* Now that we know the number of CPUs, patch the text segment. */
    497   1.5    ad 	x86_patch();
    498   1.5    ad 
    499   1.2    ad 	for (i=0; i < X86_MAXPROCS; i++) {
    500   1.2    ad 		ci = cpu_info[i];
    501   1.2    ad 		if (ci == NULL)
    502   1.2    ad 			continue;
    503   1.2    ad 		if (ci->ci_data.cpu_idlelwp == NULL)
    504   1.2    ad 			continue;
    505   1.2    ad 		if ((ci->ci_flags & CPUF_PRESENT) == 0)
    506   1.2    ad 			continue;
    507   1.2    ad 		if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY))
    508   1.2    ad 			continue;
    509   1.2    ad 		cpu_boot_secondary(ci);
    510   1.2    ad 	}
    511   1.2    ad 
    512   1.2    ad 	x86_mp_online = true;
    513   1.2    ad }
    514   1.2    ad 
    515   1.2    ad static void
    516   1.2    ad cpu_init_idle_lwp(struct cpu_info *ci)
    517   1.2    ad {
    518   1.2    ad 	struct lwp *l = ci->ci_data.cpu_idlelwp;
    519   1.2    ad 	struct pcb *pcb = &l->l_addr->u_pcb;
    520   1.2    ad 
    521   1.2    ad 	pcb->pcb_cr0 = rcr0();
    522   1.2    ad }
    523   1.2    ad 
    524   1.2    ad void
    525   1.2    ad cpu_init_idle_lwps()
    526   1.2    ad {
    527   1.2    ad 	struct cpu_info *ci;
    528   1.2    ad 	u_long i;
    529   1.2    ad 
    530   1.2    ad 	for (i = 0; i < X86_MAXPROCS; i++) {
    531   1.2    ad 		ci = cpu_info[i];
    532   1.2    ad 		if (ci == NULL)
    533   1.2    ad 			continue;
    534   1.2    ad 		if (ci->ci_data.cpu_idlelwp == NULL)
    535   1.2    ad 			continue;
    536   1.2    ad 		if ((ci->ci_flags & CPUF_PRESENT) == 0)
    537   1.2    ad 			continue;
    538   1.2    ad 		cpu_init_idle_lwp(ci);
    539   1.2    ad 	}
    540   1.2    ad }
    541   1.2    ad 
    542   1.2    ad void
    543   1.2    ad cpu_start_secondary(ci)
    544   1.2    ad 	struct cpu_info *ci;
    545   1.2    ad {
    546   1.2    ad 	int i;
    547   1.2    ad 	struct pmap *kpm = pmap_kernel();
    548   1.2    ad 	extern paddr_t mp_pdirpa;
    549   1.2    ad 
    550   1.2    ad #ifdef __x86_64__
    551   1.2    ad 	/*
    552   1.2    ad 	 * The initial PML4 pointer must be below 4G, so if the
    553   1.2    ad 	 * current one isn't, use a "bounce buffer"
    554   1.2    ad 	 *
    555   1.2    ad 	 * XXX move elsewhere, not per CPU.
    556   1.2    ad 	 */
    557   1.2    ad 	if (kpm->pm_pdirpa > 0xffffffff) {
    558   1.2    ad 		extern vaddr_t lo32_vaddr;
    559   1.2    ad 		extern paddr_t lo32_paddr;
    560   1.2    ad 		memcpy((void *)lo32_vaddr, kpm->pm_pdir, PAGE_SIZE);
    561   1.2    ad 		mp_pdirpa = lo32_paddr;
    562   1.2    ad 	} else
    563   1.2    ad #endif
    564   1.2    ad 		mp_pdirpa = kpm->pm_pdirpa;
    565   1.2    ad 
    566   1.9    ad 	atomic_or_32(&ci->ci_flags, CPUF_AP);
    567   1.2    ad 
    568   1.2    ad 	aprint_debug("%s: starting\n", ci->ci_dev->dv_xname);
    569   1.2    ad 
    570   1.2    ad 	ci->ci_curlwp = ci->ci_data.cpu_idlelwp;
    571   1.2    ad 	CPU_STARTUP(ci);
    572   1.2    ad 
    573   1.2    ad 	/*
    574   1.2    ad 	 * wait for it to become ready
    575   1.2    ad 	 */
    576   1.2    ad 	for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i>0;i--) {
    577  1.11    ad 		i8254_delay(10);
    578   1.2    ad 	}
    579   1.9    ad 	if ((ci->ci_flags & CPUF_PRESENT) == 0) {
    580   1.2    ad 		aprint_error("%s: failed to become ready\n",
    581   1.2    ad 		    ci->ci_dev->dv_xname);
    582   1.2    ad #if defined(MPDEBUG) && defined(DDB)
    583   1.2    ad 		printf("dropping into debugger; continue from here to resume boot\n");
    584   1.2    ad 		Debugger();
    585   1.2    ad #endif
    586   1.2    ad 	}
    587   1.2    ad 
    588   1.2    ad 	CPU_START_CLEANUP(ci);
    589   1.2    ad }
    590   1.2    ad 
    591   1.2    ad void
    592   1.2    ad cpu_boot_secondary(ci)
    593   1.2    ad 	struct cpu_info *ci;
    594   1.2    ad {
    595   1.2    ad 	int i;
    596   1.2    ad 
    597   1.9    ad 	atomic_or_32(&ci->ci_flags, CPUF_GO);
    598   1.2    ad 	for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i>0;i--) {
    599  1.11    ad 		i8254_delay(10);
    600   1.2    ad 	}
    601   1.9    ad 	if ((ci->ci_flags & CPUF_RUNNING) == 0) {
    602   1.2    ad 		aprint_error("%s: failed to start\n", ci->ci_dev->dv_xname);
    603   1.2    ad #if defined(MPDEBUG) && defined(DDB)
    604   1.2    ad 		printf("dropping into debugger; continue from here to resume boot\n");
    605   1.2    ad 		Debugger();
    606   1.2    ad #endif
    607   1.2    ad 	}
    608   1.2    ad }
    609   1.2    ad 
    610   1.2    ad /*
    611   1.2    ad  * The CPU ends up here when its ready to run
    612   1.2    ad  * This is called from code in mptramp.s; at this point, we are running
    613   1.2    ad  * in the idle pcb/idle stack of the new CPU.  When this function returns,
    614   1.2    ad  * this processor will enter the idle loop and start looking for work.
    615   1.2    ad  */
    616   1.2    ad void
    617   1.2    ad cpu_hatch(void *v)
    618   1.2    ad {
    619   1.2    ad 	struct cpu_info *ci = (struct cpu_info *)v;
    620   1.6    ad 	int s, i;
    621   1.2    ad 
    622   1.2    ad #ifdef __x86_64__
    623   1.2    ad 	cpu_init_msrs(ci);
    624   1.2    ad #endif
    625   1.2    ad 	cpu_probe_features(ci);
    626   1.2    ad 	cpu_feature &= ci->ci_feature_flags;
    627   1.2    ad 	cpu_feature2 &= ci->ci_feature2_flags;
    628   1.2    ad 
    629   1.8    ad 	KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0);
    630   1.9    ad 	atomic_or_32(&ci->ci_flags, CPUF_PRESENT);
    631   1.6    ad 	while ((ci->ci_flags & CPUF_GO) == 0) {
    632   1.6    ad 		/* Don't use delay, boot CPU may be patching the text. */
    633   1.6    ad 		for (i = 10000; i != 0; i--)
    634   1.6    ad 			x86_pause();
    635   1.6    ad 	}
    636   1.5    ad 
    637   1.5    ad 	/* Beacuse the text may have been patched in x86_patch(). */
    638   1.5    ad 	wbinvd();
    639   1.5    ad 	x86_flush();
    640   1.5    ad 
    641   1.8    ad 	KASSERT((ci->ci_flags & CPUF_RUNNING) == 0);
    642   1.2    ad 
    643   1.2    ad 	lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0);
    644   1.2    ad 	cpu_init_idt();
    645   1.8    ad 	gdt_init_cpu(ci);
    646   1.8    ad 	lapic_enable();
    647   1.2    ad 	lapic_set_lvt();
    648   1.8    ad 	lapic_initclocks();
    649   1.2    ad 
    650   1.2    ad #ifdef i386
    651   1.2    ad 	npxinit(ci);
    652   1.2    ad #else
    653   1.2    ad 	fpuinit(ci);
    654   1.4  yamt #endif
    655   1.2    ad 	lldt(GSYSSEL(GLDT_SEL, SEL_KPL));
    656   1.2    ad 
    657   1.2    ad 	cpu_init(ci);
    658   1.7    ad 	cpu_get_tsc_freq(ci);
    659   1.2    ad 
    660   1.2    ad 	s = splhigh();
    661   1.2    ad #ifdef i386
    662   1.2    ad 	lapic_tpr = 0;
    663   1.2    ad #else
    664   1.2    ad 	lcr8(0);
    665   1.2    ad #endif
    666   1.3    ad 	x86_enable_intr();
    667   1.2    ad 	splx(s);
    668   1.6    ad 	x86_errata();
    669   1.2    ad 
    670   1.2    ad 	aprint_debug("%s: CPU %ld running\n", ci->ci_dev->dv_xname,
    671   1.2    ad 	    (long)ci->ci_cpuid);
    672   1.2    ad }
    673   1.2    ad 
    674   1.2    ad #if defined(DDB)
    675   1.2    ad 
    676   1.2    ad #include <ddb/db_output.h>
    677   1.2    ad #include <machine/db_machdep.h>
    678   1.2    ad 
    679   1.2    ad /*
    680   1.2    ad  * Dump CPU information from ddb.
    681   1.2    ad  */
    682   1.2    ad void
    683   1.2    ad cpu_debug_dump(void)
    684   1.2    ad {
    685   1.2    ad 	struct cpu_info *ci;
    686   1.2    ad 	CPU_INFO_ITERATOR cii;
    687   1.2    ad 
    688   1.2    ad 	db_printf("addr		dev	id	flags	ipis	curproc		fpcurproc\n");
    689   1.2    ad 	for (CPU_INFO_FOREACH(cii, ci)) {
    690   1.2    ad 		db_printf("%p	%s	%ld	%x	%x	%10p	%10p\n",
    691   1.2    ad 		    ci,
    692   1.2    ad 		    ci->ci_dev == NULL ? "BOOT" : ci->ci_dev->dv_xname,
    693   1.2    ad 		    (long)ci->ci_cpuid,
    694   1.2    ad 		    ci->ci_flags, ci->ci_ipis,
    695   1.2    ad 		    ci->ci_curlwp,
    696   1.2    ad 		    ci->ci_fpcurlwp);
    697   1.2    ad 	}
    698   1.2    ad }
    699   1.2    ad #endif
    700   1.2    ad 
    701   1.2    ad static void
    702   1.2    ad cpu_copy_trampoline()
    703   1.2    ad {
    704   1.2    ad 	/*
    705   1.2    ad 	 * Copy boot code.
    706   1.2    ad 	 */
    707   1.2    ad 	extern u_char cpu_spinup_trampoline[];
    708   1.2    ad 	extern u_char cpu_spinup_trampoline_end[];
    709   1.2    ad 	pmap_kenter_pa((vaddr_t)MP_TRAMPOLINE,	/* virtual */
    710   1.2    ad 	    (paddr_t)MP_TRAMPOLINE,	/* physical */
    711   1.2    ad 	    VM_PROT_ALL);		/* protection */
    712   1.2    ad 	pmap_update(pmap_kernel());
    713   1.2    ad 	memcpy((void *)MP_TRAMPOLINE,
    714   1.2    ad 	    cpu_spinup_trampoline,
    715   1.2    ad 	    cpu_spinup_trampoline_end-cpu_spinup_trampoline);
    716   1.2    ad }
    717   1.2    ad 
    718   1.2    ad #endif
    719   1.2    ad 
    720   1.2    ad #ifdef i386
    721   1.2    ad static void
    722   1.2    ad cpu_init_tss(struct i386tss *tss, void *stack, void *func)
    723   1.2    ad {
    724   1.2    ad 	memset(tss, 0, sizeof *tss);
    725   1.2    ad 	tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16);
    726   1.2    ad 	tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
    727   1.2    ad 	tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL);
    728   1.2    ad 	tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL);
    729   1.2    ad 	tss->tss_gs = tss->__tss_es = tss->__tss_ds =
    730   1.2    ad 	    tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL);
    731   1.2    ad 	tss->tss_cr3 = pmap_kernel()->pm_pdirpa;
    732   1.2    ad 	tss->tss_esp = (int)((char *)stack + USPACE - 16);
    733   1.2    ad 	tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
    734   1.2    ad 	tss->__tss_eflags = PSL_MBO | PSL_NT;	/* XXX not needed? */
    735   1.2    ad 	tss->__tss_eip = (int)func;
    736   1.2    ad }
    737   1.2    ad 
    738   1.2    ad /* XXX */
    739   1.2    ad #define IDTVEC(name)	__CONCAT(X, name)
    740   1.2    ad typedef void (vector)(void);
    741   1.2    ad extern vector IDTVEC(tss_trap08);
    742   1.2    ad #ifdef DDB
    743   1.2    ad extern vector Xintrddbipi;
    744   1.2    ad extern int ddb_vec;
    745   1.2    ad #endif
    746   1.2    ad 
    747   1.2    ad static void
    748   1.2    ad cpu_set_tss_gates(struct cpu_info *ci)
    749   1.2    ad {
    750   1.2    ad 	struct segment_descriptor sd;
    751   1.2    ad 
    752   1.2    ad 	ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
    753   1.2    ad 	    UVM_KMF_WIRED);
    754   1.2    ad 	cpu_init_tss(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack,
    755   1.2    ad 	    IDTVEC(tss_trap08));
    756   1.2    ad 	setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1,
    757   1.2    ad 	    SDT_SYS386TSS, SEL_KPL, 0, 0);
    758   1.2    ad 	ci->ci_gdt[GTRAPTSS_SEL].sd = sd;
    759   1.2    ad 	setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
    760   1.2    ad 	    GSEL(GTRAPTSS_SEL, SEL_KPL));
    761   1.2    ad 
    762   1.2    ad #if defined(DDB) && defined(MULTIPROCESSOR)
    763   1.2    ad 	/*
    764   1.2    ad 	 * Set up separate handler for the DDB IPI, so that it doesn't
    765   1.2    ad 	 * stomp on a possibly corrupted stack.
    766   1.2    ad 	 *
    767   1.2    ad 	 * XXX overwriting the gate set in db_machine_init.
    768   1.2    ad 	 * Should rearrange the code so that it's set only once.
    769   1.2    ad 	 */
    770   1.2    ad 	ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
    771   1.2    ad 	    UVM_KMF_WIRED);
    772   1.2    ad 	cpu_init_tss(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack,
    773   1.2    ad 	    Xintrddbipi);
    774   1.2    ad 
    775   1.2    ad 	setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1,
    776   1.2    ad 	    SDT_SYS386TSS, SEL_KPL, 0, 0);
    777   1.2    ad 	ci->ci_gdt[GIPITSS_SEL].sd = sd;
    778   1.2    ad 
    779   1.2    ad 	setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
    780   1.2    ad 	    GSEL(GIPITSS_SEL, SEL_KPL));
    781   1.2    ad #endif
    782   1.2    ad }
    783   1.2    ad #else
    784   1.2    ad static void
    785   1.2    ad cpu_set_tss_gates(struct cpu_info *ci)
    786   1.2    ad {
    787   1.2    ad 
    788   1.2    ad }
    789   1.2    ad #endif	/* i386 */
    790   1.2    ad 
    791   1.2    ad 
    792   1.2    ad int
    793   1.2    ad mp_cpu_start(struct cpu_info *ci)
    794   1.2    ad {
    795   1.2    ad #if NLAPIC > 0
    796   1.2    ad 	int error;
    797   1.2    ad #endif
    798   1.2    ad 	unsigned short dwordptr[2];
    799   1.2    ad 
    800   1.2    ad 	/*
    801   1.2    ad 	 * "The BSP must initialize CMOS shutdown code to 0Ah ..."
    802   1.2    ad 	 */
    803   1.2    ad 
    804   1.2    ad 	outb(IO_RTC, NVRAM_RESET);
    805   1.2    ad 	outb(IO_RTC+1, NVRAM_RESET_JUMP);
    806   1.2    ad 
    807   1.2    ad 	/*
    808   1.2    ad 	 * "and the warm reset vector (DWORD based at 40:67) to point
    809   1.2    ad 	 * to the AP startup code ..."
    810   1.2    ad 	 */
    811   1.2    ad 
    812   1.2    ad 	dwordptr[0] = 0;
    813   1.2    ad 	dwordptr[1] = MP_TRAMPOLINE >> 4;
    814   1.2    ad 
    815   1.2    ad 	pmap_kenter_pa(0, 0, VM_PROT_READ|VM_PROT_WRITE);
    816   1.2    ad 	pmap_update(pmap_kernel());
    817   1.2    ad 	memcpy((uint8_t *)0x467, dwordptr, 4);
    818   1.2    ad 	pmap_kremove(0, PAGE_SIZE);
    819   1.2    ad 	pmap_update(pmap_kernel());
    820   1.2    ad 
    821   1.2    ad #if NLAPIC > 0
    822   1.2    ad 	/*
    823   1.2    ad 	 * ... prior to executing the following sequence:"
    824   1.2    ad 	 */
    825   1.2    ad 
    826   1.2    ad 	if (ci->ci_flags & CPUF_AP) {
    827   1.2    ad 		if ((error = x86_ipi_init(ci->ci_apicid)) != 0)
    828   1.2    ad 			return error;
    829   1.2    ad 
    830  1.11    ad 		i8254_delay(10000);
    831   1.2    ad 
    832   1.2    ad 		if (cpu_feature & CPUID_APIC) {
    833   1.2    ad 
    834   1.2    ad 			if ((error = x86_ipi(MP_TRAMPOLINE/PAGE_SIZE,
    835   1.2    ad 					     ci->ci_apicid,
    836   1.2    ad 					     LAPIC_DLMODE_STARTUP)) != 0)
    837   1.2    ad 				return error;
    838  1.11    ad 			i8254_delay(200);
    839   1.2    ad 
    840   1.2    ad 			if ((error = x86_ipi(MP_TRAMPOLINE/PAGE_SIZE,
    841   1.2    ad 					     ci->ci_apicid,
    842   1.2    ad 					     LAPIC_DLMODE_STARTUP)) != 0)
    843   1.2    ad 				return error;
    844  1.11    ad 			i8254_delay(200);
    845   1.2    ad 		}
    846   1.2    ad 	}
    847   1.2    ad #endif
    848   1.2    ad 	return 0;
    849   1.2    ad }
    850   1.2    ad 
    851   1.2    ad void
    852   1.2    ad mp_cpu_start_cleanup(struct cpu_info *ci)
    853   1.2    ad {
    854   1.2    ad 	/*
    855   1.2    ad 	 * Ensure the NVRAM reset byte contains something vaguely sane.
    856   1.2    ad 	 */
    857   1.2    ad 
    858   1.2    ad 	outb(IO_RTC, NVRAM_RESET);
    859   1.2    ad 	outb(IO_RTC+1, NVRAM_RESET_RST);
    860   1.2    ad }
    861   1.2    ad 
    862   1.2    ad #ifdef __x86_64__
    863   1.2    ad typedef void (vector)(void);
    864   1.2    ad extern vector Xsyscall, Xsyscall32;
    865   1.2    ad 
    866   1.2    ad void
    867   1.2    ad cpu_init_msrs(struct cpu_info *ci)
    868   1.2    ad {
    869   1.2    ad 	wrmsr(MSR_STAR,
    870   1.2    ad 	    ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
    871   1.2    ad 	    ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48));
    872   1.2    ad 	wrmsr(MSR_LSTAR, (uint64_t)Xsyscall);
    873   1.2    ad 	wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32);
    874   1.2    ad 	wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C);
    875   1.2    ad 
    876   1.2    ad 	wrmsr(MSR_FSBASE, 0);
    877   1.2    ad 	wrmsr(MSR_GSBASE, (u_int64_t)ci);
    878   1.2    ad 	wrmsr(MSR_KERNELGSBASE, 0);
    879   1.2    ad 
    880   1.2    ad 	if (cpu_feature & CPUID_NOX)
    881   1.2    ad 		wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE);
    882   1.2    ad }
    883   1.2    ad #endif	/* __x86_64__ */
    884   1.7    ad 
    885   1.7    ad void
    886   1.7    ad cpu_get_tsc_freq(struct cpu_info *ci)
    887   1.7    ad {
    888   1.7    ad 	uint64_t last_tsc;
    889   1.7    ad 	u_int junk[4];
    890   1.7    ad 
    891   1.7    ad 	if (ci->ci_feature_flags & CPUID_TSC) {
    892   1.7    ad 		/* Serialize. */
    893   1.7    ad 		x86_cpuid(0, junk);
    894   1.7    ad 		last_tsc = rdtsc();
    895   1.7    ad 		i8254_delay(100000);
    896   1.7    ad 		ci->ci_tsc_freq = (rdtsc() - last_tsc) * 10;
    897   1.7    ad 	}
    898   1.7    ad }
    899