cpu.c revision 1.46 1 1.46 ad /* $NetBSD: cpu.c,v 1.46 2008/05/12 11:58:10 ad Exp $ */
2 1.2 ad
3 1.2 ad /*-
4 1.38 ad * Copyright (c) 2000, 2006, 2007, 2008 The NetBSD Foundation, Inc.
5 1.2 ad * All rights reserved.
6 1.2 ad *
7 1.2 ad * This code is derived from software contributed to The NetBSD Foundation
8 1.11 ad * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran.
9 1.2 ad *
10 1.2 ad * Redistribution and use in source and binary forms, with or without
11 1.2 ad * modification, are permitted provided that the following conditions
12 1.2 ad * are met:
13 1.2 ad * 1. Redistributions of source code must retain the above copyright
14 1.2 ad * notice, this list of conditions and the following disclaimer.
15 1.2 ad * 2. Redistributions in binary form must reproduce the above copyright
16 1.2 ad * notice, this list of conditions and the following disclaimer in the
17 1.2 ad * documentation and/or other materials provided with the distribution.
18 1.2 ad *
19 1.2 ad * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.2 ad * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.2 ad * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.2 ad * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.2 ad * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.2 ad * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.2 ad * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.2 ad * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.2 ad * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.2 ad * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.2 ad * POSSIBILITY OF SUCH DAMAGE.
30 1.2 ad */
31 1.2 ad
32 1.2 ad /*
33 1.2 ad * Copyright (c) 1999 Stefan Grefen
34 1.2 ad *
35 1.2 ad * Redistribution and use in source and binary forms, with or without
36 1.2 ad * modification, are permitted provided that the following conditions
37 1.2 ad * are met:
38 1.2 ad * 1. Redistributions of source code must retain the above copyright
39 1.2 ad * notice, this list of conditions and the following disclaimer.
40 1.2 ad * 2. Redistributions in binary form must reproduce the above copyright
41 1.2 ad * notice, this list of conditions and the following disclaimer in the
42 1.2 ad * documentation and/or other materials provided with the distribution.
43 1.2 ad * 3. All advertising materials mentioning features or use of this software
44 1.2 ad * must display the following acknowledgement:
45 1.2 ad * This product includes software developed by the NetBSD
46 1.2 ad * Foundation, Inc. and its contributors.
47 1.2 ad * 4. Neither the name of The NetBSD Foundation nor the names of its
48 1.2 ad * contributors may be used to endorse or promote products derived
49 1.2 ad * from this software without specific prior written permission.
50 1.2 ad *
51 1.2 ad * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
52 1.2 ad * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
53 1.2 ad * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
54 1.2 ad * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
55 1.2 ad * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
56 1.2 ad * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
57 1.2 ad * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
58 1.2 ad * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
59 1.2 ad * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
60 1.2 ad * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
61 1.2 ad * SUCH DAMAGE.
62 1.2 ad */
63 1.2 ad
64 1.2 ad #include <sys/cdefs.h>
65 1.46 ad __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.46 2008/05/12 11:58:10 ad Exp $");
66 1.2 ad
67 1.2 ad #include "opt_ddb.h"
68 1.2 ad #include "opt_mpbios.h" /* for MPDEBUG */
69 1.2 ad #include "opt_mtrr.h"
70 1.2 ad
71 1.2 ad #include "lapic.h"
72 1.2 ad #include "ioapic.h"
73 1.2 ad
74 1.2 ad #include <sys/param.h>
75 1.2 ad #include <sys/proc.h>
76 1.2 ad #include <sys/user.h>
77 1.2 ad #include <sys/systm.h>
78 1.2 ad #include <sys/device.h>
79 1.2 ad #include <sys/malloc.h>
80 1.9 ad #include <sys/cpu.h>
81 1.9 ad #include <sys/atomic.h>
82 1.35 ad #include <sys/reboot.h>
83 1.2 ad
84 1.2 ad #include <uvm/uvm_extern.h>
85 1.2 ad
86 1.2 ad #include <machine/cpufunc.h>
87 1.2 ad #include <machine/cpuvar.h>
88 1.2 ad #include <machine/pmap.h>
89 1.2 ad #include <machine/vmparam.h>
90 1.2 ad #include <machine/mpbiosvar.h>
91 1.2 ad #include <machine/pcb.h>
92 1.2 ad #include <machine/specialreg.h>
93 1.2 ad #include <machine/segments.h>
94 1.2 ad #include <machine/gdt.h>
95 1.2 ad #include <machine/mtrr.h>
96 1.2 ad #include <machine/pio.h>
97 1.38 ad #include <machine/cpu_counter.h>
98 1.2 ad
99 1.2 ad #ifdef i386
100 1.2 ad #include <machine/tlog.h>
101 1.2 ad #endif
102 1.2 ad
103 1.2 ad #include <machine/apicvar.h>
104 1.2 ad #include <machine/i82489reg.h>
105 1.2 ad #include <machine/i82489var.h>
106 1.2 ad
107 1.2 ad #include <dev/ic/mc146818reg.h>
108 1.2 ad #include <i386/isa/nvram.h>
109 1.2 ad #include <dev/isa/isareg.h>
110 1.2 ad
111 1.38 ad #include "tsc.h"
112 1.38 ad
113 1.23 cube int cpu_match(device_t, cfdata_t, void *);
114 1.23 cube void cpu_attach(device_t, device_t, void *);
115 1.2 ad
116 1.22 dyoung static bool cpu_suspend(device_t PMF_FN_PROTO);
117 1.22 dyoung static bool cpu_resume(device_t PMF_FN_PROTO);
118 1.12 jmcneill
119 1.2 ad struct cpu_softc {
120 1.23 cube device_t sc_dev; /* device tree glue */
121 1.2 ad struct cpu_info *sc_info; /* pointer to CPU info */
122 1.20 jmcneill bool sc_wasonline;
123 1.2 ad };
124 1.2 ad
125 1.14 joerg int mp_cpu_start(struct cpu_info *, paddr_t);
126 1.2 ad void mp_cpu_start_cleanup(struct cpu_info *);
127 1.2 ad const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL,
128 1.2 ad mp_cpu_start_cleanup };
129 1.2 ad
130 1.2 ad
131 1.23 cube CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc),
132 1.2 ad cpu_match, cpu_attach, NULL, NULL);
133 1.2 ad
134 1.2 ad /*
135 1.2 ad * Statically-allocated CPU info for the primary CPU (or the only
136 1.2 ad * CPU, on uniprocessors). The CPU info list is initialized to
137 1.2 ad * point at it.
138 1.2 ad */
139 1.2 ad #ifdef TRAPLOG
140 1.2 ad struct tlog tlog_primary;
141 1.2 ad #endif
142 1.21 ad struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = {
143 1.2 ad .ci_dev = 0,
144 1.2 ad .ci_self = &cpu_info_primary,
145 1.2 ad .ci_idepth = -1,
146 1.2 ad .ci_curlwp = &lwp0,
147 1.43 ad .ci_curldt = -1,
148 1.2 ad #ifdef TRAPLOG
149 1.2 ad .ci_tlog_base = &tlog_primary,
150 1.2 ad #endif /* !TRAPLOG */
151 1.2 ad };
152 1.2 ad
153 1.2 ad struct cpu_info *cpu_info_list = &cpu_info_primary;
154 1.2 ad
155 1.12 jmcneill static void cpu_set_tss_gates(struct cpu_info *);
156 1.2 ad
157 1.2 ad #ifdef i386
158 1.15 yamt static void tss_init(struct i386tss *, void *, void *);
159 1.2 ad #endif
160 1.2 ad
161 1.12 jmcneill static void cpu_init_idle_lwp(struct cpu_info *);
162 1.12 jmcneill
163 1.2 ad uint32_t cpus_attached = 0;
164 1.9 ad uint32_t cpus_running = 0;
165 1.2 ad
166 1.2 ad extern char x86_64_doubleflt_stack[];
167 1.2 ad
168 1.12 jmcneill bool x86_mp_online;
169 1.12 jmcneill paddr_t mp_trampoline_paddr = MP_TRAMPOLINE;
170 1.12 jmcneill
171 1.14 joerg static vaddr_t cmos_data_mapping;
172 1.14 joerg
173 1.2 ad /*
174 1.2 ad * Array of CPU info structures. Must be statically-allocated because
175 1.2 ad * curproc, etc. are used early.
176 1.2 ad */
177 1.45 ad struct cpu_info *cpu_info[X86_MAXPROCS];
178 1.45 ad struct cpu_info *cpu_starting;
179 1.2 ad
180 1.2 ad void cpu_hatch(void *);
181 1.2 ad static void cpu_boot_secondary(struct cpu_info *ci);
182 1.2 ad static void cpu_start_secondary(struct cpu_info *ci);
183 1.2 ad static void cpu_copy_trampoline(void);
184 1.2 ad
185 1.2 ad /*
186 1.2 ad * Runs once per boot once multiprocessor goo has been detected and
187 1.2 ad * the local APIC on the boot processor has been mapped.
188 1.2 ad *
189 1.2 ad * Called from lapic_boot_init() (from mpbios_scan()).
190 1.2 ad */
191 1.2 ad void
192 1.9 ad cpu_init_first(void)
193 1.2 ad {
194 1.2 ad
195 1.45 ad cpu_info_primary.ci_cpuid = lapic_cpu_number();
196 1.2 ad cpu_copy_trampoline();
197 1.14 joerg
198 1.14 joerg cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY);
199 1.14 joerg if (cmos_data_mapping == 0)
200 1.14 joerg panic("No KVA for page 0");
201 1.14 joerg pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE);
202 1.14 joerg pmap_update(pmap_kernel());
203 1.2 ad }
204 1.2 ad
205 1.2 ad int
206 1.23 cube cpu_match(device_t parent, cfdata_t match, void *aux)
207 1.2 ad {
208 1.2 ad
209 1.2 ad return 1;
210 1.2 ad }
211 1.2 ad
212 1.2 ad static void
213 1.2 ad cpu_vm_init(struct cpu_info *ci)
214 1.2 ad {
215 1.2 ad int ncolors = 2, i;
216 1.2 ad
217 1.2 ad for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) {
218 1.2 ad struct x86_cache_info *cai;
219 1.2 ad int tcolors;
220 1.2 ad
221 1.2 ad cai = &ci->ci_cinfo[i];
222 1.2 ad
223 1.2 ad tcolors = atop(cai->cai_totalsize);
224 1.2 ad switch(cai->cai_associativity) {
225 1.2 ad case 0xff:
226 1.2 ad tcolors = 1; /* fully associative */
227 1.2 ad break;
228 1.2 ad case 0:
229 1.2 ad case 1:
230 1.2 ad break;
231 1.2 ad default:
232 1.2 ad tcolors /= cai->cai_associativity;
233 1.2 ad }
234 1.2 ad ncolors = max(ncolors, tcolors);
235 1.32 tls /*
236 1.32 tls * If the desired number of colors is not a power of
237 1.32 tls * two, it won't be good. Find the greatest power of
238 1.32 tls * two which is an even divisor of the number of colors,
239 1.32 tls * to preserve even coloring of pages.
240 1.32 tls */
241 1.32 tls if (ncolors & (ncolors - 1) ) {
242 1.32 tls int try, picked = 1;
243 1.32 tls for (try = 1; try < ncolors; try *= 2) {
244 1.32 tls if (ncolors % try == 0) picked = try;
245 1.32 tls }
246 1.32 tls if (picked == 1) {
247 1.32 tls panic("desired number of cache colors %d is "
248 1.32 tls " > 1, but not even!", ncolors);
249 1.32 tls }
250 1.32 tls ncolors = picked;
251 1.32 tls }
252 1.2 ad }
253 1.2 ad
254 1.2 ad /*
255 1.2 ad * Knowing the size of the largest cache on this CPU, re-color
256 1.2 ad * our pages.
257 1.2 ad */
258 1.2 ad if (ncolors <= uvmexp.ncolors)
259 1.2 ad return;
260 1.27 cegger aprint_verbose_dev(ci->ci_dev, "%d page colors\n", ncolors);
261 1.2 ad uvm_page_recolor(ncolors);
262 1.2 ad }
263 1.2 ad
264 1.2 ad
265 1.2 ad void
266 1.23 cube cpu_attach(device_t parent, device_t self, void *aux)
267 1.2 ad {
268 1.23 cube struct cpu_softc *sc = device_private(self);
269 1.2 ad struct cpu_attach_args *caa = aux;
270 1.2 ad struct cpu_info *ci;
271 1.21 ad uintptr_t ptr;
272 1.2 ad int cpunum = caa->cpu_number;
273 1.2 ad
274 1.23 cube sc->sc_dev = self;
275 1.23 cube
276 1.45 ad /* Make sure DELAY() is initialized. */
277 1.45 ad DELAY(1);
278 1.45 ad
279 1.2 ad /*
280 1.2 ad * If we're an Application Processor, allocate a cpu_info
281 1.2 ad * structure, otherwise use the primary's.
282 1.2 ad */
283 1.2 ad if (caa->cpu_role == CPU_ROLE_AP) {
284 1.36 ad if ((boothowto & RB_MD1) != 0) {
285 1.35 ad aprint_error(": multiprocessor boot disabled\n");
286 1.35 ad return;
287 1.35 ad }
288 1.2 ad aprint_naive(": Application Processor\n");
289 1.21 ad ptr = (uintptr_t)malloc(sizeof(*ci) + CACHE_LINE_SIZE - 1,
290 1.21 ad M_DEVBUF, M_WAITOK);
291 1.21 ad ci = (struct cpu_info *)((ptr + CACHE_LINE_SIZE - 1) &
292 1.21 ad ~(CACHE_LINE_SIZE - 1));
293 1.2 ad memset(ci, 0, sizeof(*ci));
294 1.43 ad ci->ci_curldt = -1;
295 1.2 ad #ifdef TRAPLOG
296 1.2 ad ci->ci_tlog_base = malloc(sizeof(struct tlog),
297 1.2 ad M_DEVBUF, M_WAITOK);
298 1.2 ad #endif
299 1.2 ad } else {
300 1.2 ad aprint_naive(": %s Processor\n",
301 1.2 ad caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot");
302 1.2 ad ci = &cpu_info_primary;
303 1.2 ad if (cpunum != lapic_cpu_number()) {
304 1.39 ad uint32_t reg;
305 1.39 ad aprint_verbose("\n");
306 1.39 ad aprint_verbose("%s: running CPU is at apic %d"
307 1.2 ad " instead of at expected %d",
308 1.23 cube device_xname(sc->sc_dev), lapic_cpu_number(),
309 1.23 cube cpunum);
310 1.39 ad reg = i82489_readreg(LAPIC_ID);
311 1.39 ad i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) |
312 1.39 ad (cpunum << LAPIC_ID_SHIFT));
313 1.2 ad }
314 1.2 ad }
315 1.2 ad
316 1.2 ad ci->ci_self = ci;
317 1.2 ad sc->sc_info = ci;
318 1.2 ad
319 1.2 ad ci->ci_dev = self;
320 1.42 ad ci->ci_cpuid = caa->cpu_number;
321 1.2 ad ci->ci_func = caa->cpu_func;
322 1.2 ad
323 1.2 ad if (caa->cpu_role == CPU_ROLE_AP) {
324 1.2 ad int error;
325 1.2 ad
326 1.2 ad error = mi_cpu_attach(ci);
327 1.2 ad if (error != 0) {
328 1.2 ad aprint_normal("\n");
329 1.30 cegger aprint_error_dev(sc->sc_dev,
330 1.30 cegger "mi_cpu_attach failed with %d\n", error);
331 1.2 ad return;
332 1.2 ad }
333 1.15 yamt cpu_init_tss(ci);
334 1.2 ad } else {
335 1.2 ad KASSERT(ci->ci_data.cpu_idlelwp != NULL);
336 1.2 ad }
337 1.2 ad
338 1.42 ad ci->ci_cpumask = (1 << cpu_index(ci));
339 1.45 ad cpu_info[cpu_index(ci)] = ci;
340 1.2 ad pmap_reference(pmap_kernel());
341 1.2 ad ci->ci_pmap = pmap_kernel();
342 1.2 ad ci->ci_tlbstate = TLBSTATE_STALE;
343 1.2 ad
344 1.2 ad /* further PCB init done later. */
345 1.2 ad
346 1.2 ad switch (caa->cpu_role) {
347 1.2 ad case CPU_ROLE_SP:
348 1.9 ad atomic_or_32(&ci->ci_flags,
349 1.9 ad CPUF_PRESENT | CPUF_SP | CPUF_PRIMARY);
350 1.2 ad cpu_intr_init(ci);
351 1.40 ad cpu_get_tsc_freq(ci);
352 1.40 ad cpu_identify(ci);
353 1.2 ad cpu_init(ci);
354 1.2 ad cpu_set_tss_gates(ci);
355 1.2 ad pmap_cpu_init_late(ci);
356 1.6 ad x86_errata();
357 1.37 joerg x86_cpu_idle_init();
358 1.2 ad break;
359 1.2 ad
360 1.2 ad case CPU_ROLE_BP:
361 1.9 ad atomic_or_32(&ci->ci_flags,
362 1.9 ad CPUF_PRESENT | CPUF_BSP | CPUF_PRIMARY);
363 1.2 ad cpu_intr_init(ci);
364 1.40 ad cpu_get_tsc_freq(ci);
365 1.40 ad cpu_identify(ci);
366 1.2 ad cpu_init(ci);
367 1.2 ad cpu_set_tss_gates(ci);
368 1.2 ad pmap_cpu_init_late(ci);
369 1.2 ad /*
370 1.2 ad * Enable local apic
371 1.2 ad */
372 1.2 ad lapic_enable();
373 1.19 joerg lapic_set_lvt();
374 1.2 ad lapic_calibrate_timer(ci);
375 1.6 ad x86_errata();
376 1.37 joerg x86_cpu_idle_init();
377 1.2 ad break;
378 1.2 ad
379 1.2 ad case CPU_ROLE_AP:
380 1.2 ad /*
381 1.2 ad * report on an AP
382 1.2 ad */
383 1.2 ad cpu_intr_init(ci);
384 1.2 ad gdt_alloc_cpu(ci);
385 1.2 ad cpu_set_tss_gates(ci);
386 1.2 ad pmap_cpu_init_early(ci);
387 1.2 ad pmap_cpu_init_late(ci);
388 1.2 ad cpu_start_secondary(ci);
389 1.2 ad if (ci->ci_flags & CPUF_PRESENT) {
390 1.40 ad cpu_identify(ci);
391 1.2 ad ci->ci_next = cpu_info_list->ci_next;
392 1.2 ad cpu_info_list->ci_next = ci;
393 1.2 ad }
394 1.2 ad break;
395 1.2 ad
396 1.2 ad default:
397 1.28 cegger aprint_normal("\n");
398 1.2 ad panic("unknown processor type??\n");
399 1.2 ad }
400 1.2 ad cpu_vm_init(ci);
401 1.2 ad
402 1.2 ad cpus_attached |= ci->ci_cpumask;
403 1.2 ad
404 1.12 jmcneill if (!pmf_device_register(self, cpu_suspend, cpu_resume))
405 1.12 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
406 1.12 jmcneill
407 1.2 ad if (mp_verbose) {
408 1.2 ad struct lwp *l = ci->ci_data.cpu_idlelwp;
409 1.2 ad
410 1.28 cegger aprint_verbose_dev(sc->sc_dev,
411 1.28 cegger "idle lwp at %p, idle sp at %p\n",
412 1.28 cegger l,
413 1.2 ad #ifdef i386
414 1.2 ad (void *)l->l_addr->u_pcb.pcb_esp
415 1.2 ad #else
416 1.2 ad (void *)l->l_addr->u_pcb.pcb_rsp
417 1.2 ad #endif
418 1.2 ad );
419 1.2 ad }
420 1.2 ad }
421 1.2 ad
422 1.2 ad /*
423 1.2 ad * Initialize the processor appropriately.
424 1.2 ad */
425 1.2 ad
426 1.2 ad void
427 1.9 ad cpu_init(struct cpu_info *ci)
428 1.2 ad {
429 1.2 ad
430 1.2 ad lcr0(rcr0() | CR0_WP);
431 1.2 ad
432 1.2 ad /*
433 1.2 ad * On a P6 or above, enable global TLB caching if the
434 1.2 ad * hardware supports it.
435 1.2 ad */
436 1.2 ad if (cpu_feature & CPUID_PGE)
437 1.2 ad lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */
438 1.2 ad
439 1.2 ad /*
440 1.2 ad * If we have FXSAVE/FXRESTOR, use them.
441 1.2 ad */
442 1.2 ad if (cpu_feature & CPUID_FXSR) {
443 1.2 ad lcr4(rcr4() | CR4_OSFXSR);
444 1.2 ad
445 1.2 ad /*
446 1.2 ad * If we have SSE/SSE2, enable XMM exceptions.
447 1.2 ad */
448 1.2 ad if (cpu_feature & (CPUID_SSE|CPUID_SSE2))
449 1.2 ad lcr4(rcr4() | CR4_OSXMMEXCPT);
450 1.2 ad }
451 1.2 ad
452 1.2 ad #ifdef MTRR
453 1.2 ad /*
454 1.2 ad * On a P6 or above, initialize MTRR's if the hardware supports them.
455 1.2 ad */
456 1.2 ad if (cpu_feature & CPUID_MTRR) {
457 1.2 ad if ((ci->ci_flags & CPUF_AP) == 0)
458 1.2 ad i686_mtrr_init_first();
459 1.2 ad mtrr_init_cpu(ci);
460 1.2 ad }
461 1.2 ad
462 1.2 ad #ifdef i386
463 1.2 ad if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) {
464 1.2 ad /*
465 1.2 ad * Must be a K6-2 Step >= 7 or a K6-III.
466 1.2 ad */
467 1.2 ad if (CPUID2FAMILY(ci->ci_signature) == 5) {
468 1.2 ad if (CPUID2MODEL(ci->ci_signature) > 8 ||
469 1.2 ad (CPUID2MODEL(ci->ci_signature) == 8 &&
470 1.2 ad CPUID2STEPPING(ci->ci_signature) >= 7)) {
471 1.2 ad mtrr_funcs = &k6_mtrr_funcs;
472 1.2 ad k6_mtrr_init_first();
473 1.2 ad mtrr_init_cpu(ci);
474 1.2 ad }
475 1.2 ad }
476 1.2 ad }
477 1.2 ad #endif /* i386 */
478 1.2 ad #endif /* MTRR */
479 1.2 ad
480 1.9 ad atomic_or_32(&cpus_running, ci->ci_cpumask);
481 1.9 ad
482 1.38 ad if (ci != &cpu_info_primary) {
483 1.38 ad /* Synchronize TSC again, and check for drift. */
484 1.38 ad wbinvd();
485 1.38 ad atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
486 1.38 ad tsc_sync_ap(ci);
487 1.38 ad tsc_sync_ap(ci);
488 1.38 ad } else {
489 1.38 ad atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
490 1.38 ad }
491 1.2 ad }
492 1.2 ad
493 1.2 ad void
494 1.12 jmcneill cpu_boot_secondary_processors(void)
495 1.2 ad {
496 1.2 ad struct cpu_info *ci;
497 1.2 ad u_long i;
498 1.2 ad
499 1.5 ad /* Now that we know the number of CPUs, patch the text segment. */
500 1.5 ad x86_patch();
501 1.5 ad
502 1.2 ad for (i=0; i < X86_MAXPROCS; i++) {
503 1.2 ad ci = cpu_info[i];
504 1.2 ad if (ci == NULL)
505 1.2 ad continue;
506 1.2 ad if (ci->ci_data.cpu_idlelwp == NULL)
507 1.2 ad continue;
508 1.2 ad if ((ci->ci_flags & CPUF_PRESENT) == 0)
509 1.2 ad continue;
510 1.2 ad if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY))
511 1.2 ad continue;
512 1.2 ad cpu_boot_secondary(ci);
513 1.2 ad }
514 1.2 ad
515 1.2 ad x86_mp_online = true;
516 1.38 ad
517 1.38 ad /* Now that we know about the TSC, attach the timecounter. */
518 1.38 ad tsc_tc_init();
519 1.2 ad }
520 1.2 ad
521 1.2 ad static void
522 1.2 ad cpu_init_idle_lwp(struct cpu_info *ci)
523 1.2 ad {
524 1.2 ad struct lwp *l = ci->ci_data.cpu_idlelwp;
525 1.2 ad struct pcb *pcb = &l->l_addr->u_pcb;
526 1.2 ad
527 1.2 ad pcb->pcb_cr0 = rcr0();
528 1.2 ad }
529 1.2 ad
530 1.2 ad void
531 1.12 jmcneill cpu_init_idle_lwps(void)
532 1.2 ad {
533 1.2 ad struct cpu_info *ci;
534 1.2 ad u_long i;
535 1.2 ad
536 1.2 ad for (i = 0; i < X86_MAXPROCS; i++) {
537 1.2 ad ci = cpu_info[i];
538 1.2 ad if (ci == NULL)
539 1.2 ad continue;
540 1.2 ad if (ci->ci_data.cpu_idlelwp == NULL)
541 1.2 ad continue;
542 1.2 ad if ((ci->ci_flags & CPUF_PRESENT) == 0)
543 1.2 ad continue;
544 1.2 ad cpu_init_idle_lwp(ci);
545 1.2 ad }
546 1.2 ad }
547 1.2 ad
548 1.2 ad void
549 1.12 jmcneill cpu_start_secondary(struct cpu_info *ci)
550 1.2 ad {
551 1.38 ad extern paddr_t mp_pdirpa;
552 1.38 ad u_long psl;
553 1.2 ad int i;
554 1.2 ad
555 1.45 ad KASSERT(cpu_starting == NULL);
556 1.45 ad
557 1.45 ad cpu_starting = ci;
558 1.12 jmcneill mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr);
559 1.9 ad atomic_or_32(&ci->ci_flags, CPUF_AP);
560 1.2 ad ci->ci_curlwp = ci->ci_data.cpu_idlelwp;
561 1.45 ad if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) {
562 1.45 ad cpu_starting = NULL;
563 1.25 ad return;
564 1.45 ad }
565 1.2 ad
566 1.2 ad /*
567 1.2 ad * wait for it to become ready
568 1.2 ad */
569 1.26 cegger for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) {
570 1.24 ad #ifdef MPDEBUG
571 1.24 ad extern int cpu_trace[3];
572 1.24 ad static int otrace[3];
573 1.24 ad if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) {
574 1.26 cegger aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n",
575 1.26 cegger cpu_trace[0], cpu_trace[1], cpu_trace[2]);
576 1.24 ad memcpy(otrace, cpu_trace, sizeof(otrace));
577 1.24 ad }
578 1.24 ad #endif
579 1.11 ad i8254_delay(10);
580 1.2 ad }
581 1.38 ad
582 1.9 ad if ((ci->ci_flags & CPUF_PRESENT) == 0) {
583 1.26 cegger aprint_error_dev(ci->ci_dev, "failed to become ready\n");
584 1.2 ad #if defined(MPDEBUG) && defined(DDB)
585 1.2 ad printf("dropping into debugger; continue from here to resume boot\n");
586 1.2 ad Debugger();
587 1.2 ad #endif
588 1.38 ad } else {
589 1.38 ad /*
590 1.38 ad * Synchronize time stamp counters. Invalidate cache and do twice
591 1.38 ad * to try and minimize possible cache effects. Disable interrupts
592 1.38 ad * to try and rule out any external interference.
593 1.38 ad */
594 1.38 ad psl = x86_read_psl();
595 1.38 ad x86_disable_intr();
596 1.38 ad wbinvd();
597 1.38 ad tsc_sync_bp(ci);
598 1.38 ad tsc_sync_bp(ci);
599 1.38 ad x86_write_psl(psl);
600 1.2 ad }
601 1.2 ad
602 1.2 ad CPU_START_CLEANUP(ci);
603 1.45 ad cpu_starting = NULL;
604 1.2 ad }
605 1.2 ad
606 1.2 ad void
607 1.12 jmcneill cpu_boot_secondary(struct cpu_info *ci)
608 1.2 ad {
609 1.38 ad int64_t drift;
610 1.38 ad u_long psl;
611 1.2 ad int i;
612 1.2 ad
613 1.9 ad atomic_or_32(&ci->ci_flags, CPUF_GO);
614 1.26 cegger for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) {
615 1.11 ad i8254_delay(10);
616 1.2 ad }
617 1.9 ad if ((ci->ci_flags & CPUF_RUNNING) == 0) {
618 1.26 cegger aprint_error_dev(ci->ci_dev, "failed to start\n");
619 1.2 ad #if defined(MPDEBUG) && defined(DDB)
620 1.2 ad printf("dropping into debugger; continue from here to resume boot\n");
621 1.2 ad Debugger();
622 1.2 ad #endif
623 1.38 ad } else {
624 1.38 ad /* Synchronize TSC again, check for drift. */
625 1.38 ad drift = ci->ci_data.cpu_cc_skew;
626 1.38 ad psl = x86_read_psl();
627 1.38 ad x86_disable_intr();
628 1.38 ad wbinvd();
629 1.38 ad tsc_sync_bp(ci);
630 1.38 ad tsc_sync_bp(ci);
631 1.38 ad x86_write_psl(psl);
632 1.38 ad drift -= ci->ci_data.cpu_cc_skew;
633 1.38 ad aprint_debug_dev(ci->ci_dev, "TSC skew=%lld drift=%lld\n",
634 1.38 ad (long long)ci->ci_data.cpu_cc_skew, (long long)drift);
635 1.38 ad tsc_sync_drift(drift);
636 1.2 ad }
637 1.2 ad }
638 1.2 ad
639 1.2 ad /*
640 1.2 ad * The CPU ends up here when its ready to run
641 1.2 ad * This is called from code in mptramp.s; at this point, we are running
642 1.2 ad * in the idle pcb/idle stack of the new CPU. When this function returns,
643 1.2 ad * this processor will enter the idle loop and start looking for work.
644 1.2 ad */
645 1.2 ad void
646 1.2 ad cpu_hatch(void *v)
647 1.2 ad {
648 1.2 ad struct cpu_info *ci = (struct cpu_info *)v;
649 1.6 ad int s, i;
650 1.2 ad
651 1.2 ad #ifdef __x86_64__
652 1.12 jmcneill cpu_init_msrs(ci, true);
653 1.2 ad #endif
654 1.40 ad cpu_probe(ci);
655 1.46 ad
656 1.46 ad ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq;
657 1.46 ad /* cpu_get_tsc_freq(ci); */
658 1.38 ad
659 1.8 ad KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0);
660 1.38 ad
661 1.38 ad /*
662 1.38 ad * Synchronize time stamp counters. Invalidate cache and do twice
663 1.38 ad * to try and minimize possible cache effects. Note that interrupts
664 1.38 ad * are off at this point.
665 1.38 ad */
666 1.38 ad wbinvd();
667 1.9 ad atomic_or_32(&ci->ci_flags, CPUF_PRESENT);
668 1.38 ad tsc_sync_ap(ci);
669 1.38 ad tsc_sync_ap(ci);
670 1.38 ad
671 1.38 ad /*
672 1.38 ad * Wait to be brought online. Use 'monitor/mwait' if available,
673 1.38 ad * in order to make the TSC drift as much as possible. so that
674 1.38 ad * we can detect it later. If not available, try 'pause'.
675 1.38 ad * We'd like to use 'hlt', but we have interrupts off.
676 1.38 ad */
677 1.6 ad while ((ci->ci_flags & CPUF_GO) == 0) {
678 1.38 ad if ((ci->ci_feature2_flags & CPUID2_MONITOR) != 0) {
679 1.38 ad x86_monitor(&ci->ci_flags, 0, 0);
680 1.38 ad if ((ci->ci_flags & CPUF_GO) != 0) {
681 1.38 ad continue;
682 1.38 ad }
683 1.38 ad x86_mwait(0, 0);
684 1.38 ad } else {
685 1.38 ad for (i = 10000; i != 0; i--) {
686 1.38 ad x86_pause();
687 1.38 ad }
688 1.38 ad }
689 1.6 ad }
690 1.5 ad
691 1.26 cegger /* Because the text may have been patched in x86_patch(). */
692 1.5 ad wbinvd();
693 1.5 ad x86_flush();
694 1.5 ad
695 1.8 ad KASSERT((ci->ci_flags & CPUF_RUNNING) == 0);
696 1.2 ad
697 1.12 jmcneill lcr3(pmap_kernel()->pm_pdirpa);
698 1.12 jmcneill curlwp->l_addr->u_pcb.pcb_cr3 = pmap_kernel()->pm_pdirpa;
699 1.2 ad lcr0(ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_cr0);
700 1.2 ad cpu_init_idt();
701 1.8 ad gdt_init_cpu(ci);
702 1.8 ad lapic_enable();
703 1.2 ad lapic_set_lvt();
704 1.8 ad lapic_initclocks();
705 1.2 ad
706 1.2 ad #ifdef i386
707 1.2 ad npxinit(ci);
708 1.2 ad #else
709 1.2 ad fpuinit(ci);
710 1.4 yamt #endif
711 1.2 ad lldt(GSYSSEL(GLDT_SEL, SEL_KPL));
712 1.15 yamt ltr(ci->ci_tss_sel);
713 1.2 ad
714 1.2 ad cpu_init(ci);
715 1.7 ad cpu_get_tsc_freq(ci);
716 1.2 ad
717 1.2 ad s = splhigh();
718 1.2 ad #ifdef i386
719 1.2 ad lapic_tpr = 0;
720 1.2 ad #else
721 1.2 ad lcr8(0);
722 1.2 ad #endif
723 1.3 ad x86_enable_intr();
724 1.2 ad splx(s);
725 1.6 ad x86_errata();
726 1.2 ad
727 1.42 ad aprint_debug_dev(ci->ci_dev, "running\n");
728 1.2 ad }
729 1.2 ad
730 1.2 ad #if defined(DDB)
731 1.2 ad
732 1.2 ad #include <ddb/db_output.h>
733 1.2 ad #include <machine/db_machdep.h>
734 1.2 ad
735 1.2 ad /*
736 1.2 ad * Dump CPU information from ddb.
737 1.2 ad */
738 1.2 ad void
739 1.2 ad cpu_debug_dump(void)
740 1.2 ad {
741 1.2 ad struct cpu_info *ci;
742 1.2 ad CPU_INFO_ITERATOR cii;
743 1.2 ad
744 1.29 yamt db_printf("addr dev id flags ipis curlwp fpcurlwp\n");
745 1.2 ad for (CPU_INFO_FOREACH(cii, ci)) {
746 1.2 ad db_printf("%p %s %ld %x %x %10p %10p\n",
747 1.2 ad ci,
748 1.27 cegger ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev),
749 1.2 ad (long)ci->ci_cpuid,
750 1.2 ad ci->ci_flags, ci->ci_ipis,
751 1.2 ad ci->ci_curlwp,
752 1.2 ad ci->ci_fpcurlwp);
753 1.2 ad }
754 1.2 ad }
755 1.2 ad #endif
756 1.2 ad
757 1.2 ad static void
758 1.12 jmcneill cpu_copy_trampoline(void)
759 1.2 ad {
760 1.2 ad /*
761 1.2 ad * Copy boot code.
762 1.2 ad */
763 1.2 ad extern u_char cpu_spinup_trampoline[];
764 1.2 ad extern u_char cpu_spinup_trampoline_end[];
765 1.12 jmcneill
766 1.12 jmcneill vaddr_t mp_trampoline_vaddr;
767 1.12 jmcneill
768 1.12 jmcneill mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0,
769 1.12 jmcneill UVM_KMF_VAONLY);
770 1.12 jmcneill
771 1.12 jmcneill pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr,
772 1.12 jmcneill VM_PROT_READ | VM_PROT_WRITE);
773 1.2 ad pmap_update(pmap_kernel());
774 1.12 jmcneill memcpy((void *)mp_trampoline_vaddr,
775 1.2 ad cpu_spinup_trampoline,
776 1.26 cegger cpu_spinup_trampoline_end - cpu_spinup_trampoline);
777 1.12 jmcneill
778 1.12 jmcneill pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE);
779 1.12 jmcneill pmap_update(pmap_kernel());
780 1.12 jmcneill uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY);
781 1.2 ad }
782 1.2 ad
783 1.2 ad #ifdef i386
784 1.2 ad static void
785 1.15 yamt tss_init(struct i386tss *tss, void *stack, void *func)
786 1.2 ad {
787 1.2 ad memset(tss, 0, sizeof *tss);
788 1.2 ad tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16);
789 1.2 ad tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
790 1.2 ad tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL);
791 1.2 ad tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL);
792 1.2 ad tss->tss_gs = tss->__tss_es = tss->__tss_ds =
793 1.2 ad tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL);
794 1.2 ad tss->tss_cr3 = pmap_kernel()->pm_pdirpa;
795 1.2 ad tss->tss_esp = (int)((char *)stack + USPACE - 16);
796 1.2 ad tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
797 1.2 ad tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */
798 1.2 ad tss->__tss_eip = (int)func;
799 1.2 ad }
800 1.2 ad
801 1.2 ad /* XXX */
802 1.2 ad #define IDTVEC(name) __CONCAT(X, name)
803 1.2 ad typedef void (vector)(void);
804 1.2 ad extern vector IDTVEC(tss_trap08);
805 1.2 ad #ifdef DDB
806 1.2 ad extern vector Xintrddbipi;
807 1.2 ad extern int ddb_vec;
808 1.2 ad #endif
809 1.2 ad
810 1.2 ad static void
811 1.2 ad cpu_set_tss_gates(struct cpu_info *ci)
812 1.2 ad {
813 1.2 ad struct segment_descriptor sd;
814 1.2 ad
815 1.2 ad ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
816 1.2 ad UVM_KMF_WIRED);
817 1.15 yamt tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack,
818 1.2 ad IDTVEC(tss_trap08));
819 1.2 ad setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1,
820 1.2 ad SDT_SYS386TSS, SEL_KPL, 0, 0);
821 1.2 ad ci->ci_gdt[GTRAPTSS_SEL].sd = sd;
822 1.2 ad setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
823 1.2 ad GSEL(GTRAPTSS_SEL, SEL_KPL));
824 1.2 ad
825 1.44 ad #if defined(DDB)
826 1.2 ad /*
827 1.2 ad * Set up separate handler for the DDB IPI, so that it doesn't
828 1.2 ad * stomp on a possibly corrupted stack.
829 1.2 ad *
830 1.2 ad * XXX overwriting the gate set in db_machine_init.
831 1.2 ad * Should rearrange the code so that it's set only once.
832 1.2 ad */
833 1.2 ad ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
834 1.2 ad UVM_KMF_WIRED);
835 1.15 yamt tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, Xintrddbipi);
836 1.2 ad
837 1.2 ad setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1,
838 1.2 ad SDT_SYS386TSS, SEL_KPL, 0, 0);
839 1.2 ad ci->ci_gdt[GIPITSS_SEL].sd = sd;
840 1.2 ad
841 1.2 ad setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
842 1.2 ad GSEL(GIPITSS_SEL, SEL_KPL));
843 1.2 ad #endif
844 1.2 ad }
845 1.2 ad #else
846 1.2 ad static void
847 1.2 ad cpu_set_tss_gates(struct cpu_info *ci)
848 1.2 ad {
849 1.2 ad
850 1.2 ad }
851 1.2 ad #endif /* i386 */
852 1.2 ad
853 1.2 ad int
854 1.14 joerg mp_cpu_start(struct cpu_info *ci, paddr_t target)
855 1.2 ad {
856 1.44 ad unsigned short dwordptr[2];
857 1.2 ad int error;
858 1.14 joerg
859 1.14 joerg /*
860 1.14 joerg * Bootstrap code must be addressable in real mode
861 1.14 joerg * and it must be page aligned.
862 1.14 joerg */
863 1.14 joerg KASSERT(target < 0x10000 && target % PAGE_SIZE == 0);
864 1.2 ad
865 1.2 ad /*
866 1.2 ad * "The BSP must initialize CMOS shutdown code to 0Ah ..."
867 1.2 ad */
868 1.2 ad
869 1.2 ad outb(IO_RTC, NVRAM_RESET);
870 1.2 ad outb(IO_RTC+1, NVRAM_RESET_JUMP);
871 1.2 ad
872 1.2 ad /*
873 1.2 ad * "and the warm reset vector (DWORD based at 40:67) to point
874 1.2 ad * to the AP startup code ..."
875 1.2 ad */
876 1.2 ad
877 1.2 ad dwordptr[0] = 0;
878 1.14 joerg dwordptr[1] = target >> 4;
879 1.2 ad
880 1.25 ad memcpy((uint8_t *)cmos_data_mapping + 0x467, dwordptr, 4);
881 1.2 ad
882 1.25 ad if ((cpu_feature & CPUID_APIC) == 0) {
883 1.25 ad aprint_error("mp_cpu_start: CPU does not have APIC\n");
884 1.25 ad return ENODEV;
885 1.25 ad }
886 1.25 ad
887 1.2 ad /*
888 1.2 ad * ... prior to executing the following sequence:"
889 1.2 ad */
890 1.2 ad
891 1.2 ad if (ci->ci_flags & CPUF_AP) {
892 1.42 ad error = x86_ipi_init(ci->ci_cpuid);
893 1.26 cegger if (error != 0) {
894 1.26 cegger aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n",
895 1.26 cegger __func__);
896 1.2 ad return error;
897 1.25 ad }
898 1.2 ad
899 1.11 ad i8254_delay(10000);
900 1.2 ad
901 1.42 ad error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid,
902 1.26 cegger LAPIC_DLMODE_STARTUP);
903 1.26 cegger if (error != 0) {
904 1.26 cegger aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n",
905 1.26 cegger __func__);
906 1.25 ad return error;
907 1.25 ad }
908 1.25 ad i8254_delay(200);
909 1.2 ad
910 1.42 ad error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid,
911 1.26 cegger LAPIC_DLMODE_STARTUP);
912 1.26 cegger if (error != 0) {
913 1.26 cegger aprint_error_dev(ci->ci_dev, "%s: IPI not taken (3)\n",
914 1.26 cegger __func__);
915 1.25 ad return error;
916 1.2 ad }
917 1.25 ad i8254_delay(200);
918 1.2 ad }
919 1.44 ad
920 1.2 ad return 0;
921 1.2 ad }
922 1.2 ad
923 1.2 ad void
924 1.2 ad mp_cpu_start_cleanup(struct cpu_info *ci)
925 1.2 ad {
926 1.2 ad /*
927 1.2 ad * Ensure the NVRAM reset byte contains something vaguely sane.
928 1.2 ad */
929 1.2 ad
930 1.2 ad outb(IO_RTC, NVRAM_RESET);
931 1.2 ad outb(IO_RTC+1, NVRAM_RESET_RST);
932 1.2 ad }
933 1.2 ad
934 1.2 ad #ifdef __x86_64__
935 1.2 ad typedef void (vector)(void);
936 1.2 ad extern vector Xsyscall, Xsyscall32;
937 1.2 ad
938 1.2 ad void
939 1.12 jmcneill cpu_init_msrs(struct cpu_info *ci, bool full)
940 1.2 ad {
941 1.2 ad wrmsr(MSR_STAR,
942 1.2 ad ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
943 1.2 ad ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48));
944 1.2 ad wrmsr(MSR_LSTAR, (uint64_t)Xsyscall);
945 1.2 ad wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32);
946 1.2 ad wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C);
947 1.2 ad
948 1.12 jmcneill if (full) {
949 1.12 jmcneill wrmsr(MSR_FSBASE, 0);
950 1.27 cegger wrmsr(MSR_GSBASE, (uint64_t)ci);
951 1.12 jmcneill wrmsr(MSR_KERNELGSBASE, 0);
952 1.12 jmcneill }
953 1.2 ad
954 1.2 ad if (cpu_feature & CPUID_NOX)
955 1.2 ad wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE);
956 1.2 ad }
957 1.2 ad #endif /* __x86_64__ */
958 1.7 ad
959 1.18 joerg void
960 1.18 joerg cpu_offline_md(void)
961 1.18 joerg {
962 1.18 joerg int s;
963 1.18 joerg
964 1.18 joerg s = splhigh();
965 1.18 joerg #ifdef __i386__
966 1.18 joerg npxsave_cpu(true);
967 1.18 joerg #else
968 1.18 joerg fpusave_cpu(true);
969 1.18 joerg #endif
970 1.18 joerg splx(s);
971 1.18 joerg }
972 1.18 joerg
973 1.12 jmcneill /* XXX joerg restructure and restart CPUs individually */
974 1.12 jmcneill static bool
975 1.22 dyoung cpu_suspend(device_t dv PMF_FN_ARGS)
976 1.12 jmcneill {
977 1.12 jmcneill struct cpu_softc *sc = device_private(dv);
978 1.12 jmcneill struct cpu_info *ci = sc->sc_info;
979 1.18 joerg int err;
980 1.12 jmcneill
981 1.13 joerg if (ci->ci_flags & CPUF_PRIMARY)
982 1.12 jmcneill return true;
983 1.12 jmcneill if (ci->ci_data.cpu_idlelwp == NULL)
984 1.12 jmcneill return true;
985 1.12 jmcneill if ((ci->ci_flags & CPUF_PRESENT) == 0)
986 1.12 jmcneill return true;
987 1.12 jmcneill
988 1.20 jmcneill sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE);
989 1.17 joerg
990 1.20 jmcneill if (sc->sc_wasonline) {
991 1.20 jmcneill mutex_enter(&cpu_lock);
992 1.20 jmcneill err = cpu_setonline(ci, false);
993 1.20 jmcneill mutex_exit(&cpu_lock);
994 1.20 jmcneill
995 1.20 jmcneill if (err)
996 1.20 jmcneill return false;
997 1.20 jmcneill }
998 1.17 joerg
999 1.17 joerg return true;
1000 1.12 jmcneill }
1001 1.12 jmcneill
1002 1.12 jmcneill static bool
1003 1.22 dyoung cpu_resume(device_t dv PMF_FN_ARGS)
1004 1.12 jmcneill {
1005 1.12 jmcneill struct cpu_softc *sc = device_private(dv);
1006 1.12 jmcneill struct cpu_info *ci = sc->sc_info;
1007 1.20 jmcneill int err = 0;
1008 1.12 jmcneill
1009 1.13 joerg if (ci->ci_flags & CPUF_PRIMARY)
1010 1.12 jmcneill return true;
1011 1.12 jmcneill if (ci->ci_data.cpu_idlelwp == NULL)
1012 1.12 jmcneill return true;
1013 1.12 jmcneill if ((ci->ci_flags & CPUF_PRESENT) == 0)
1014 1.12 jmcneill return true;
1015 1.12 jmcneill
1016 1.20 jmcneill if (sc->sc_wasonline) {
1017 1.20 jmcneill mutex_enter(&cpu_lock);
1018 1.20 jmcneill err = cpu_setonline(ci, true);
1019 1.20 jmcneill mutex_exit(&cpu_lock);
1020 1.20 jmcneill }
1021 1.13 joerg
1022 1.13 joerg return err == 0;
1023 1.12 jmcneill }
1024 1.12 jmcneill
1025 1.7 ad void
1026 1.7 ad cpu_get_tsc_freq(struct cpu_info *ci)
1027 1.7 ad {
1028 1.7 ad uint64_t last_tsc;
1029 1.7 ad
1030 1.7 ad if (ci->ci_feature_flags & CPUID_TSC) {
1031 1.45 ad last_tsc = rdmsr(MSR_TSC);
1032 1.7 ad i8254_delay(100000);
1033 1.45 ad ci->ci_data.cpu_cc_freq = (rdmsr(MSR_TSC) - last_tsc) * 10;
1034 1.7 ad }
1035 1.7 ad }
1036 1.37 joerg
1037 1.37 joerg void
1038 1.37 joerg x86_cpu_idle_mwait(void)
1039 1.37 joerg {
1040 1.37 joerg struct cpu_info *ci = curcpu();
1041 1.37 joerg
1042 1.37 joerg KASSERT(ci->ci_ilevel == IPL_NONE);
1043 1.37 joerg
1044 1.37 joerg x86_monitor(&ci->ci_want_resched, 0, 0);
1045 1.37 joerg if (__predict_false(ci->ci_want_resched)) {
1046 1.37 joerg return;
1047 1.37 joerg }
1048 1.37 joerg x86_mwait(0, 0);
1049 1.37 joerg }
1050 1.37 joerg
1051 1.37 joerg void
1052 1.37 joerg x86_cpu_idle_halt(void)
1053 1.37 joerg {
1054 1.37 joerg struct cpu_info *ci = curcpu();
1055 1.37 joerg
1056 1.37 joerg KASSERT(ci->ci_ilevel == IPL_NONE);
1057 1.37 joerg
1058 1.37 joerg x86_disable_intr();
1059 1.37 joerg if (!__predict_false(ci->ci_want_resched)) {
1060 1.37 joerg x86_stihlt();
1061 1.37 joerg } else {
1062 1.37 joerg x86_enable_intr();
1063 1.37 joerg }
1064 1.37 joerg }
1065