cpu.c revision 1.109
1 /* $NetBSD: cpu.c,v 1.109 2014/02/19 21:23:02 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 2000-2012 NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999 Stefan Grefen 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by the NetBSD 46 * Foundation, Inc. and its contributors. 47 * 4. Neither the name of The NetBSD Foundation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.109 2014/02/19 21:23:02 dsl Exp $"); 66 67 #include "opt_ddb.h" 68 #include "opt_mpbios.h" /* for MPDEBUG */ 69 #include "opt_mtrr.h" 70 #include "opt_multiprocessor.h" 71 72 #include "lapic.h" 73 #include "ioapic.h" 74 75 #include <sys/param.h> 76 #include <sys/proc.h> 77 #include <sys/systm.h> 78 #include <sys/device.h> 79 #include <sys/kmem.h> 80 #include <sys/cpu.h> 81 #include <sys/cpufreq.h> 82 #include <sys/idle.h> 83 #include <sys/atomic.h> 84 #include <sys/reboot.h> 85 86 #include <uvm/uvm.h> 87 88 #include "acpica.h" /* for NACPICA, for mp_verbose */ 89 90 #include <machine/cpufunc.h> 91 #include <machine/cpuvar.h> 92 #include <machine/pmap.h> 93 #include <machine/vmparam.h> 94 #if defined(MULTIPROCESSOR) 95 #include <machine/mpbiosvar.h> 96 #endif 97 #include <machine/mpconfig.h> /* for mp_verbose */ 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 #include <machine/cpu_counter.h> 105 106 #include <x86/fpu.h> 107 108 #ifdef i386 109 #include <machine/tlog.h> 110 #endif 111 112 #if NLAPIC > 0 113 #include <machine/apicvar.h> 114 #include <machine/i82489reg.h> 115 #include <machine/i82489var.h> 116 #endif 117 118 #include <dev/ic/mc146818reg.h> 119 #include <i386/isa/nvram.h> 120 #include <dev/isa/isareg.h> 121 122 #include "tsc.h" 123 124 static int cpu_match(device_t, cfdata_t, void *); 125 static void cpu_attach(device_t, device_t, void *); 126 static void cpu_defer(device_t); 127 static int cpu_rescan(device_t, const char *, const int *); 128 static void cpu_childdetached(device_t, device_t); 129 static bool cpu_stop(device_t); 130 static bool cpu_suspend(device_t, const pmf_qual_t *); 131 static bool cpu_resume(device_t, const pmf_qual_t *); 132 static bool cpu_shutdown(device_t, int); 133 134 struct cpu_softc { 135 device_t sc_dev; /* device tree glue */ 136 struct cpu_info *sc_info; /* pointer to CPU info */ 137 bool sc_wasonline; 138 }; 139 140 #ifdef MULTIPROCESSOR 141 int mp_cpu_start(struct cpu_info *, paddr_t); 142 void mp_cpu_start_cleanup(struct cpu_info *); 143 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 144 mp_cpu_start_cleanup }; 145 #endif 146 147 148 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 149 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 150 151 /* 152 * Statically-allocated CPU info for the primary CPU (or the only 153 * CPU, on uniprocessors). The CPU info list is initialized to 154 * point at it. 155 */ 156 #ifdef TRAPLOG 157 struct tlog tlog_primary; 158 #endif 159 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 160 .ci_dev = 0, 161 .ci_self = &cpu_info_primary, 162 .ci_idepth = -1, 163 .ci_curlwp = &lwp0, 164 .ci_curldt = -1, 165 #ifdef TRAPLOG 166 .ci_tlog_base = &tlog_primary, 167 #endif /* !TRAPLOG */ 168 }; 169 170 struct cpu_info *cpu_info_list = &cpu_info_primary; 171 172 static void cpu_set_tss_gates(struct cpu_info *); 173 174 #ifdef i386 175 static void tss_init(struct i386tss *, void *, void *); 176 #endif 177 178 static void cpu_init_idle_lwp(struct cpu_info *); 179 180 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 181 * [0] basic features %edx 182 * [1] basic features %ecx 183 * [2] extended features %edx 184 * [3] extended features %ecx 185 * [4] VIA padlock features 186 */ 187 188 extern char x86_64_doubleflt_stack[]; 189 190 #ifdef MULTIPROCESSOR 191 bool x86_mp_online; 192 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 193 #endif 194 #if NLAPIC > 0 195 static vaddr_t cmos_data_mapping; 196 #endif 197 struct cpu_info *cpu_starting; 198 199 #ifdef MULTIPROCESSOR 200 void cpu_hatch(void *); 201 static void cpu_boot_secondary(struct cpu_info *ci); 202 static void cpu_start_secondary(struct cpu_info *ci); 203 #endif 204 #if NLAPIC > 0 205 static void cpu_copy_trampoline(void); 206 #endif 207 208 /* 209 * Runs once per boot once multiprocessor goo has been detected and 210 * the local APIC on the boot processor has been mapped. 211 * 212 * Called from lapic_boot_init() (from mpbios_scan()). 213 */ 214 #if NLAPIC > 0 215 void 216 cpu_init_first(void) 217 { 218 219 cpu_info_primary.ci_cpuid = lapic_cpu_number(); 220 cpu_copy_trampoline(); 221 222 cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY); 223 if (cmos_data_mapping == 0) 224 panic("No KVA for page 0"); 225 pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE, 0); 226 pmap_update(pmap_kernel()); 227 } 228 #endif 229 230 static int 231 cpu_match(device_t parent, cfdata_t match, void *aux) 232 { 233 234 return 1; 235 } 236 237 static void 238 cpu_vm_init(struct cpu_info *ci) 239 { 240 int ncolors = 2, i; 241 242 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 243 struct x86_cache_info *cai; 244 int tcolors; 245 246 cai = &ci->ci_cinfo[i]; 247 248 tcolors = atop(cai->cai_totalsize); 249 switch(cai->cai_associativity) { 250 case 0xff: 251 tcolors = 1; /* fully associative */ 252 break; 253 case 0: 254 case 1: 255 break; 256 default: 257 tcolors /= cai->cai_associativity; 258 } 259 ncolors = max(ncolors, tcolors); 260 /* 261 * If the desired number of colors is not a power of 262 * two, it won't be good. Find the greatest power of 263 * two which is an even divisor of the number of colors, 264 * to preserve even coloring of pages. 265 */ 266 if (ncolors & (ncolors - 1) ) { 267 int try, picked = 1; 268 for (try = 1; try < ncolors; try *= 2) { 269 if (ncolors % try == 0) picked = try; 270 } 271 if (picked == 1) { 272 panic("desired number of cache colors %d is " 273 " > 1, but not even!", ncolors); 274 } 275 ncolors = picked; 276 } 277 } 278 279 /* 280 * Knowing the size of the largest cache on this CPU, potentially 281 * re-color our pages. 282 */ 283 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 284 uvm_page_recolor(ncolors); 285 286 pmap_tlb_cpu_init(ci); 287 } 288 289 static void 290 cpu_attach(device_t parent, device_t self, void *aux) 291 { 292 struct cpu_softc *sc = device_private(self); 293 struct cpu_attach_args *caa = aux; 294 struct cpu_info *ci; 295 uintptr_t ptr; 296 #if NLAPIC > 0 297 int cpunum = caa->cpu_number; 298 #endif 299 static bool again; 300 301 sc->sc_dev = self; 302 303 if (ncpu == maxcpus) { 304 #ifndef _LP64 305 aprint_error(": too many CPUs, please use NetBSD/amd64\n"); 306 #else 307 aprint_error(": too many CPUs\n"); 308 #endif 309 return; 310 } 311 312 /* 313 * If we're an Application Processor, allocate a cpu_info 314 * structure, otherwise use the primary's. 315 */ 316 if (caa->cpu_role == CPU_ROLE_AP) { 317 if ((boothowto & RB_MD1) != 0) { 318 aprint_error(": multiprocessor boot disabled\n"); 319 if (!pmf_device_register(self, NULL, NULL)) 320 aprint_error_dev(self, 321 "couldn't establish power handler\n"); 322 return; 323 } 324 aprint_naive(": Application Processor\n"); 325 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 326 KM_SLEEP); 327 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 328 ci->ci_curldt = -1; 329 #ifdef TRAPLOG 330 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 331 #endif 332 } else { 333 aprint_naive(": %s Processor\n", 334 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 335 ci = &cpu_info_primary; 336 #if NLAPIC > 0 337 if (cpunum != lapic_cpu_number()) { 338 /* XXX should be done earlier. */ 339 uint32_t reg; 340 aprint_verbose("\n"); 341 aprint_verbose_dev(self, "running CPU at apic %d" 342 " instead of at expected %d", lapic_cpu_number(), 343 cpunum); 344 reg = i82489_readreg(LAPIC_ID); 345 i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) | 346 (cpunum << LAPIC_ID_SHIFT)); 347 } 348 if (cpunum != lapic_cpu_number()) { 349 aprint_error_dev(self, "unable to reset apic id\n"); 350 } 351 #endif 352 } 353 354 ci->ci_self = ci; 355 sc->sc_info = ci; 356 ci->ci_dev = self; 357 ci->ci_acpiid = caa->cpu_id; 358 ci->ci_cpuid = caa->cpu_number; 359 ci->ci_func = caa->cpu_func; 360 361 /* Must be before mi_cpu_attach(). */ 362 cpu_vm_init(ci); 363 364 if (caa->cpu_role == CPU_ROLE_AP) { 365 int error; 366 367 error = mi_cpu_attach(ci); 368 if (error != 0) { 369 aprint_normal("\n"); 370 aprint_error_dev(self, 371 "mi_cpu_attach failed with %d\n", error); 372 return; 373 } 374 cpu_init_tss(ci); 375 } else { 376 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 377 } 378 379 pmap_reference(pmap_kernel()); 380 ci->ci_pmap = pmap_kernel(); 381 ci->ci_tlbstate = TLBSTATE_STALE; 382 383 /* 384 * Boot processor may not be attached first, but the below 385 * must be done to allow booting other processors. 386 */ 387 if (!again) { 388 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 389 /* Basic init. */ 390 cpu_intr_init(ci); 391 cpu_get_tsc_freq(ci); 392 cpu_init(ci); 393 cpu_set_tss_gates(ci); 394 pmap_cpu_init_late(ci); 395 #if NLAPIC > 0 396 if (caa->cpu_role != CPU_ROLE_SP) { 397 /* Enable lapic. */ 398 lapic_enable(); 399 lapic_set_lvt(); 400 lapic_calibrate_timer(ci); 401 } 402 #endif 403 /* Make sure DELAY() is initialized. */ 404 DELAY(1); 405 again = true; 406 } 407 408 /* further PCB init done later. */ 409 410 switch (caa->cpu_role) { 411 case CPU_ROLE_SP: 412 atomic_or_32(&ci->ci_flags, CPUF_SP); 413 cpu_identify(ci); 414 x86_errata(); 415 x86_cpu_idle_init(); 416 break; 417 418 case CPU_ROLE_BP: 419 atomic_or_32(&ci->ci_flags, CPUF_BSP); 420 cpu_identify(ci); 421 x86_errata(); 422 x86_cpu_idle_init(); 423 break; 424 425 #ifdef MULTIPROCESSOR 426 case CPU_ROLE_AP: 427 /* 428 * report on an AP 429 */ 430 cpu_intr_init(ci); 431 gdt_alloc_cpu(ci); 432 cpu_set_tss_gates(ci); 433 pmap_cpu_init_late(ci); 434 cpu_start_secondary(ci); 435 if (ci->ci_flags & CPUF_PRESENT) { 436 struct cpu_info *tmp; 437 438 cpu_identify(ci); 439 tmp = cpu_info_list; 440 while (tmp->ci_next) 441 tmp = tmp->ci_next; 442 443 tmp->ci_next = ci; 444 } 445 break; 446 #endif 447 448 default: 449 aprint_normal("\n"); 450 panic("unknown processor type??\n"); 451 } 452 453 pat_init(ci); 454 455 if (!pmf_device_register1(self, cpu_suspend, cpu_resume, cpu_shutdown)) 456 aprint_error_dev(self, "couldn't establish power handler\n"); 457 458 #ifdef MULTIPROCESSOR 459 if (mp_verbose) { 460 struct lwp *l = ci->ci_data.cpu_idlelwp; 461 struct pcb *pcb = lwp_getpcb(l); 462 463 aprint_verbose_dev(self, 464 "idle lwp at %p, idle sp at %p\n", 465 l, 466 #ifdef i386 467 (void *)pcb->pcb_esp 468 #else 469 (void *)pcb->pcb_rsp 470 #endif 471 ); 472 } 473 #endif 474 475 /* 476 * Postpone the "cpufeaturebus" scan. 477 * It is safe to scan the pseudo-bus 478 * only after all CPUs have attached. 479 */ 480 (void)config_defer(self, cpu_defer); 481 } 482 483 static void 484 cpu_defer(device_t self) 485 { 486 cpu_rescan(self, NULL, NULL); 487 } 488 489 static int 490 cpu_rescan(device_t self, const char *ifattr, const int *locators) 491 { 492 struct cpu_softc *sc = device_private(self); 493 struct cpufeature_attach_args cfaa; 494 struct cpu_info *ci = sc->sc_info; 495 496 memset(&cfaa, 0, sizeof(cfaa)); 497 cfaa.ci = ci; 498 499 if (ifattr_match(ifattr, "cpufeaturebus")) { 500 501 if (ci->ci_frequency == NULL) { 502 cfaa.name = "frequency"; 503 ci->ci_frequency = config_found_ia(self, 504 "cpufeaturebus", &cfaa, NULL); 505 } 506 507 if (ci->ci_padlock == NULL) { 508 cfaa.name = "padlock"; 509 ci->ci_padlock = config_found_ia(self, 510 "cpufeaturebus", &cfaa, NULL); 511 } 512 513 if (ci->ci_temperature == NULL) { 514 cfaa.name = "temperature"; 515 ci->ci_temperature = config_found_ia(self, 516 "cpufeaturebus", &cfaa, NULL); 517 } 518 519 if (ci->ci_vm == NULL) { 520 cfaa.name = "vm"; 521 ci->ci_vm = config_found_ia(self, 522 "cpufeaturebus", &cfaa, NULL); 523 } 524 } 525 526 return 0; 527 } 528 529 static void 530 cpu_childdetached(device_t self, device_t child) 531 { 532 struct cpu_softc *sc = device_private(self); 533 struct cpu_info *ci = sc->sc_info; 534 535 if (ci->ci_frequency == child) 536 ci->ci_frequency = NULL; 537 538 if (ci->ci_padlock == child) 539 ci->ci_padlock = NULL; 540 541 if (ci->ci_temperature == child) 542 ci->ci_temperature = NULL; 543 544 if (ci->ci_vm == child) 545 ci->ci_vm = NULL; 546 } 547 548 /* 549 * Initialize the processor appropriately. 550 */ 551 552 void 553 cpu_init(struct cpu_info *ci) 554 { 555 556 lcr0(rcr0() | CR0_WP); 557 558 /* 559 * On a P6 or above, enable global TLB caching if the 560 * hardware supports it. 561 */ 562 if (cpu_feature[0] & CPUID_PGE) 563 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 564 565 /* 566 * If we have FXSAVE/FXRESTOR, use them. 567 */ 568 if (cpu_feature[0] & CPUID_FXSR) { 569 lcr4(rcr4() | CR4_OSFXSR); 570 571 /* 572 * If we have SSE/SSE2, enable XMM exceptions. 573 */ 574 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 575 lcr4(rcr4() | CR4_OSXMMEXCPT); 576 } 577 578 #ifdef MTRR 579 /* 580 * On a P6 or above, initialize MTRR's if the hardware supports them. 581 */ 582 if (cpu_feature[0] & CPUID_MTRR) { 583 if ((ci->ci_flags & CPUF_AP) == 0) 584 i686_mtrr_init_first(); 585 mtrr_init_cpu(ci); 586 } 587 588 #ifdef i386 589 if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) { 590 /* 591 * Must be a K6-2 Step >= 7 or a K6-III. 592 */ 593 if (CPUID_TO_FAMILY(ci->ci_signature) == 5) { 594 if (CPUID_TO_MODEL(ci->ci_signature) > 8 || 595 (CPUID_TO_MODEL(ci->ci_signature) == 8 && 596 CPUID_TO_STEPPING(ci->ci_signature) >= 7)) { 597 mtrr_funcs = &k6_mtrr_funcs; 598 k6_mtrr_init_first(); 599 mtrr_init_cpu(ci); 600 } 601 } 602 } 603 #endif /* i386 */ 604 #endif /* MTRR */ 605 606 if (ci != &cpu_info_primary) { 607 /* Synchronize TSC again, and check for drift. */ 608 wbinvd(); 609 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 610 tsc_sync_ap(ci); 611 } else { 612 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 613 } 614 } 615 616 #ifdef MULTIPROCESSOR 617 void 618 cpu_boot_secondary_processors(void) 619 { 620 struct cpu_info *ci; 621 kcpuset_t *cpus; 622 u_long i; 623 624 /* Now that we know the number of CPUs, patch the text segment. */ 625 x86_patch(false); 626 627 kcpuset_create(&cpus, true); 628 kcpuset_set(cpus, cpu_index(curcpu())); 629 for (i = 0; i < maxcpus; i++) { 630 ci = cpu_lookup(i); 631 if (ci == NULL) 632 continue; 633 if (ci->ci_data.cpu_idlelwp == NULL) 634 continue; 635 if ((ci->ci_flags & CPUF_PRESENT) == 0) 636 continue; 637 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 638 continue; 639 cpu_boot_secondary(ci); 640 kcpuset_set(cpus, cpu_index(ci)); 641 } 642 while (!kcpuset_match(cpus, kcpuset_running)) 643 ; 644 kcpuset_destroy(cpus); 645 646 x86_mp_online = true; 647 648 /* Now that we know about the TSC, attach the timecounter. */ 649 tsc_tc_init(); 650 651 /* Enable zeroing of pages in the idle loop if we have SSE2. */ 652 vm_page_zero_enable = ((cpu_feature[0] & CPUID_SSE2) != 0); 653 } 654 #endif 655 656 static void 657 cpu_init_idle_lwp(struct cpu_info *ci) 658 { 659 struct lwp *l = ci->ci_data.cpu_idlelwp; 660 struct pcb *pcb = lwp_getpcb(l); 661 662 pcb->pcb_cr0 = rcr0(); 663 } 664 665 void 666 cpu_init_idle_lwps(void) 667 { 668 struct cpu_info *ci; 669 u_long i; 670 671 for (i = 0; i < maxcpus; i++) { 672 ci = cpu_lookup(i); 673 if (ci == NULL) 674 continue; 675 if (ci->ci_data.cpu_idlelwp == NULL) 676 continue; 677 if ((ci->ci_flags & CPUF_PRESENT) == 0) 678 continue; 679 cpu_init_idle_lwp(ci); 680 } 681 } 682 683 #ifdef MULTIPROCESSOR 684 void 685 cpu_start_secondary(struct cpu_info *ci) 686 { 687 extern paddr_t mp_pdirpa; 688 u_long psl; 689 int i; 690 691 mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr); 692 atomic_or_32(&ci->ci_flags, CPUF_AP); 693 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 694 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) { 695 return; 696 } 697 698 /* 699 * Wait for it to become ready. Setting cpu_starting opens the 700 * initial gate and allows the AP to start soft initialization. 701 */ 702 KASSERT(cpu_starting == NULL); 703 cpu_starting = ci; 704 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 705 #ifdef MPDEBUG 706 extern int cpu_trace[3]; 707 static int otrace[3]; 708 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 709 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 710 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 711 memcpy(otrace, cpu_trace, sizeof(otrace)); 712 } 713 #endif 714 i8254_delay(10); 715 } 716 717 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 718 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 719 #if defined(MPDEBUG) && defined(DDB) 720 printf("dropping into debugger; continue from here to resume boot\n"); 721 Debugger(); 722 #endif 723 } else { 724 /* 725 * Synchronize time stamp counters. Invalidate cache and do 726 * twice to try and minimize possible cache effects. Disable 727 * interrupts to try and rule out any external interference. 728 */ 729 psl = x86_read_psl(); 730 x86_disable_intr(); 731 wbinvd(); 732 tsc_sync_bp(ci); 733 x86_write_psl(psl); 734 } 735 736 CPU_START_CLEANUP(ci); 737 cpu_starting = NULL; 738 } 739 740 void 741 cpu_boot_secondary(struct cpu_info *ci) 742 { 743 int64_t drift; 744 u_long psl; 745 int i; 746 747 atomic_or_32(&ci->ci_flags, CPUF_GO); 748 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 749 i8254_delay(10); 750 } 751 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 752 aprint_error_dev(ci->ci_dev, "failed to start\n"); 753 #if defined(MPDEBUG) && defined(DDB) 754 printf("dropping into debugger; continue from here to resume boot\n"); 755 Debugger(); 756 #endif 757 } else { 758 /* Synchronize TSC again, check for drift. */ 759 drift = ci->ci_data.cpu_cc_skew; 760 psl = x86_read_psl(); 761 x86_disable_intr(); 762 wbinvd(); 763 tsc_sync_bp(ci); 764 x86_write_psl(psl); 765 drift -= ci->ci_data.cpu_cc_skew; 766 aprint_debug_dev(ci->ci_dev, "TSC skew=%lld drift=%lld\n", 767 (long long)ci->ci_data.cpu_cc_skew, (long long)drift); 768 tsc_sync_drift(drift); 769 } 770 } 771 772 /* 773 * The CPU ends up here when its ready to run 774 * This is called from code in mptramp.s; at this point, we are running 775 * in the idle pcb/idle stack of the new CPU. When this function returns, 776 * this processor will enter the idle loop and start looking for work. 777 */ 778 void 779 cpu_hatch(void *v) 780 { 781 struct cpu_info *ci = (struct cpu_info *)v; 782 struct pcb *pcb; 783 int s, i; 784 785 cpu_init_msrs(ci, true); 786 cpu_probe(ci); 787 788 ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq; 789 /* cpu_get_tsc_freq(ci); */ 790 791 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 792 793 /* 794 * Synchronize time stamp counters. Invalidate cache and do twice 795 * to try and minimize possible cache effects. Note that interrupts 796 * are off at this point. 797 */ 798 wbinvd(); 799 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 800 tsc_sync_ap(ci); 801 802 /* 803 * Wait to be brought online. Use 'monitor/mwait' if available, 804 * in order to make the TSC drift as much as possible. so that 805 * we can detect it later. If not available, try 'pause'. 806 * We'd like to use 'hlt', but we have interrupts off. 807 */ 808 while ((ci->ci_flags & CPUF_GO) == 0) { 809 if ((cpu_feature[1] & CPUID2_MONITOR) != 0) { 810 x86_monitor(&ci->ci_flags, 0, 0); 811 if ((ci->ci_flags & CPUF_GO) != 0) { 812 continue; 813 } 814 x86_mwait(0, 0); 815 } else { 816 for (i = 10000; i != 0; i--) { 817 x86_pause(); 818 } 819 } 820 } 821 822 /* Because the text may have been patched in x86_patch(). */ 823 wbinvd(); 824 x86_flush(); 825 tlbflushg(); 826 827 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 828 829 #ifdef PAE 830 pd_entry_t * l3_pd = ci->ci_pae_l3_pdir; 831 for (i = 0 ; i < PDP_SIZE; i++) { 832 l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PG_V; 833 } 834 lcr3(ci->ci_pae_l3_pdirpa); 835 #else 836 lcr3(pmap_pdirpa(pmap_kernel(), 0)); 837 #endif 838 839 pcb = lwp_getpcb(curlwp); 840 pcb->pcb_cr3 = rcr3(); 841 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 842 lcr0(pcb->pcb_cr0); 843 844 cpu_init_idt(); 845 gdt_init_cpu(ci); 846 lapic_enable(); 847 lapic_set_lvt(); 848 lapic_initclocks(); 849 850 fpuinit(ci); 851 lldt(GSYSSEL(GLDT_SEL, SEL_KPL)); 852 ltr(ci->ci_tss_sel); 853 854 cpu_init(ci); 855 cpu_get_tsc_freq(ci); 856 857 s = splhigh(); 858 #ifdef i386 859 lapic_tpr = 0; 860 #else 861 lcr8(0); 862 #endif 863 x86_enable_intr(); 864 splx(s); 865 x86_errata(); 866 867 aprint_debug_dev(ci->ci_dev, "running\n"); 868 869 idle_loop(NULL); 870 KASSERT(false); 871 } 872 #endif 873 874 #if defined(DDB) 875 876 #include <ddb/db_output.h> 877 #include <machine/db_machdep.h> 878 879 /* 880 * Dump CPU information from ddb. 881 */ 882 void 883 cpu_debug_dump(void) 884 { 885 struct cpu_info *ci; 886 CPU_INFO_ITERATOR cii; 887 888 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 889 for (CPU_INFO_FOREACH(cii, ci)) { 890 db_printf("%p %s %ld %x %x %10p %10p\n", 891 ci, 892 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 893 (long)ci->ci_cpuid, 894 ci->ci_flags, ci->ci_ipis, 895 ci->ci_curlwp, 896 ci->ci_fpcurlwp); 897 } 898 } 899 #endif 900 901 #if NLAPIC > 0 902 static void 903 cpu_copy_trampoline(void) 904 { 905 /* 906 * Copy boot code. 907 */ 908 extern u_char cpu_spinup_trampoline[]; 909 extern u_char cpu_spinup_trampoline_end[]; 910 911 vaddr_t mp_trampoline_vaddr; 912 913 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 914 UVM_KMF_VAONLY); 915 916 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 917 VM_PROT_READ | VM_PROT_WRITE, 0); 918 pmap_update(pmap_kernel()); 919 memcpy((void *)mp_trampoline_vaddr, 920 cpu_spinup_trampoline, 921 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 922 923 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 924 pmap_update(pmap_kernel()); 925 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 926 } 927 #endif 928 929 #ifdef i386 930 static void 931 tss_init(struct i386tss *tss, void *stack, void *func) 932 { 933 KASSERT(curcpu()->ci_pmap == pmap_kernel()); 934 935 memset(tss, 0, sizeof *tss); 936 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 937 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 938 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 939 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 940 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 941 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 942 /* %cr3 contains the value associated to pmap_kernel */ 943 tss->tss_cr3 = rcr3(); 944 tss->tss_esp = (int)((char *)stack + USPACE - 16); 945 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 946 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 947 tss->__tss_eip = (int)func; 948 } 949 950 /* XXX */ 951 #define IDTVEC(name) __CONCAT(X, name) 952 typedef void (vector)(void); 953 extern vector IDTVEC(tss_trap08); 954 #if defined(DDB) && defined(MULTIPROCESSOR) 955 extern vector Xintrddbipi; 956 extern int ddb_vec; 957 #endif 958 959 static void 960 cpu_set_tss_gates(struct cpu_info *ci) 961 { 962 struct segment_descriptor sd; 963 964 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 965 UVM_KMF_WIRED); 966 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 967 IDTVEC(tss_trap08)); 968 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 969 SDT_SYS386TSS, SEL_KPL, 0, 0); 970 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 971 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 972 GSEL(GTRAPTSS_SEL, SEL_KPL)); 973 974 #if defined(DDB) && defined(MULTIPROCESSOR) 975 /* 976 * Set up separate handler for the DDB IPI, so that it doesn't 977 * stomp on a possibly corrupted stack. 978 * 979 * XXX overwriting the gate set in db_machine_init. 980 * Should rearrange the code so that it's set only once. 981 */ 982 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 983 UVM_KMF_WIRED); 984 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, Xintrddbipi); 985 986 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 987 SDT_SYS386TSS, SEL_KPL, 0, 0); 988 ci->ci_gdt[GIPITSS_SEL].sd = sd; 989 990 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 991 GSEL(GIPITSS_SEL, SEL_KPL)); 992 #endif 993 } 994 #else 995 static void 996 cpu_set_tss_gates(struct cpu_info *ci) 997 { 998 999 } 1000 #endif /* i386 */ 1001 1002 #ifdef MULTIPROCESSOR 1003 int 1004 mp_cpu_start(struct cpu_info *ci, paddr_t target) 1005 { 1006 unsigned short dwordptr[2]; 1007 int error; 1008 1009 /* 1010 * Bootstrap code must be addressable in real mode 1011 * and it must be page aligned. 1012 */ 1013 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 1014 1015 /* 1016 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 1017 */ 1018 1019 outb(IO_RTC, NVRAM_RESET); 1020 outb(IO_RTC+1, NVRAM_RESET_JUMP); 1021 1022 /* 1023 * "and the warm reset vector (DWORD based at 40:67) to point 1024 * to the AP startup code ..." 1025 */ 1026 1027 dwordptr[0] = 0; 1028 dwordptr[1] = target >> 4; 1029 1030 memcpy((uint8_t *)cmos_data_mapping + 0x467, dwordptr, 4); 1031 1032 if ((cpu_feature[0] & CPUID_APIC) == 0) { 1033 aprint_error("mp_cpu_start: CPU does not have APIC\n"); 1034 return ENODEV; 1035 } 1036 1037 /* 1038 * ... prior to executing the following sequence:". We'll also add in 1039 * local cache flush, in case the BIOS has left the AP with its cache 1040 * disabled. It may not be able to cope with MP coherency. 1041 */ 1042 wbinvd(); 1043 1044 if (ci->ci_flags & CPUF_AP) { 1045 error = x86_ipi_init(ci->ci_cpuid); 1046 if (error != 0) { 1047 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 1048 __func__); 1049 return error; 1050 } 1051 i8254_delay(10000); 1052 1053 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1054 if (error != 0) { 1055 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 1056 __func__); 1057 return error; 1058 } 1059 i8254_delay(200); 1060 1061 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1062 if (error != 0) { 1063 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (3)\n", 1064 __func__); 1065 return error; 1066 } 1067 i8254_delay(200); 1068 } 1069 1070 return 0; 1071 } 1072 1073 void 1074 mp_cpu_start_cleanup(struct cpu_info *ci) 1075 { 1076 /* 1077 * Ensure the NVRAM reset byte contains something vaguely sane. 1078 */ 1079 1080 outb(IO_RTC, NVRAM_RESET); 1081 outb(IO_RTC+1, NVRAM_RESET_RST); 1082 } 1083 #endif 1084 1085 #ifdef __x86_64__ 1086 typedef void (vector)(void); 1087 extern vector Xsyscall, Xsyscall32; 1088 #endif 1089 1090 void 1091 cpu_init_msrs(struct cpu_info *ci, bool full) 1092 { 1093 #ifdef __x86_64__ 1094 wrmsr(MSR_STAR, 1095 ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1096 ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48)); 1097 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall); 1098 wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32); 1099 wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C); 1100 1101 if (full) { 1102 wrmsr(MSR_FSBASE, 0); 1103 wrmsr(MSR_GSBASE, (uint64_t)ci); 1104 wrmsr(MSR_KERNELGSBASE, 0); 1105 } 1106 #endif /* __x86_64__ */ 1107 1108 if (cpu_feature[2] & CPUID_NOX) 1109 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1110 } 1111 1112 void 1113 cpu_offline_md(void) 1114 { 1115 int s; 1116 1117 s = splhigh(); 1118 fpusave_cpu(true); 1119 splx(s); 1120 } 1121 1122 /* XXX joerg restructure and restart CPUs individually */ 1123 static bool 1124 cpu_stop(device_t dv) 1125 { 1126 struct cpu_softc *sc = device_private(dv); 1127 struct cpu_info *ci = sc->sc_info; 1128 int err; 1129 1130 KASSERT((ci->ci_flags & CPUF_PRESENT) != 0); 1131 1132 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1133 return true; 1134 1135 if (ci->ci_data.cpu_idlelwp == NULL) 1136 return true; 1137 1138 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1139 1140 if (sc->sc_wasonline) { 1141 mutex_enter(&cpu_lock); 1142 err = cpu_setstate(ci, false); 1143 mutex_exit(&cpu_lock); 1144 1145 if (err != 0) 1146 return false; 1147 } 1148 1149 return true; 1150 } 1151 1152 static bool 1153 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1154 { 1155 struct cpu_softc *sc = device_private(dv); 1156 struct cpu_info *ci = sc->sc_info; 1157 1158 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1159 return true; 1160 else { 1161 cpufreq_suspend(ci); 1162 } 1163 1164 return cpu_stop(dv); 1165 } 1166 1167 static bool 1168 cpu_resume(device_t dv, const pmf_qual_t *qual) 1169 { 1170 struct cpu_softc *sc = device_private(dv); 1171 struct cpu_info *ci = sc->sc_info; 1172 int err = 0; 1173 1174 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1175 return true; 1176 1177 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1178 goto out; 1179 1180 if (ci->ci_data.cpu_idlelwp == NULL) 1181 goto out; 1182 1183 if (sc->sc_wasonline) { 1184 mutex_enter(&cpu_lock); 1185 err = cpu_setstate(ci, true); 1186 mutex_exit(&cpu_lock); 1187 } 1188 1189 out: 1190 if (err != 0) 1191 return false; 1192 1193 cpufreq_resume(ci); 1194 1195 return true; 1196 } 1197 1198 static bool 1199 cpu_shutdown(device_t dv, int how) 1200 { 1201 struct cpu_softc *sc = device_private(dv); 1202 struct cpu_info *ci = sc->sc_info; 1203 1204 if ((ci->ci_flags & CPUF_BSP) != 0) 1205 return false; 1206 1207 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1208 return true; 1209 1210 return cpu_stop(dv); 1211 } 1212 1213 void 1214 cpu_get_tsc_freq(struct cpu_info *ci) 1215 { 1216 uint64_t last_tsc; 1217 1218 if (cpu_hascounter()) { 1219 last_tsc = cpu_counter_serializing(); 1220 i8254_delay(100000); 1221 ci->ci_data.cpu_cc_freq = 1222 (cpu_counter_serializing() - last_tsc) * 10; 1223 } 1224 } 1225 1226 void 1227 x86_cpu_idle_mwait(void) 1228 { 1229 struct cpu_info *ci = curcpu(); 1230 1231 KASSERT(ci->ci_ilevel == IPL_NONE); 1232 1233 x86_monitor(&ci->ci_want_resched, 0, 0); 1234 if (__predict_false(ci->ci_want_resched)) { 1235 return; 1236 } 1237 x86_mwait(0, 0); 1238 } 1239 1240 void 1241 x86_cpu_idle_halt(void) 1242 { 1243 struct cpu_info *ci = curcpu(); 1244 1245 KASSERT(ci->ci_ilevel == IPL_NONE); 1246 1247 x86_disable_intr(); 1248 if (!__predict_false(ci->ci_want_resched)) { 1249 x86_stihlt(); 1250 } else { 1251 x86_enable_intr(); 1252 } 1253 } 1254 1255 /* 1256 * Loads pmap for the current CPU. 1257 */ 1258 void 1259 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1260 { 1261 #ifdef PAE 1262 struct cpu_info *ci = curcpu(); 1263 pd_entry_t *l3_pd = ci->ci_pae_l3_pdir; 1264 int i; 1265 1266 /* 1267 * disable interrupts to block TLB shootdowns, which can reload cr3. 1268 * while this doesn't block NMIs, it's probably ok as NMIs unlikely 1269 * reload cr3. 1270 */ 1271 x86_disable_intr(); 1272 for (i = 0 ; i < PDP_SIZE; i++) { 1273 l3_pd[i] = pmap->pm_pdirpa[i] | PG_V; 1274 } 1275 x86_enable_intr(); 1276 tlbflush(); 1277 #else /* PAE */ 1278 lcr3(pmap_pdirpa(pmap, 0)); 1279 #endif /* PAE */ 1280 } 1281 1282 /* 1283 * Notify all other cpus to halt. 1284 */ 1285 1286 void 1287 cpu_broadcast_halt(void) 1288 { 1289 x86_broadcast_ipi(X86_IPI_HALT); 1290 } 1291 1292 /* 1293 * Send a dummy ipi to a cpu to force it to run splraise()/spllower() 1294 */ 1295 1296 void 1297 cpu_kick(struct cpu_info *ci) 1298 { 1299 x86_send_ipi(ci, 0); 1300 } 1301
Indexes created Fri Sep 26 20:09:58 GMT 2025