cpu.c revision 1.111
1 /* $NetBSD: cpu.c,v 1.111 2014/05/12 11:56:02 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2000-2012 NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999 Stefan Grefen 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by the NetBSD 46 * Foundation, Inc. and its contributors. 47 * 4. Neither the name of The NetBSD Foundation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.111 2014/05/12 11:56:02 joerg Exp $"); 66 67 #include "opt_ddb.h" 68 #include "opt_mpbios.h" /* for MPDEBUG */ 69 #include "opt_mtrr.h" 70 #include "opt_multiprocessor.h" 71 72 #include "lapic.h" 73 #include "ioapic.h" 74 75 #include <sys/param.h> 76 #include <sys/proc.h> 77 #include <sys/systm.h> 78 #include <sys/device.h> 79 #include <sys/kmem.h> 80 #include <sys/cpu.h> 81 #include <sys/cpufreq.h> 82 #include <sys/idle.h> 83 #include <sys/atomic.h> 84 #include <sys/reboot.h> 85 86 #include <uvm/uvm.h> 87 88 #include "acpica.h" /* for NACPICA, for mp_verbose */ 89 90 #include <machine/cpufunc.h> 91 #include <machine/cpuvar.h> 92 #include <machine/pmap.h> 93 #include <machine/vmparam.h> 94 #if defined(MULTIPROCESSOR) 95 #include <machine/mpbiosvar.h> 96 #endif 97 #include <machine/mpconfig.h> /* for mp_verbose */ 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 #include <machine/cpu_counter.h> 105 106 #include <x86/fpu.h> 107 108 #ifdef i386 109 #include <machine/tlog.h> 110 #endif 111 112 #if NLAPIC > 0 113 #include <machine/apicvar.h> 114 #include <machine/i82489reg.h> 115 #include <machine/i82489var.h> 116 #endif 117 118 #include <dev/ic/mc146818reg.h> 119 #include <i386/isa/nvram.h> 120 #include <dev/isa/isareg.h> 121 122 #include "tsc.h" 123 124 static int cpu_match(device_t, cfdata_t, void *); 125 static void cpu_attach(device_t, device_t, void *); 126 static void cpu_defer(device_t); 127 static int cpu_rescan(device_t, const char *, const int *); 128 static void cpu_childdetached(device_t, device_t); 129 static bool cpu_stop(device_t); 130 static bool cpu_suspend(device_t, const pmf_qual_t *); 131 static bool cpu_resume(device_t, const pmf_qual_t *); 132 static bool cpu_shutdown(device_t, int); 133 134 struct cpu_softc { 135 device_t sc_dev; /* device tree glue */ 136 struct cpu_info *sc_info; /* pointer to CPU info */ 137 bool sc_wasonline; 138 }; 139 140 #ifdef MULTIPROCESSOR 141 int mp_cpu_start(struct cpu_info *, paddr_t); 142 void mp_cpu_start_cleanup(struct cpu_info *); 143 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 144 mp_cpu_start_cleanup }; 145 #endif 146 147 148 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 149 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 150 151 /* 152 * Statically-allocated CPU info for the primary CPU (or the only 153 * CPU, on uniprocessors). The CPU info list is initialized to 154 * point at it. 155 */ 156 #ifdef TRAPLOG 157 struct tlog tlog_primary; 158 #endif 159 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 160 .ci_dev = 0, 161 .ci_self = &cpu_info_primary, 162 .ci_idepth = -1, 163 .ci_curlwp = &lwp0, 164 .ci_curldt = -1, 165 #ifdef TRAPLOG 166 .ci_tlog_base = &tlog_primary, 167 #endif /* !TRAPLOG */ 168 }; 169 170 struct cpu_info *cpu_info_list = &cpu_info_primary; 171 172 static void cpu_set_tss_gates(struct cpu_info *); 173 174 #ifdef i386 175 static void tss_init(struct i386tss *, void *, void *); 176 #endif 177 178 static void cpu_init_idle_lwp(struct cpu_info *); 179 180 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 181 * [0] basic features %edx 182 * [1] basic features %ecx 183 * [2] extended features %edx 184 * [3] extended features %ecx 185 * [4] VIA padlock features 186 */ 187 188 extern char x86_64_doubleflt_stack[]; 189 190 #ifdef MULTIPROCESSOR 191 bool x86_mp_online; 192 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 193 #endif 194 #if NLAPIC > 0 195 static vaddr_t cmos_data_mapping; 196 #endif 197 struct cpu_info *cpu_starting; 198 199 #ifdef MULTIPROCESSOR 200 void cpu_hatch(void *); 201 static void cpu_boot_secondary(struct cpu_info *ci); 202 static void cpu_start_secondary(struct cpu_info *ci); 203 #endif 204 #if NLAPIC > 0 205 static void cpu_copy_trampoline(void); 206 #endif 207 208 /* 209 * Runs once per boot once multiprocessor goo has been detected and 210 * the local APIC on the boot processor has been mapped. 211 * 212 * Called from lapic_boot_init() (from mpbios_scan()). 213 */ 214 #if NLAPIC > 0 215 void 216 cpu_init_first(void) 217 { 218 219 cpu_info_primary.ci_cpuid = lapic_cpu_number(); 220 cpu_copy_trampoline(); 221 222 cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY); 223 if (cmos_data_mapping == 0) 224 panic("No KVA for page 0"); 225 pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE, 0); 226 pmap_update(pmap_kernel()); 227 } 228 #endif 229 230 static int 231 cpu_match(device_t parent, cfdata_t match, void *aux) 232 { 233 234 return 1; 235 } 236 237 static void 238 cpu_vm_init(struct cpu_info *ci) 239 { 240 int ncolors = 2, i; 241 242 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 243 struct x86_cache_info *cai; 244 int tcolors; 245 246 cai = &ci->ci_cinfo[i]; 247 248 tcolors = atop(cai->cai_totalsize); 249 switch(cai->cai_associativity) { 250 case 0xff: 251 tcolors = 1; /* fully associative */ 252 break; 253 case 0: 254 case 1: 255 break; 256 default: 257 tcolors /= cai->cai_associativity; 258 } 259 ncolors = max(ncolors, tcolors); 260 /* 261 * If the desired number of colors is not a power of 262 * two, it won't be good. Find the greatest power of 263 * two which is an even divisor of the number of colors, 264 * to preserve even coloring of pages. 265 */ 266 if (ncolors & (ncolors - 1) ) { 267 int try, picked = 1; 268 for (try = 1; try < ncolors; try *= 2) { 269 if (ncolors % try == 0) picked = try; 270 } 271 if (picked == 1) { 272 panic("desired number of cache colors %d is " 273 " > 1, but not even!", ncolors); 274 } 275 ncolors = picked; 276 } 277 } 278 279 /* 280 * Knowing the size of the largest cache on this CPU, potentially 281 * re-color our pages. 282 */ 283 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 284 uvm_page_recolor(ncolors); 285 286 pmap_tlb_cpu_init(ci); 287 } 288 289 static void 290 cpu_attach(device_t parent, device_t self, void *aux) 291 { 292 struct cpu_softc *sc = device_private(self); 293 struct cpu_attach_args *caa = aux; 294 struct cpu_info *ci; 295 uintptr_t ptr; 296 #if NLAPIC > 0 297 int cpunum = caa->cpu_number; 298 #endif 299 static bool again; 300 301 sc->sc_dev = self; 302 303 if (ncpu == maxcpus) { 304 #ifndef _LP64 305 aprint_error(": too many CPUs, please use NetBSD/amd64\n"); 306 #else 307 aprint_error(": too many CPUs\n"); 308 #endif 309 return; 310 } 311 312 /* 313 * If we're an Application Processor, allocate a cpu_info 314 * structure, otherwise use the primary's. 315 */ 316 if (caa->cpu_role == CPU_ROLE_AP) { 317 if ((boothowto & RB_MD1) != 0) { 318 aprint_error(": multiprocessor boot disabled\n"); 319 if (!pmf_device_register(self, NULL, NULL)) 320 aprint_error_dev(self, 321 "couldn't establish power handler\n"); 322 return; 323 } 324 aprint_naive(": Application Processor\n"); 325 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 326 KM_SLEEP); 327 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 328 ci->ci_curldt = -1; 329 #ifdef TRAPLOG 330 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 331 #endif 332 } else { 333 aprint_naive(": %s Processor\n", 334 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 335 ci = &cpu_info_primary; 336 #if NLAPIC > 0 337 if (cpunum != lapic_cpu_number()) { 338 /* XXX should be done earlier. */ 339 uint32_t reg; 340 aprint_verbose("\n"); 341 aprint_verbose_dev(self, "running CPU at apic %d" 342 " instead of at expected %d", lapic_cpu_number(), 343 cpunum); 344 reg = i82489_readreg(LAPIC_ID); 345 i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) | 346 (cpunum << LAPIC_ID_SHIFT)); 347 } 348 if (cpunum != lapic_cpu_number()) { 349 aprint_error_dev(self, "unable to reset apic id\n"); 350 } 351 #endif 352 } 353 354 ci->ci_self = ci; 355 sc->sc_info = ci; 356 ci->ci_dev = self; 357 ci->ci_acpiid = caa->cpu_id; 358 ci->ci_cpuid = caa->cpu_number; 359 ci->ci_func = caa->cpu_func; 360 361 /* Must be before mi_cpu_attach(). */ 362 cpu_vm_init(ci); 363 364 if (caa->cpu_role == CPU_ROLE_AP) { 365 int error; 366 367 error = mi_cpu_attach(ci); 368 if (error != 0) { 369 aprint_normal("\n"); 370 aprint_error_dev(self, 371 "mi_cpu_attach failed with %d\n", error); 372 return; 373 } 374 cpu_init_tss(ci); 375 } else { 376 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 377 } 378 379 pmap_reference(pmap_kernel()); 380 ci->ci_pmap = pmap_kernel(); 381 ci->ci_tlbstate = TLBSTATE_STALE; 382 383 /* 384 * Boot processor may not be attached first, but the below 385 * must be done to allow booting other processors. 386 */ 387 if (!again) { 388 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 389 /* Basic init. */ 390 cpu_intr_init(ci); 391 cpu_get_tsc_freq(ci); 392 cpu_init(ci); 393 cpu_set_tss_gates(ci); 394 pmap_cpu_init_late(ci); 395 #if NLAPIC > 0 396 if (caa->cpu_role != CPU_ROLE_SP) { 397 /* Enable lapic. */ 398 lapic_enable(); 399 lapic_set_lvt(); 400 lapic_calibrate_timer(ci); 401 } 402 #endif 403 /* Make sure DELAY() is initialized. */ 404 DELAY(1); 405 again = true; 406 } 407 408 /* further PCB init done later. */ 409 410 switch (caa->cpu_role) { 411 case CPU_ROLE_SP: 412 atomic_or_32(&ci->ci_flags, CPUF_SP); 413 cpu_identify(ci); 414 x86_errata(); 415 x86_cpu_idle_init(); 416 break; 417 418 case CPU_ROLE_BP: 419 atomic_or_32(&ci->ci_flags, CPUF_BSP); 420 cpu_identify(ci); 421 x86_errata(); 422 x86_cpu_idle_init(); 423 break; 424 425 #ifdef MULTIPROCESSOR 426 case CPU_ROLE_AP: 427 /* 428 * report on an AP 429 */ 430 cpu_intr_init(ci); 431 gdt_alloc_cpu(ci); 432 cpu_set_tss_gates(ci); 433 pmap_cpu_init_late(ci); 434 cpu_start_secondary(ci); 435 if (ci->ci_flags & CPUF_PRESENT) { 436 struct cpu_info *tmp; 437 438 cpu_identify(ci); 439 tmp = cpu_info_list; 440 while (tmp->ci_next) 441 tmp = tmp->ci_next; 442 443 tmp->ci_next = ci; 444 } 445 break; 446 #endif 447 448 default: 449 aprint_normal("\n"); 450 panic("unknown processor type??\n"); 451 } 452 453 pat_init(ci); 454 455 if (!pmf_device_register1(self, cpu_suspend, cpu_resume, cpu_shutdown)) 456 aprint_error_dev(self, "couldn't establish power handler\n"); 457 458 #ifdef MULTIPROCESSOR 459 if (mp_verbose) { 460 struct lwp *l = ci->ci_data.cpu_idlelwp; 461 struct pcb *pcb = lwp_getpcb(l); 462 463 aprint_verbose_dev(self, 464 "idle lwp at %p, idle sp at %p\n", 465 l, 466 #ifdef i386 467 (void *)pcb->pcb_esp 468 #else 469 (void *)pcb->pcb_rsp 470 #endif 471 ); 472 } 473 #endif 474 475 /* 476 * Postpone the "cpufeaturebus" scan. 477 * It is safe to scan the pseudo-bus 478 * only after all CPUs have attached. 479 */ 480 (void)config_defer(self, cpu_defer); 481 } 482 483 static void 484 cpu_defer(device_t self) 485 { 486 cpu_rescan(self, NULL, NULL); 487 } 488 489 static int 490 cpu_rescan(device_t self, const char *ifattr, const int *locators) 491 { 492 struct cpu_softc *sc = device_private(self); 493 struct cpufeature_attach_args cfaa; 494 struct cpu_info *ci = sc->sc_info; 495 496 memset(&cfaa, 0, sizeof(cfaa)); 497 cfaa.ci = ci; 498 499 if (ifattr_match(ifattr, "cpufeaturebus")) { 500 501 if (ci->ci_frequency == NULL) { 502 cfaa.name = "frequency"; 503 ci->ci_frequency = config_found_ia(self, 504 "cpufeaturebus", &cfaa, NULL); 505 } 506 507 if (ci->ci_padlock == NULL) { 508 cfaa.name = "padlock"; 509 ci->ci_padlock = config_found_ia(self, 510 "cpufeaturebus", &cfaa, NULL); 511 } 512 513 if (ci->ci_temperature == NULL) { 514 cfaa.name = "temperature"; 515 ci->ci_temperature = config_found_ia(self, 516 "cpufeaturebus", &cfaa, NULL); 517 } 518 519 if (ci->ci_vm == NULL) { 520 cfaa.name = "vm"; 521 ci->ci_vm = config_found_ia(self, 522 "cpufeaturebus", &cfaa, NULL); 523 } 524 } 525 526 return 0; 527 } 528 529 static void 530 cpu_childdetached(device_t self, device_t child) 531 { 532 struct cpu_softc *sc = device_private(self); 533 struct cpu_info *ci = sc->sc_info; 534 535 if (ci->ci_frequency == child) 536 ci->ci_frequency = NULL; 537 538 if (ci->ci_padlock == child) 539 ci->ci_padlock = NULL; 540 541 if (ci->ci_temperature == child) 542 ci->ci_temperature = NULL; 543 544 if (ci->ci_vm == child) 545 ci->ci_vm = NULL; 546 } 547 548 /* 549 * Initialize the processor appropriately. 550 */ 551 552 void 553 cpu_init(struct cpu_info *ci) 554 { 555 uint32_t cr4; 556 557 lcr0(rcr0() | CR0_WP); 558 559 cr4 = rcr4(); 560 /* 561 * On a P6 or above, enable global TLB caching if the 562 * hardware supports it. 563 */ 564 if (cpu_feature[0] & CPUID_PGE) 565 cr4 |= CR4_PGE; /* enable global TLB caching */ 566 567 /* 568 * If we have FXSAVE/FXRESTOR, use them. 569 */ 570 if (cpu_feature[0] & CPUID_FXSR) { 571 cr4 |= CR4_OSFXSR; 572 573 /* 574 * If we have SSE/SSE2, enable XMM exceptions. 575 */ 576 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 577 cr4 |= CR4_OSXMMEXCPT; 578 } 579 580 /* If xsave is supported, enable it */ 581 if (cpu_feature[1] & CPUID2_XSAVE) 582 cr4 |= CR4_OSXSAVE; 583 584 lcr4(cr4); 585 586 /* If xsave is enabled, enable all fpu features */ 587 if (cr4 & CR4_OSXSAVE) 588 wrxcr(0, x86_xsave_features & XCR0_FPU); 589 590 #ifdef MTRR 591 /* 592 * On a P6 or above, initialize MTRR's if the hardware supports them. 593 */ 594 if (cpu_feature[0] & CPUID_MTRR) { 595 if ((ci->ci_flags & CPUF_AP) == 0) 596 i686_mtrr_init_first(); 597 mtrr_init_cpu(ci); 598 } 599 600 #ifdef i386 601 if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) { 602 /* 603 * Must be a K6-2 Step >= 7 or a K6-III. 604 */ 605 if (CPUID_TO_FAMILY(ci->ci_signature) == 5) { 606 if (CPUID_TO_MODEL(ci->ci_signature) > 8 || 607 (CPUID_TO_MODEL(ci->ci_signature) == 8 && 608 CPUID_TO_STEPPING(ci->ci_signature) >= 7)) { 609 mtrr_funcs = &k6_mtrr_funcs; 610 k6_mtrr_init_first(); 611 mtrr_init_cpu(ci); 612 } 613 } 614 } 615 #endif /* i386 */ 616 #endif /* MTRR */ 617 618 if (ci != &cpu_info_primary) { 619 /* Synchronize TSC again, and check for drift. */ 620 wbinvd(); 621 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 622 tsc_sync_ap(ci); 623 } else { 624 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 625 } 626 } 627 628 #ifdef MULTIPROCESSOR 629 void 630 cpu_boot_secondary_processors(void) 631 { 632 struct cpu_info *ci; 633 kcpuset_t *cpus; 634 u_long i; 635 636 /* Now that we know the number of CPUs, patch the text segment. */ 637 x86_patch(false); 638 639 kcpuset_create(&cpus, true); 640 kcpuset_set(cpus, cpu_index(curcpu())); 641 for (i = 0; i < maxcpus; i++) { 642 ci = cpu_lookup(i); 643 if (ci == NULL) 644 continue; 645 if (ci->ci_data.cpu_idlelwp == NULL) 646 continue; 647 if ((ci->ci_flags & CPUF_PRESENT) == 0) 648 continue; 649 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 650 continue; 651 cpu_boot_secondary(ci); 652 kcpuset_set(cpus, cpu_index(ci)); 653 } 654 while (!kcpuset_match(cpus, kcpuset_running)) 655 ; 656 kcpuset_destroy(cpus); 657 658 x86_mp_online = true; 659 660 /* Now that we know about the TSC, attach the timecounter. */ 661 tsc_tc_init(); 662 663 /* Enable zeroing of pages in the idle loop if we have SSE2. */ 664 vm_page_zero_enable = ((cpu_feature[0] & CPUID_SSE2) != 0); 665 } 666 #endif 667 668 static void 669 cpu_init_idle_lwp(struct cpu_info *ci) 670 { 671 struct lwp *l = ci->ci_data.cpu_idlelwp; 672 struct pcb *pcb = lwp_getpcb(l); 673 674 pcb->pcb_cr0 = rcr0(); 675 } 676 677 void 678 cpu_init_idle_lwps(void) 679 { 680 struct cpu_info *ci; 681 u_long i; 682 683 for (i = 0; i < maxcpus; i++) { 684 ci = cpu_lookup(i); 685 if (ci == NULL) 686 continue; 687 if (ci->ci_data.cpu_idlelwp == NULL) 688 continue; 689 if ((ci->ci_flags & CPUF_PRESENT) == 0) 690 continue; 691 cpu_init_idle_lwp(ci); 692 } 693 } 694 695 #ifdef MULTIPROCESSOR 696 void 697 cpu_start_secondary(struct cpu_info *ci) 698 { 699 extern paddr_t mp_pdirpa; 700 u_long psl; 701 int i; 702 703 mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr); 704 atomic_or_32(&ci->ci_flags, CPUF_AP); 705 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 706 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) { 707 return; 708 } 709 710 /* 711 * Wait for it to become ready. Setting cpu_starting opens the 712 * initial gate and allows the AP to start soft initialization. 713 */ 714 KASSERT(cpu_starting == NULL); 715 cpu_starting = ci; 716 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 717 #ifdef MPDEBUG 718 extern int cpu_trace[3]; 719 static int otrace[3]; 720 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 721 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 722 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 723 memcpy(otrace, cpu_trace, sizeof(otrace)); 724 } 725 #endif 726 i8254_delay(10); 727 } 728 729 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 730 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 731 #if defined(MPDEBUG) && defined(DDB) 732 printf("dropping into debugger; continue from here to resume boot\n"); 733 Debugger(); 734 #endif 735 } else { 736 /* 737 * Synchronize time stamp counters. Invalidate cache and do 738 * twice to try and minimize possible cache effects. Disable 739 * interrupts to try and rule out any external interference. 740 */ 741 psl = x86_read_psl(); 742 x86_disable_intr(); 743 wbinvd(); 744 tsc_sync_bp(ci); 745 x86_write_psl(psl); 746 } 747 748 CPU_START_CLEANUP(ci); 749 cpu_starting = NULL; 750 } 751 752 void 753 cpu_boot_secondary(struct cpu_info *ci) 754 { 755 int64_t drift; 756 u_long psl; 757 int i; 758 759 atomic_or_32(&ci->ci_flags, CPUF_GO); 760 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 761 i8254_delay(10); 762 } 763 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 764 aprint_error_dev(ci->ci_dev, "failed to start\n"); 765 #if defined(MPDEBUG) && defined(DDB) 766 printf("dropping into debugger; continue from here to resume boot\n"); 767 Debugger(); 768 #endif 769 } else { 770 /* Synchronize TSC again, check for drift. */ 771 drift = ci->ci_data.cpu_cc_skew; 772 psl = x86_read_psl(); 773 x86_disable_intr(); 774 wbinvd(); 775 tsc_sync_bp(ci); 776 x86_write_psl(psl); 777 drift -= ci->ci_data.cpu_cc_skew; 778 aprint_debug_dev(ci->ci_dev, "TSC skew=%lld drift=%lld\n", 779 (long long)ci->ci_data.cpu_cc_skew, (long long)drift); 780 tsc_sync_drift(drift); 781 } 782 } 783 784 /* 785 * The CPU ends up here when its ready to run 786 * This is called from code in mptramp.s; at this point, we are running 787 * in the idle pcb/idle stack of the new CPU. When this function returns, 788 * this processor will enter the idle loop and start looking for work. 789 */ 790 void 791 cpu_hatch(void *v) 792 { 793 struct cpu_info *ci = (struct cpu_info *)v; 794 struct pcb *pcb; 795 int s, i; 796 797 cpu_init_msrs(ci, true); 798 cpu_probe(ci); 799 800 ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq; 801 /* cpu_get_tsc_freq(ci); */ 802 803 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 804 805 /* 806 * Synchronize time stamp counters. Invalidate cache and do twice 807 * to try and minimize possible cache effects. Note that interrupts 808 * are off at this point. 809 */ 810 wbinvd(); 811 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 812 tsc_sync_ap(ci); 813 814 /* 815 * Wait to be brought online. Use 'monitor/mwait' if available, 816 * in order to make the TSC drift as much as possible. so that 817 * we can detect it later. If not available, try 'pause'. 818 * We'd like to use 'hlt', but we have interrupts off. 819 */ 820 while ((ci->ci_flags & CPUF_GO) == 0) { 821 if ((cpu_feature[1] & CPUID2_MONITOR) != 0) { 822 x86_monitor(&ci->ci_flags, 0, 0); 823 if ((ci->ci_flags & CPUF_GO) != 0) { 824 continue; 825 } 826 x86_mwait(0, 0); 827 } else { 828 for (i = 10000; i != 0; i--) { 829 x86_pause(); 830 } 831 } 832 } 833 834 /* Because the text may have been patched in x86_patch(). */ 835 wbinvd(); 836 x86_flush(); 837 tlbflushg(); 838 839 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 840 841 #ifdef PAE 842 pd_entry_t * l3_pd = ci->ci_pae_l3_pdir; 843 for (i = 0 ; i < PDP_SIZE; i++) { 844 l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PG_V; 845 } 846 lcr3(ci->ci_pae_l3_pdirpa); 847 #else 848 lcr3(pmap_pdirpa(pmap_kernel(), 0)); 849 #endif 850 851 pcb = lwp_getpcb(curlwp); 852 pcb->pcb_cr3 = rcr3(); 853 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 854 lcr0(pcb->pcb_cr0); 855 856 cpu_init_idt(); 857 gdt_init_cpu(ci); 858 #if NLAPIC > 0 859 lapic_enable(); 860 lapic_set_lvt(); 861 lapic_initclocks(); 862 #endif 863 864 fpuinit(ci); 865 lldt(GSYSSEL(GLDT_SEL, SEL_KPL)); 866 ltr(ci->ci_tss_sel); 867 868 cpu_init(ci); 869 cpu_get_tsc_freq(ci); 870 871 s = splhigh(); 872 #ifdef i386 873 lapic_tpr = 0; 874 #else 875 lcr8(0); 876 #endif 877 x86_enable_intr(); 878 splx(s); 879 x86_errata(); 880 881 aprint_debug_dev(ci->ci_dev, "running\n"); 882 883 idle_loop(NULL); 884 KASSERT(false); 885 } 886 #endif 887 888 #if defined(DDB) 889 890 #include <ddb/db_output.h> 891 #include <machine/db_machdep.h> 892 893 /* 894 * Dump CPU information from ddb. 895 */ 896 void 897 cpu_debug_dump(void) 898 { 899 struct cpu_info *ci; 900 CPU_INFO_ITERATOR cii; 901 902 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 903 for (CPU_INFO_FOREACH(cii, ci)) { 904 db_printf("%p %s %ld %x %x %10p %10p\n", 905 ci, 906 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 907 (long)ci->ci_cpuid, 908 ci->ci_flags, ci->ci_ipis, 909 ci->ci_curlwp, 910 ci->ci_fpcurlwp); 911 } 912 } 913 #endif 914 915 #if NLAPIC > 0 916 static void 917 cpu_copy_trampoline(void) 918 { 919 /* 920 * Copy boot code. 921 */ 922 extern u_char cpu_spinup_trampoline[]; 923 extern u_char cpu_spinup_trampoline_end[]; 924 925 vaddr_t mp_trampoline_vaddr; 926 927 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 928 UVM_KMF_VAONLY); 929 930 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 931 VM_PROT_READ | VM_PROT_WRITE, 0); 932 pmap_update(pmap_kernel()); 933 memcpy((void *)mp_trampoline_vaddr, 934 cpu_spinup_trampoline, 935 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 936 937 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 938 pmap_update(pmap_kernel()); 939 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 940 } 941 #endif 942 943 #ifdef i386 944 static void 945 tss_init(struct i386tss *tss, void *stack, void *func) 946 { 947 KASSERT(curcpu()->ci_pmap == pmap_kernel()); 948 949 memset(tss, 0, sizeof *tss); 950 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 951 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 952 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 953 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 954 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 955 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 956 /* %cr3 contains the value associated to pmap_kernel */ 957 tss->tss_cr3 = rcr3(); 958 tss->tss_esp = (int)((char *)stack + USPACE - 16); 959 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 960 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 961 tss->__tss_eip = (int)func; 962 } 963 964 /* XXX */ 965 #define IDTVEC(name) __CONCAT(X, name) 966 typedef void (vector)(void); 967 extern vector IDTVEC(tss_trap08); 968 #if defined(DDB) && defined(MULTIPROCESSOR) 969 extern vector Xintrddbipi; 970 extern int ddb_vec; 971 #endif 972 973 static void 974 cpu_set_tss_gates(struct cpu_info *ci) 975 { 976 struct segment_descriptor sd; 977 978 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 979 UVM_KMF_WIRED); 980 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 981 IDTVEC(tss_trap08)); 982 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 983 SDT_SYS386TSS, SEL_KPL, 0, 0); 984 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 985 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 986 GSEL(GTRAPTSS_SEL, SEL_KPL)); 987 988 #if defined(DDB) && defined(MULTIPROCESSOR) 989 /* 990 * Set up separate handler for the DDB IPI, so that it doesn't 991 * stomp on a possibly corrupted stack. 992 * 993 * XXX overwriting the gate set in db_machine_init. 994 * Should rearrange the code so that it's set only once. 995 */ 996 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 997 UVM_KMF_WIRED); 998 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, Xintrddbipi); 999 1000 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 1001 SDT_SYS386TSS, SEL_KPL, 0, 0); 1002 ci->ci_gdt[GIPITSS_SEL].sd = sd; 1003 1004 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 1005 GSEL(GIPITSS_SEL, SEL_KPL)); 1006 #endif 1007 } 1008 #else 1009 static void 1010 cpu_set_tss_gates(struct cpu_info *ci) 1011 { 1012 1013 } 1014 #endif /* i386 */ 1015 1016 #ifdef MULTIPROCESSOR 1017 int 1018 mp_cpu_start(struct cpu_info *ci, paddr_t target) 1019 { 1020 unsigned short dwordptr[2]; 1021 int error; 1022 1023 /* 1024 * Bootstrap code must be addressable in real mode 1025 * and it must be page aligned. 1026 */ 1027 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 1028 1029 /* 1030 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 1031 */ 1032 1033 outb(IO_RTC, NVRAM_RESET); 1034 outb(IO_RTC+1, NVRAM_RESET_JUMP); 1035 1036 /* 1037 * "and the warm reset vector (DWORD based at 40:67) to point 1038 * to the AP startup code ..." 1039 */ 1040 1041 dwordptr[0] = 0; 1042 dwordptr[1] = target >> 4; 1043 1044 #if NLAPIC > 0 1045 memcpy((uint8_t *)cmos_data_mapping + 0x467, dwordptr, 4); 1046 #endif 1047 1048 if ((cpu_feature[0] & CPUID_APIC) == 0) { 1049 aprint_error("mp_cpu_start: CPU does not have APIC\n"); 1050 return ENODEV; 1051 } 1052 1053 /* 1054 * ... prior to executing the following sequence:". We'll also add in 1055 * local cache flush, in case the BIOS has left the AP with its cache 1056 * disabled. It may not be able to cope with MP coherency. 1057 */ 1058 wbinvd(); 1059 1060 if (ci->ci_flags & CPUF_AP) { 1061 error = x86_ipi_init(ci->ci_cpuid); 1062 if (error != 0) { 1063 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 1064 __func__); 1065 return error; 1066 } 1067 i8254_delay(10000); 1068 1069 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1070 if (error != 0) { 1071 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 1072 __func__); 1073 return error; 1074 } 1075 i8254_delay(200); 1076 1077 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1078 if (error != 0) { 1079 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (3)\n", 1080 __func__); 1081 return error; 1082 } 1083 i8254_delay(200); 1084 } 1085 1086 return 0; 1087 } 1088 1089 void 1090 mp_cpu_start_cleanup(struct cpu_info *ci) 1091 { 1092 /* 1093 * Ensure the NVRAM reset byte contains something vaguely sane. 1094 */ 1095 1096 outb(IO_RTC, NVRAM_RESET); 1097 outb(IO_RTC+1, NVRAM_RESET_RST); 1098 } 1099 #endif 1100 1101 #ifdef __x86_64__ 1102 typedef void (vector)(void); 1103 extern vector Xsyscall, Xsyscall32; 1104 #endif 1105 1106 void 1107 cpu_init_msrs(struct cpu_info *ci, bool full) 1108 { 1109 #ifdef __x86_64__ 1110 wrmsr(MSR_STAR, 1111 ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1112 ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48)); 1113 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall); 1114 wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32); 1115 wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C); 1116 1117 if (full) { 1118 wrmsr(MSR_FSBASE, 0); 1119 wrmsr(MSR_GSBASE, (uint64_t)ci); 1120 wrmsr(MSR_KERNELGSBASE, 0); 1121 } 1122 #endif /* __x86_64__ */ 1123 1124 if (cpu_feature[2] & CPUID_NOX) 1125 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1126 } 1127 1128 void 1129 cpu_offline_md(void) 1130 { 1131 int s; 1132 1133 s = splhigh(); 1134 fpusave_cpu(true); 1135 splx(s); 1136 } 1137 1138 /* XXX joerg restructure and restart CPUs individually */ 1139 static bool 1140 cpu_stop(device_t dv) 1141 { 1142 struct cpu_softc *sc = device_private(dv); 1143 struct cpu_info *ci = sc->sc_info; 1144 int err; 1145 1146 KASSERT((ci->ci_flags & CPUF_PRESENT) != 0); 1147 1148 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1149 return true; 1150 1151 if (ci->ci_data.cpu_idlelwp == NULL) 1152 return true; 1153 1154 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1155 1156 if (sc->sc_wasonline) { 1157 mutex_enter(&cpu_lock); 1158 err = cpu_setstate(ci, false); 1159 mutex_exit(&cpu_lock); 1160 1161 if (err != 0) 1162 return false; 1163 } 1164 1165 return true; 1166 } 1167 1168 static bool 1169 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1170 { 1171 struct cpu_softc *sc = device_private(dv); 1172 struct cpu_info *ci = sc->sc_info; 1173 1174 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1175 return true; 1176 else { 1177 cpufreq_suspend(ci); 1178 } 1179 1180 return cpu_stop(dv); 1181 } 1182 1183 static bool 1184 cpu_resume(device_t dv, const pmf_qual_t *qual) 1185 { 1186 struct cpu_softc *sc = device_private(dv); 1187 struct cpu_info *ci = sc->sc_info; 1188 int err = 0; 1189 1190 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1191 return true; 1192 1193 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1194 goto out; 1195 1196 if (ci->ci_data.cpu_idlelwp == NULL) 1197 goto out; 1198 1199 if (sc->sc_wasonline) { 1200 mutex_enter(&cpu_lock); 1201 err = cpu_setstate(ci, true); 1202 mutex_exit(&cpu_lock); 1203 } 1204 1205 out: 1206 if (err != 0) 1207 return false; 1208 1209 cpufreq_resume(ci); 1210 1211 return true; 1212 } 1213 1214 static bool 1215 cpu_shutdown(device_t dv, int how) 1216 { 1217 struct cpu_softc *sc = device_private(dv); 1218 struct cpu_info *ci = sc->sc_info; 1219 1220 if ((ci->ci_flags & CPUF_BSP) != 0) 1221 return false; 1222 1223 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1224 return true; 1225 1226 return cpu_stop(dv); 1227 } 1228 1229 void 1230 cpu_get_tsc_freq(struct cpu_info *ci) 1231 { 1232 uint64_t last_tsc; 1233 1234 if (cpu_hascounter()) { 1235 last_tsc = cpu_counter_serializing(); 1236 i8254_delay(100000); 1237 ci->ci_data.cpu_cc_freq = 1238 (cpu_counter_serializing() - last_tsc) * 10; 1239 } 1240 } 1241 1242 void 1243 x86_cpu_idle_mwait(void) 1244 { 1245 struct cpu_info *ci = curcpu(); 1246 1247 KASSERT(ci->ci_ilevel == IPL_NONE); 1248 1249 x86_monitor(&ci->ci_want_resched, 0, 0); 1250 if (__predict_false(ci->ci_want_resched)) { 1251 return; 1252 } 1253 x86_mwait(0, 0); 1254 } 1255 1256 void 1257 x86_cpu_idle_halt(void) 1258 { 1259 struct cpu_info *ci = curcpu(); 1260 1261 KASSERT(ci->ci_ilevel == IPL_NONE); 1262 1263 x86_disable_intr(); 1264 if (!__predict_false(ci->ci_want_resched)) { 1265 x86_stihlt(); 1266 } else { 1267 x86_enable_intr(); 1268 } 1269 } 1270 1271 /* 1272 * Loads pmap for the current CPU. 1273 */ 1274 void 1275 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1276 { 1277 #ifdef PAE 1278 struct cpu_info *ci = curcpu(); 1279 pd_entry_t *l3_pd = ci->ci_pae_l3_pdir; 1280 int i; 1281 1282 /* 1283 * disable interrupts to block TLB shootdowns, which can reload cr3. 1284 * while this doesn't block NMIs, it's probably ok as NMIs unlikely 1285 * reload cr3. 1286 */ 1287 x86_disable_intr(); 1288 for (i = 0 ; i < PDP_SIZE; i++) { 1289 l3_pd[i] = pmap->pm_pdirpa[i] | PG_V; 1290 } 1291 x86_enable_intr(); 1292 tlbflush(); 1293 #else /* PAE */ 1294 lcr3(pmap_pdirpa(pmap, 0)); 1295 #endif /* PAE */ 1296 } 1297 1298 /* 1299 * Notify all other cpus to halt. 1300 */ 1301 1302 void 1303 cpu_broadcast_halt(void) 1304 { 1305 x86_broadcast_ipi(X86_IPI_HALT); 1306 } 1307 1308 /* 1309 * Send a dummy ipi to a cpu to force it to run splraise()/spllower() 1310 */ 1311 1312 void 1313 cpu_kick(struct cpu_info *ci) 1314 { 1315 x86_send_ipi(ci, 0); 1316 } 1317
Indexes created Tue Sep 23 14:10:03 GMT 2025