cpu.c revision 1.112
1 /* $NetBSD: cpu.c,v 1.112 2014/12/08 15:22:47 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000-2012 NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999 Stefan Grefen 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by the NetBSD 46 * Foundation, Inc. and its contributors. 47 * 4. Neither the name of The NetBSD Foundation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.112 2014/12/08 15:22:47 msaitoh Exp $"); 66 67 #include "opt_ddb.h" 68 #include "opt_mpbios.h" /* for MPDEBUG */ 69 #include "opt_mtrr.h" 70 #include "opt_multiprocessor.h" 71 72 #include "lapic.h" 73 #include "ioapic.h" 74 75 #include <sys/param.h> 76 #include <sys/proc.h> 77 #include <sys/systm.h> 78 #include <sys/device.h> 79 #include <sys/kmem.h> 80 #include <sys/cpu.h> 81 #include <sys/cpufreq.h> 82 #include <sys/idle.h> 83 #include <sys/atomic.h> 84 #include <sys/reboot.h> 85 86 #include <uvm/uvm.h> 87 88 #include "acpica.h" /* for NACPICA, for mp_verbose */ 89 90 #include <machine/cpufunc.h> 91 #include <machine/cpuvar.h> 92 #include <machine/pmap.h> 93 #include <machine/vmparam.h> 94 #if defined(MULTIPROCESSOR) 95 #include <machine/mpbiosvar.h> 96 #endif 97 #include <machine/mpconfig.h> /* for mp_verbose */ 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 #include <machine/cpu_counter.h> 105 106 #include <x86/fpu.h> 107 108 #ifdef i386 109 #include <machine/tlog.h> 110 #endif 111 112 #if NLAPIC > 0 113 #include <machine/apicvar.h> 114 #include <machine/i82489reg.h> 115 #include <machine/i82489var.h> 116 #endif 117 118 #include <dev/ic/mc146818reg.h> 119 #include <i386/isa/nvram.h> 120 #include <dev/isa/isareg.h> 121 122 #include "tsc.h" 123 124 static int cpu_match(device_t, cfdata_t, void *); 125 static void cpu_attach(device_t, device_t, void *); 126 static void cpu_defer(device_t); 127 static int cpu_rescan(device_t, const char *, const int *); 128 static void cpu_childdetached(device_t, device_t); 129 static bool cpu_stop(device_t); 130 static bool cpu_suspend(device_t, const pmf_qual_t *); 131 static bool cpu_resume(device_t, const pmf_qual_t *); 132 static bool cpu_shutdown(device_t, int); 133 134 struct cpu_softc { 135 device_t sc_dev; /* device tree glue */ 136 struct cpu_info *sc_info; /* pointer to CPU info */ 137 bool sc_wasonline; 138 }; 139 140 #ifdef MULTIPROCESSOR 141 int mp_cpu_start(struct cpu_info *, paddr_t); 142 void mp_cpu_start_cleanup(struct cpu_info *); 143 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 144 mp_cpu_start_cleanup }; 145 #endif 146 147 148 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 149 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 150 151 /* 152 * Statically-allocated CPU info for the primary CPU (or the only 153 * CPU, on uniprocessors). The CPU info list is initialized to 154 * point at it. 155 */ 156 #ifdef TRAPLOG 157 struct tlog tlog_primary; 158 #endif 159 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 160 .ci_dev = 0, 161 .ci_self = &cpu_info_primary, 162 .ci_idepth = -1, 163 .ci_curlwp = &lwp0, 164 .ci_curldt = -1, 165 #ifdef TRAPLOG 166 .ci_tlog_base = &tlog_primary, 167 #endif /* !TRAPLOG */ 168 }; 169 170 struct cpu_info *cpu_info_list = &cpu_info_primary; 171 172 static void cpu_set_tss_gates(struct cpu_info *); 173 174 #ifdef i386 175 static void tss_init(struct i386tss *, void *, void *); 176 #endif 177 178 static void cpu_init_idle_lwp(struct cpu_info *); 179 180 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 181 * [0] basic features %edx 182 * [1] basic features %ecx 183 * [2] extended features %edx 184 * [3] extended features %ecx 185 * [4] VIA padlock features 186 */ 187 188 extern char x86_64_doubleflt_stack[]; 189 190 #ifdef MULTIPROCESSOR 191 bool x86_mp_online; 192 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 193 #endif 194 #if NLAPIC > 0 195 static vaddr_t cmos_data_mapping; 196 #endif 197 struct cpu_info *cpu_starting; 198 199 #ifdef MULTIPROCESSOR 200 void cpu_hatch(void *); 201 static void cpu_boot_secondary(struct cpu_info *ci); 202 static void cpu_start_secondary(struct cpu_info *ci); 203 #endif 204 #if NLAPIC > 0 205 static void cpu_copy_trampoline(void); 206 #endif 207 208 /* 209 * Runs once per boot once multiprocessor goo has been detected and 210 * the local APIC on the boot processor has been mapped. 211 * 212 * Called from lapic_boot_init() (from mpbios_scan()). 213 */ 214 #if NLAPIC > 0 215 void 216 cpu_init_first(void) 217 { 218 219 cpu_info_primary.ci_cpuid = lapic_cpu_number(); 220 cpu_copy_trampoline(); 221 222 cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY); 223 if (cmos_data_mapping == 0) 224 panic("No KVA for page 0"); 225 pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE, 0); 226 pmap_update(pmap_kernel()); 227 } 228 #endif 229 230 static int 231 cpu_match(device_t parent, cfdata_t match, void *aux) 232 { 233 234 return 1; 235 } 236 237 static void 238 cpu_vm_init(struct cpu_info *ci) 239 { 240 int ncolors = 2, i; 241 242 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 243 struct x86_cache_info *cai; 244 int tcolors; 245 246 cai = &ci->ci_cinfo[i]; 247 248 tcolors = atop(cai->cai_totalsize); 249 switch(cai->cai_associativity) { 250 case 0xff: 251 tcolors = 1; /* fully associative */ 252 break; 253 case 0: 254 case 1: 255 break; 256 default: 257 tcolors /= cai->cai_associativity; 258 } 259 ncolors = max(ncolors, tcolors); 260 /* 261 * If the desired number of colors is not a power of 262 * two, it won't be good. Find the greatest power of 263 * two which is an even divisor of the number of colors, 264 * to preserve even coloring of pages. 265 */ 266 if (ncolors & (ncolors - 1) ) { 267 int try, picked = 1; 268 for (try = 1; try < ncolors; try *= 2) { 269 if (ncolors % try == 0) picked = try; 270 } 271 if (picked == 1) { 272 panic("desired number of cache colors %d is " 273 " > 1, but not even!", ncolors); 274 } 275 ncolors = picked; 276 } 277 } 278 279 /* 280 * Knowing the size of the largest cache on this CPU, potentially 281 * re-color our pages. 282 */ 283 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 284 uvm_page_recolor(ncolors); 285 286 pmap_tlb_cpu_init(ci); 287 } 288 289 static void 290 cpu_attach(device_t parent, device_t self, void *aux) 291 { 292 struct cpu_softc *sc = device_private(self); 293 struct cpu_attach_args *caa = aux; 294 struct cpu_info *ci; 295 uintptr_t ptr; 296 #if NLAPIC > 0 297 int cpunum = caa->cpu_number; 298 #endif 299 static bool again; 300 301 sc->sc_dev = self; 302 303 if (ncpu == maxcpus) { 304 #ifndef _LP64 305 aprint_error(": too many CPUs, please use NetBSD/amd64\n"); 306 #else 307 aprint_error(": too many CPUs\n"); 308 #endif 309 return; 310 } 311 312 /* 313 * If we're an Application Processor, allocate a cpu_info 314 * structure, otherwise use the primary's. 315 */ 316 if (caa->cpu_role == CPU_ROLE_AP) { 317 if ((boothowto & RB_MD1) != 0) { 318 aprint_error(": multiprocessor boot disabled\n"); 319 if (!pmf_device_register(self, NULL, NULL)) 320 aprint_error_dev(self, 321 "couldn't establish power handler\n"); 322 return; 323 } 324 aprint_naive(": Application Processor\n"); 325 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 326 KM_SLEEP); 327 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 328 ci->ci_curldt = -1; 329 #ifdef TRAPLOG 330 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 331 #endif 332 } else { 333 aprint_naive(": %s Processor\n", 334 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 335 ci = &cpu_info_primary; 336 #if NLAPIC > 0 337 if (cpunum != lapic_cpu_number()) { 338 /* XXX should be done earlier. */ 339 uint32_t reg; 340 aprint_verbose("\n"); 341 aprint_verbose_dev(self, "running CPU at apic %d" 342 " instead of at expected %d", lapic_cpu_number(), 343 cpunum); 344 reg = i82489_readreg(LAPIC_ID); 345 i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) | 346 (cpunum << LAPIC_ID_SHIFT)); 347 } 348 if (cpunum != lapic_cpu_number()) { 349 aprint_error_dev(self, "unable to reset apic id\n"); 350 } 351 #endif 352 } 353 354 ci->ci_self = ci; 355 sc->sc_info = ci; 356 ci->ci_dev = self; 357 ci->ci_acpiid = caa->cpu_id; 358 ci->ci_cpuid = caa->cpu_number; 359 ci->ci_func = caa->cpu_func; 360 aprint_normal("\n"); 361 362 /* Must be before mi_cpu_attach(). */ 363 cpu_vm_init(ci); 364 365 if (caa->cpu_role == CPU_ROLE_AP) { 366 int error; 367 368 error = mi_cpu_attach(ci); 369 if (error != 0) { 370 aprint_error_dev(self, 371 "mi_cpu_attach failed with %d\n", error); 372 return; 373 } 374 cpu_init_tss(ci); 375 } else { 376 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 377 } 378 379 pmap_reference(pmap_kernel()); 380 ci->ci_pmap = pmap_kernel(); 381 ci->ci_tlbstate = TLBSTATE_STALE; 382 383 /* 384 * Boot processor may not be attached first, but the below 385 * must be done to allow booting other processors. 386 */ 387 if (!again) { 388 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 389 /* Basic init. */ 390 cpu_intr_init(ci); 391 cpu_get_tsc_freq(ci); 392 cpu_init(ci); 393 cpu_set_tss_gates(ci); 394 pmap_cpu_init_late(ci); 395 #if NLAPIC > 0 396 if (caa->cpu_role != CPU_ROLE_SP) { 397 /* Enable lapic. */ 398 lapic_enable(); 399 lapic_set_lvt(); 400 lapic_calibrate_timer(ci); 401 } 402 #endif 403 /* Make sure DELAY() is initialized. */ 404 DELAY(1); 405 again = true; 406 } 407 408 /* further PCB init done later. */ 409 410 switch (caa->cpu_role) { 411 case CPU_ROLE_SP: 412 atomic_or_32(&ci->ci_flags, CPUF_SP); 413 cpu_identify(ci); 414 x86_errata(); 415 x86_cpu_idle_init(); 416 break; 417 418 case CPU_ROLE_BP: 419 atomic_or_32(&ci->ci_flags, CPUF_BSP); 420 cpu_identify(ci); 421 x86_errata(); 422 x86_cpu_idle_init(); 423 break; 424 425 #ifdef MULTIPROCESSOR 426 case CPU_ROLE_AP: 427 /* 428 * report on an AP 429 */ 430 cpu_intr_init(ci); 431 gdt_alloc_cpu(ci); 432 cpu_set_tss_gates(ci); 433 pmap_cpu_init_late(ci); 434 cpu_start_secondary(ci); 435 if (ci->ci_flags & CPUF_PRESENT) { 436 struct cpu_info *tmp; 437 438 cpu_identify(ci); 439 tmp = cpu_info_list; 440 while (tmp->ci_next) 441 tmp = tmp->ci_next; 442 443 tmp->ci_next = ci; 444 } 445 break; 446 #endif 447 448 default: 449 panic("unknown processor type??\n"); 450 } 451 452 pat_init(ci); 453 454 if (!pmf_device_register1(self, cpu_suspend, cpu_resume, cpu_shutdown)) 455 aprint_error_dev(self, "couldn't establish power handler\n"); 456 457 #ifdef MULTIPROCESSOR 458 if (mp_verbose) { 459 struct lwp *l = ci->ci_data.cpu_idlelwp; 460 struct pcb *pcb = lwp_getpcb(l); 461 462 aprint_verbose_dev(self, 463 "idle lwp at %p, idle sp at %p\n", 464 l, 465 #ifdef i386 466 (void *)pcb->pcb_esp 467 #else 468 (void *)pcb->pcb_rsp 469 #endif 470 ); 471 } 472 #endif 473 474 /* 475 * Postpone the "cpufeaturebus" scan. 476 * It is safe to scan the pseudo-bus 477 * only after all CPUs have attached. 478 */ 479 (void)config_defer(self, cpu_defer); 480 } 481 482 static void 483 cpu_defer(device_t self) 484 { 485 cpu_rescan(self, NULL, NULL); 486 } 487 488 static int 489 cpu_rescan(device_t self, const char *ifattr, const int *locators) 490 { 491 struct cpu_softc *sc = device_private(self); 492 struct cpufeature_attach_args cfaa; 493 struct cpu_info *ci = sc->sc_info; 494 495 memset(&cfaa, 0, sizeof(cfaa)); 496 cfaa.ci = ci; 497 498 if (ifattr_match(ifattr, "cpufeaturebus")) { 499 500 if (ci->ci_frequency == NULL) { 501 cfaa.name = "frequency"; 502 ci->ci_frequency = config_found_ia(self, 503 "cpufeaturebus", &cfaa, NULL); 504 } 505 506 if (ci->ci_padlock == NULL) { 507 cfaa.name = "padlock"; 508 ci->ci_padlock = config_found_ia(self, 509 "cpufeaturebus", &cfaa, NULL); 510 } 511 512 if (ci->ci_temperature == NULL) { 513 cfaa.name = "temperature"; 514 ci->ci_temperature = config_found_ia(self, 515 "cpufeaturebus", &cfaa, NULL); 516 } 517 518 if (ci->ci_vm == NULL) { 519 cfaa.name = "vm"; 520 ci->ci_vm = config_found_ia(self, 521 "cpufeaturebus", &cfaa, NULL); 522 } 523 } 524 525 return 0; 526 } 527 528 static void 529 cpu_childdetached(device_t self, device_t child) 530 { 531 struct cpu_softc *sc = device_private(self); 532 struct cpu_info *ci = sc->sc_info; 533 534 if (ci->ci_frequency == child) 535 ci->ci_frequency = NULL; 536 537 if (ci->ci_padlock == child) 538 ci->ci_padlock = NULL; 539 540 if (ci->ci_temperature == child) 541 ci->ci_temperature = NULL; 542 543 if (ci->ci_vm == child) 544 ci->ci_vm = NULL; 545 } 546 547 /* 548 * Initialize the processor appropriately. 549 */ 550 551 void 552 cpu_init(struct cpu_info *ci) 553 { 554 uint32_t cr4; 555 556 lcr0(rcr0() | CR0_WP); 557 558 cr4 = rcr4(); 559 /* 560 * On a P6 or above, enable global TLB caching if the 561 * hardware supports it. 562 */ 563 if (cpu_feature[0] & CPUID_PGE) 564 cr4 |= CR4_PGE; /* enable global TLB caching */ 565 566 /* 567 * If we have FXSAVE/FXRESTOR, use them. 568 */ 569 if (cpu_feature[0] & CPUID_FXSR) { 570 cr4 |= CR4_OSFXSR; 571 572 /* 573 * If we have SSE/SSE2, enable XMM exceptions. 574 */ 575 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 576 cr4 |= CR4_OSXMMEXCPT; 577 } 578 579 /* If xsave is supported, enable it */ 580 if (cpu_feature[1] & CPUID2_XSAVE) 581 cr4 |= CR4_OSXSAVE; 582 583 lcr4(cr4); 584 585 /* If xsave is enabled, enable all fpu features */ 586 if (cr4 & CR4_OSXSAVE) 587 wrxcr(0, x86_xsave_features & XCR0_FPU); 588 589 #ifdef MTRR 590 /* 591 * On a P6 or above, initialize MTRR's if the hardware supports them. 592 */ 593 if (cpu_feature[0] & CPUID_MTRR) { 594 if ((ci->ci_flags & CPUF_AP) == 0) 595 i686_mtrr_init_first(); 596 mtrr_init_cpu(ci); 597 } 598 599 #ifdef i386 600 if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) { 601 /* 602 * Must be a K6-2 Step >= 7 or a K6-III. 603 */ 604 if (CPUID_TO_FAMILY(ci->ci_signature) == 5) { 605 if (CPUID_TO_MODEL(ci->ci_signature) > 8 || 606 (CPUID_TO_MODEL(ci->ci_signature) == 8 && 607 CPUID_TO_STEPPING(ci->ci_signature) >= 7)) { 608 mtrr_funcs = &k6_mtrr_funcs; 609 k6_mtrr_init_first(); 610 mtrr_init_cpu(ci); 611 } 612 } 613 } 614 #endif /* i386 */ 615 #endif /* MTRR */ 616 617 if (ci != &cpu_info_primary) { 618 /* Synchronize TSC again, and check for drift. */ 619 wbinvd(); 620 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 621 tsc_sync_ap(ci); 622 } else { 623 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 624 } 625 } 626 627 #ifdef MULTIPROCESSOR 628 void 629 cpu_boot_secondary_processors(void) 630 { 631 struct cpu_info *ci; 632 kcpuset_t *cpus; 633 u_long i; 634 635 /* Now that we know the number of CPUs, patch the text segment. */ 636 x86_patch(false); 637 638 kcpuset_create(&cpus, true); 639 kcpuset_set(cpus, cpu_index(curcpu())); 640 for (i = 0; i < maxcpus; i++) { 641 ci = cpu_lookup(i); 642 if (ci == NULL) 643 continue; 644 if (ci->ci_data.cpu_idlelwp == NULL) 645 continue; 646 if ((ci->ci_flags & CPUF_PRESENT) == 0) 647 continue; 648 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 649 continue; 650 cpu_boot_secondary(ci); 651 kcpuset_set(cpus, cpu_index(ci)); 652 } 653 while (!kcpuset_match(cpus, kcpuset_running)) 654 ; 655 kcpuset_destroy(cpus); 656 657 x86_mp_online = true; 658 659 /* Now that we know about the TSC, attach the timecounter. */ 660 tsc_tc_init(); 661 662 /* Enable zeroing of pages in the idle loop if we have SSE2. */ 663 vm_page_zero_enable = ((cpu_feature[0] & CPUID_SSE2) != 0); 664 } 665 #endif 666 667 static void 668 cpu_init_idle_lwp(struct cpu_info *ci) 669 { 670 struct lwp *l = ci->ci_data.cpu_idlelwp; 671 struct pcb *pcb = lwp_getpcb(l); 672 673 pcb->pcb_cr0 = rcr0(); 674 } 675 676 void 677 cpu_init_idle_lwps(void) 678 { 679 struct cpu_info *ci; 680 u_long i; 681 682 for (i = 0; i < maxcpus; i++) { 683 ci = cpu_lookup(i); 684 if (ci == NULL) 685 continue; 686 if (ci->ci_data.cpu_idlelwp == NULL) 687 continue; 688 if ((ci->ci_flags & CPUF_PRESENT) == 0) 689 continue; 690 cpu_init_idle_lwp(ci); 691 } 692 } 693 694 #ifdef MULTIPROCESSOR 695 void 696 cpu_start_secondary(struct cpu_info *ci) 697 { 698 extern paddr_t mp_pdirpa; 699 u_long psl; 700 int i; 701 702 mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr); 703 atomic_or_32(&ci->ci_flags, CPUF_AP); 704 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 705 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) { 706 return; 707 } 708 709 /* 710 * Wait for it to become ready. Setting cpu_starting opens the 711 * initial gate and allows the AP to start soft initialization. 712 */ 713 KASSERT(cpu_starting == NULL); 714 cpu_starting = ci; 715 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 716 #ifdef MPDEBUG 717 extern int cpu_trace[3]; 718 static int otrace[3]; 719 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 720 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 721 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 722 memcpy(otrace, cpu_trace, sizeof(otrace)); 723 } 724 #endif 725 i8254_delay(10); 726 } 727 728 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 729 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 730 #if defined(MPDEBUG) && defined(DDB) 731 printf("dropping into debugger; continue from here to resume boot\n"); 732 Debugger(); 733 #endif 734 } else { 735 /* 736 * Synchronize time stamp counters. Invalidate cache and do 737 * twice to try and minimize possible cache effects. Disable 738 * interrupts to try and rule out any external interference. 739 */ 740 psl = x86_read_psl(); 741 x86_disable_intr(); 742 wbinvd(); 743 tsc_sync_bp(ci); 744 x86_write_psl(psl); 745 } 746 747 CPU_START_CLEANUP(ci); 748 cpu_starting = NULL; 749 } 750 751 void 752 cpu_boot_secondary(struct cpu_info *ci) 753 { 754 int64_t drift; 755 u_long psl; 756 int i; 757 758 atomic_or_32(&ci->ci_flags, CPUF_GO); 759 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 760 i8254_delay(10); 761 } 762 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 763 aprint_error_dev(ci->ci_dev, "failed to start\n"); 764 #if defined(MPDEBUG) && defined(DDB) 765 printf("dropping into debugger; continue from here to resume boot\n"); 766 Debugger(); 767 #endif 768 } else { 769 /* Synchronize TSC again, check for drift. */ 770 drift = ci->ci_data.cpu_cc_skew; 771 psl = x86_read_psl(); 772 x86_disable_intr(); 773 wbinvd(); 774 tsc_sync_bp(ci); 775 x86_write_psl(psl); 776 drift -= ci->ci_data.cpu_cc_skew; 777 aprint_debug_dev(ci->ci_dev, "TSC skew=%lld drift=%lld\n", 778 (long long)ci->ci_data.cpu_cc_skew, (long long)drift); 779 tsc_sync_drift(drift); 780 } 781 } 782 783 /* 784 * The CPU ends up here when its ready to run 785 * This is called from code in mptramp.s; at this point, we are running 786 * in the idle pcb/idle stack of the new CPU. When this function returns, 787 * this processor will enter the idle loop and start looking for work. 788 */ 789 void 790 cpu_hatch(void *v) 791 { 792 struct cpu_info *ci = (struct cpu_info *)v; 793 struct pcb *pcb; 794 int s, i; 795 796 cpu_init_msrs(ci, true); 797 cpu_probe(ci); 798 799 ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq; 800 /* cpu_get_tsc_freq(ci); */ 801 802 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 803 804 /* 805 * Synchronize time stamp counters. Invalidate cache and do twice 806 * to try and minimize possible cache effects. Note that interrupts 807 * are off at this point. 808 */ 809 wbinvd(); 810 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 811 tsc_sync_ap(ci); 812 813 /* 814 * Wait to be brought online. Use 'monitor/mwait' if available, 815 * in order to make the TSC drift as much as possible. so that 816 * we can detect it later. If not available, try 'pause'. 817 * We'd like to use 'hlt', but we have interrupts off. 818 */ 819 while ((ci->ci_flags & CPUF_GO) == 0) { 820 if ((cpu_feature[1] & CPUID2_MONITOR) != 0) { 821 x86_monitor(&ci->ci_flags, 0, 0); 822 if ((ci->ci_flags & CPUF_GO) != 0) { 823 continue; 824 } 825 x86_mwait(0, 0); 826 } else { 827 for (i = 10000; i != 0; i--) { 828 x86_pause(); 829 } 830 } 831 } 832 833 /* Because the text may have been patched in x86_patch(). */ 834 wbinvd(); 835 x86_flush(); 836 tlbflushg(); 837 838 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 839 840 #ifdef PAE 841 pd_entry_t * l3_pd = ci->ci_pae_l3_pdir; 842 for (i = 0 ; i < PDP_SIZE; i++) { 843 l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PG_V; 844 } 845 lcr3(ci->ci_pae_l3_pdirpa); 846 #else 847 lcr3(pmap_pdirpa(pmap_kernel(), 0)); 848 #endif 849 850 pcb = lwp_getpcb(curlwp); 851 pcb->pcb_cr3 = rcr3(); 852 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 853 lcr0(pcb->pcb_cr0); 854 855 cpu_init_idt(); 856 gdt_init_cpu(ci); 857 #if NLAPIC > 0 858 lapic_enable(); 859 lapic_set_lvt(); 860 lapic_initclocks(); 861 #endif 862 863 fpuinit(ci); 864 lldt(GSYSSEL(GLDT_SEL, SEL_KPL)); 865 ltr(ci->ci_tss_sel); 866 867 cpu_init(ci); 868 cpu_get_tsc_freq(ci); 869 870 s = splhigh(); 871 #ifdef i386 872 lapic_tpr = 0; 873 #else 874 lcr8(0); 875 #endif 876 x86_enable_intr(); 877 splx(s); 878 x86_errata(); 879 880 aprint_debug_dev(ci->ci_dev, "running\n"); 881 882 idle_loop(NULL); 883 KASSERT(false); 884 } 885 #endif 886 887 #if defined(DDB) 888 889 #include <ddb/db_output.h> 890 #include <machine/db_machdep.h> 891 892 /* 893 * Dump CPU information from ddb. 894 */ 895 void 896 cpu_debug_dump(void) 897 { 898 struct cpu_info *ci; 899 CPU_INFO_ITERATOR cii; 900 901 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 902 for (CPU_INFO_FOREACH(cii, ci)) { 903 db_printf("%p %s %ld %x %x %10p %10p\n", 904 ci, 905 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 906 (long)ci->ci_cpuid, 907 ci->ci_flags, ci->ci_ipis, 908 ci->ci_curlwp, 909 ci->ci_fpcurlwp); 910 } 911 } 912 #endif 913 914 #if NLAPIC > 0 915 static void 916 cpu_copy_trampoline(void) 917 { 918 /* 919 * Copy boot code. 920 */ 921 extern u_char cpu_spinup_trampoline[]; 922 extern u_char cpu_spinup_trampoline_end[]; 923 924 vaddr_t mp_trampoline_vaddr; 925 926 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 927 UVM_KMF_VAONLY); 928 929 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 930 VM_PROT_READ | VM_PROT_WRITE, 0); 931 pmap_update(pmap_kernel()); 932 memcpy((void *)mp_trampoline_vaddr, 933 cpu_spinup_trampoline, 934 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 935 936 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 937 pmap_update(pmap_kernel()); 938 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 939 } 940 #endif 941 942 #ifdef i386 943 static void 944 tss_init(struct i386tss *tss, void *stack, void *func) 945 { 946 KASSERT(curcpu()->ci_pmap == pmap_kernel()); 947 948 memset(tss, 0, sizeof *tss); 949 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 950 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 951 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 952 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 953 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 954 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 955 /* %cr3 contains the value associated to pmap_kernel */ 956 tss->tss_cr3 = rcr3(); 957 tss->tss_esp = (int)((char *)stack + USPACE - 16); 958 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 959 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 960 tss->__tss_eip = (int)func; 961 } 962 963 /* XXX */ 964 #define IDTVEC(name) __CONCAT(X, name) 965 typedef void (vector)(void); 966 extern vector IDTVEC(tss_trap08); 967 #if defined(DDB) && defined(MULTIPROCESSOR) 968 extern vector Xintrddbipi; 969 extern int ddb_vec; 970 #endif 971 972 static void 973 cpu_set_tss_gates(struct cpu_info *ci) 974 { 975 struct segment_descriptor sd; 976 977 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 978 UVM_KMF_WIRED); 979 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 980 IDTVEC(tss_trap08)); 981 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 982 SDT_SYS386TSS, SEL_KPL, 0, 0); 983 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 984 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 985 GSEL(GTRAPTSS_SEL, SEL_KPL)); 986 987 #if defined(DDB) && defined(MULTIPROCESSOR) 988 /* 989 * Set up separate handler for the DDB IPI, so that it doesn't 990 * stomp on a possibly corrupted stack. 991 * 992 * XXX overwriting the gate set in db_machine_init. 993 * Should rearrange the code so that it's set only once. 994 */ 995 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 996 UVM_KMF_WIRED); 997 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, Xintrddbipi); 998 999 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 1000 SDT_SYS386TSS, SEL_KPL, 0, 0); 1001 ci->ci_gdt[GIPITSS_SEL].sd = sd; 1002 1003 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 1004 GSEL(GIPITSS_SEL, SEL_KPL)); 1005 #endif 1006 } 1007 #else 1008 static void 1009 cpu_set_tss_gates(struct cpu_info *ci) 1010 { 1011 1012 } 1013 #endif /* i386 */ 1014 1015 #ifdef MULTIPROCESSOR 1016 int 1017 mp_cpu_start(struct cpu_info *ci, paddr_t target) 1018 { 1019 unsigned short dwordptr[2]; 1020 int error; 1021 1022 /* 1023 * Bootstrap code must be addressable in real mode 1024 * and it must be page aligned. 1025 */ 1026 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 1027 1028 /* 1029 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 1030 */ 1031 1032 outb(IO_RTC, NVRAM_RESET); 1033 outb(IO_RTC+1, NVRAM_RESET_JUMP); 1034 1035 /* 1036 * "and the warm reset vector (DWORD based at 40:67) to point 1037 * to the AP startup code ..." 1038 */ 1039 1040 dwordptr[0] = 0; 1041 dwordptr[1] = target >> 4; 1042 1043 #if NLAPIC > 0 1044 memcpy((uint8_t *)cmos_data_mapping + 0x467, dwordptr, 4); 1045 #endif 1046 1047 if ((cpu_feature[0] & CPUID_APIC) == 0) { 1048 aprint_error("mp_cpu_start: CPU does not have APIC\n"); 1049 return ENODEV; 1050 } 1051 1052 /* 1053 * ... prior to executing the following sequence:". We'll also add in 1054 * local cache flush, in case the BIOS has left the AP with its cache 1055 * disabled. It may not be able to cope with MP coherency. 1056 */ 1057 wbinvd(); 1058 1059 if (ci->ci_flags & CPUF_AP) { 1060 error = x86_ipi_init(ci->ci_cpuid); 1061 if (error != 0) { 1062 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 1063 __func__); 1064 return error; 1065 } 1066 i8254_delay(10000); 1067 1068 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1069 if (error != 0) { 1070 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 1071 __func__); 1072 return error; 1073 } 1074 i8254_delay(200); 1075 1076 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1077 if (error != 0) { 1078 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (3)\n", 1079 __func__); 1080 return error; 1081 } 1082 i8254_delay(200); 1083 } 1084 1085 return 0; 1086 } 1087 1088 void 1089 mp_cpu_start_cleanup(struct cpu_info *ci) 1090 { 1091 /* 1092 * Ensure the NVRAM reset byte contains something vaguely sane. 1093 */ 1094 1095 outb(IO_RTC, NVRAM_RESET); 1096 outb(IO_RTC+1, NVRAM_RESET_RST); 1097 } 1098 #endif 1099 1100 #ifdef __x86_64__ 1101 typedef void (vector)(void); 1102 extern vector Xsyscall, Xsyscall32; 1103 #endif 1104 1105 void 1106 cpu_init_msrs(struct cpu_info *ci, bool full) 1107 { 1108 #ifdef __x86_64__ 1109 wrmsr(MSR_STAR, 1110 ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1111 ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48)); 1112 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall); 1113 wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32); 1114 wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C); 1115 1116 if (full) { 1117 wrmsr(MSR_FSBASE, 0); 1118 wrmsr(MSR_GSBASE, (uint64_t)ci); 1119 wrmsr(MSR_KERNELGSBASE, 0); 1120 } 1121 #endif /* __x86_64__ */ 1122 1123 if (cpu_feature[2] & CPUID_NOX) 1124 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1125 } 1126 1127 void 1128 cpu_offline_md(void) 1129 { 1130 int s; 1131 1132 s = splhigh(); 1133 fpusave_cpu(true); 1134 splx(s); 1135 } 1136 1137 /* XXX joerg restructure and restart CPUs individually */ 1138 static bool 1139 cpu_stop(device_t dv) 1140 { 1141 struct cpu_softc *sc = device_private(dv); 1142 struct cpu_info *ci = sc->sc_info; 1143 int err; 1144 1145 KASSERT((ci->ci_flags & CPUF_PRESENT) != 0); 1146 1147 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1148 return true; 1149 1150 if (ci->ci_data.cpu_idlelwp == NULL) 1151 return true; 1152 1153 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1154 1155 if (sc->sc_wasonline) { 1156 mutex_enter(&cpu_lock); 1157 err = cpu_setstate(ci, false); 1158 mutex_exit(&cpu_lock); 1159 1160 if (err != 0) 1161 return false; 1162 } 1163 1164 return true; 1165 } 1166 1167 static bool 1168 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1169 { 1170 struct cpu_softc *sc = device_private(dv); 1171 struct cpu_info *ci = sc->sc_info; 1172 1173 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1174 return true; 1175 else { 1176 cpufreq_suspend(ci); 1177 } 1178 1179 return cpu_stop(dv); 1180 } 1181 1182 static bool 1183 cpu_resume(device_t dv, const pmf_qual_t *qual) 1184 { 1185 struct cpu_softc *sc = device_private(dv); 1186 struct cpu_info *ci = sc->sc_info; 1187 int err = 0; 1188 1189 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1190 return true; 1191 1192 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1193 goto out; 1194 1195 if (ci->ci_data.cpu_idlelwp == NULL) 1196 goto out; 1197 1198 if (sc->sc_wasonline) { 1199 mutex_enter(&cpu_lock); 1200 err = cpu_setstate(ci, true); 1201 mutex_exit(&cpu_lock); 1202 } 1203 1204 out: 1205 if (err != 0) 1206 return false; 1207 1208 cpufreq_resume(ci); 1209 1210 return true; 1211 } 1212 1213 static bool 1214 cpu_shutdown(device_t dv, int how) 1215 { 1216 struct cpu_softc *sc = device_private(dv); 1217 struct cpu_info *ci = sc->sc_info; 1218 1219 if ((ci->ci_flags & CPUF_BSP) != 0) 1220 return false; 1221 1222 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1223 return true; 1224 1225 return cpu_stop(dv); 1226 } 1227 1228 void 1229 cpu_get_tsc_freq(struct cpu_info *ci) 1230 { 1231 uint64_t last_tsc; 1232 1233 if (cpu_hascounter()) { 1234 last_tsc = cpu_counter_serializing(); 1235 i8254_delay(100000); 1236 ci->ci_data.cpu_cc_freq = 1237 (cpu_counter_serializing() - last_tsc) * 10; 1238 } 1239 } 1240 1241 void 1242 x86_cpu_idle_mwait(void) 1243 { 1244 struct cpu_info *ci = curcpu(); 1245 1246 KASSERT(ci->ci_ilevel == IPL_NONE); 1247 1248 x86_monitor(&ci->ci_want_resched, 0, 0); 1249 if (__predict_false(ci->ci_want_resched)) { 1250 return; 1251 } 1252 x86_mwait(0, 0); 1253 } 1254 1255 void 1256 x86_cpu_idle_halt(void) 1257 { 1258 struct cpu_info *ci = curcpu(); 1259 1260 KASSERT(ci->ci_ilevel == IPL_NONE); 1261 1262 x86_disable_intr(); 1263 if (!__predict_false(ci->ci_want_resched)) { 1264 x86_stihlt(); 1265 } else { 1266 x86_enable_intr(); 1267 } 1268 } 1269 1270 /* 1271 * Loads pmap for the current CPU. 1272 */ 1273 void 1274 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1275 { 1276 #ifdef PAE 1277 struct cpu_info *ci = curcpu(); 1278 pd_entry_t *l3_pd = ci->ci_pae_l3_pdir; 1279 int i; 1280 1281 /* 1282 * disable interrupts to block TLB shootdowns, which can reload cr3. 1283 * while this doesn't block NMIs, it's probably ok as NMIs unlikely 1284 * reload cr3. 1285 */ 1286 x86_disable_intr(); 1287 for (i = 0 ; i < PDP_SIZE; i++) { 1288 l3_pd[i] = pmap->pm_pdirpa[i] | PG_V; 1289 } 1290 x86_enable_intr(); 1291 tlbflush(); 1292 #else /* PAE */ 1293 lcr3(pmap_pdirpa(pmap, 0)); 1294 #endif /* PAE */ 1295 } 1296 1297 /* 1298 * Notify all other cpus to halt. 1299 */ 1300 1301 void 1302 cpu_broadcast_halt(void) 1303 { 1304 x86_broadcast_ipi(X86_IPI_HALT); 1305 } 1306 1307 /* 1308 * Send a dummy ipi to a cpu to force it to run splraise()/spllower() 1309 */ 1310 1311 void 1312 cpu_kick(struct cpu_info *ci) 1313 { 1314 x86_send_ipi(ci, 0); 1315 } 1316
Indexes created Mon Sep 22 13:09:51 GMT 2025