cpu.c revision 1.116
1 /* $NetBSD: cpu.c,v 1.116 2015/09/17 23:48:01 nat Exp $ */ 2 3 /*- 4 * Copyright (c) 2000-2012 NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999 Stefan Grefen 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by the NetBSD 46 * Foundation, Inc. and its contributors. 47 * 4. Neither the name of The NetBSD Foundation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.116 2015/09/17 23:48:01 nat Exp $"); 66 67 #include "opt_ddb.h" 68 #include "opt_mpbios.h" /* for MPDEBUG */ 69 #include "opt_mtrr.h" 70 #include "opt_multiprocessor.h" 71 72 #include "lapic.h" 73 #include "ioapic.h" 74 75 #include <sys/param.h> 76 #include <sys/proc.h> 77 #include <sys/systm.h> 78 #include <sys/device.h> 79 #include <sys/kmem.h> 80 #include <sys/cpu.h> 81 #include <sys/cpufreq.h> 82 #include <sys/idle.h> 83 #include <sys/atomic.h> 84 #include <sys/reboot.h> 85 86 #include <uvm/uvm.h> 87 88 #include "acpica.h" /* for NACPICA, for mp_verbose */ 89 90 #include <machine/cpufunc.h> 91 #include <machine/cpuvar.h> 92 #include <machine/pmap.h> 93 #include <machine/vmparam.h> 94 #if defined(MULTIPROCESSOR) 95 #include <machine/mpbiosvar.h> 96 #endif 97 #include <machine/mpconfig.h> /* for mp_verbose */ 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 #include <machine/cpu_counter.h> 105 106 #include <x86/fpu.h> 107 108 #ifdef i386 109 #include <machine/tlog.h> 110 #endif 111 112 #if NLAPIC > 0 113 #include <machine/apicvar.h> 114 #include <machine/i82489reg.h> 115 #include <machine/i82489var.h> 116 #endif 117 118 #include <dev/ic/mc146818reg.h> 119 #include <i386/isa/nvram.h> 120 #include <dev/isa/isareg.h> 121 122 #include "tsc.h" 123 124 static int cpu_match(device_t, cfdata_t, void *); 125 static void cpu_attach(device_t, device_t, void *); 126 static void cpu_defer(device_t); 127 static int cpu_rescan(device_t, const char *, const int *); 128 static void cpu_childdetached(device_t, device_t); 129 static bool cpu_stop(device_t); 130 static bool cpu_suspend(device_t, const pmf_qual_t *); 131 static bool cpu_resume(device_t, const pmf_qual_t *); 132 static bool cpu_shutdown(device_t, int); 133 134 struct cpu_softc { 135 device_t sc_dev; /* device tree glue */ 136 struct cpu_info *sc_info; /* pointer to CPU info */ 137 bool sc_wasonline; 138 }; 139 140 #ifdef MULTIPROCESSOR 141 int mp_cpu_start(struct cpu_info *, paddr_t); 142 void mp_cpu_start_cleanup(struct cpu_info *); 143 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 144 mp_cpu_start_cleanup }; 145 #endif 146 147 148 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 149 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 150 151 /* 152 * Statically-allocated CPU info for the primary CPU (or the only 153 * CPU, on uniprocessors). The CPU info list is initialized to 154 * point at it. 155 */ 156 #ifdef TRAPLOG 157 struct tlog tlog_primary; 158 #endif 159 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 160 .ci_dev = 0, 161 .ci_self = &cpu_info_primary, 162 .ci_idepth = -1, 163 .ci_curlwp = &lwp0, 164 .ci_curldt = -1, 165 #ifdef TRAPLOG 166 .ci_tlog_base = &tlog_primary, 167 #endif /* !TRAPLOG */ 168 }; 169 170 struct cpu_info *cpu_info_list = &cpu_info_primary; 171 172 static void cpu_set_tss_gates(struct cpu_info *); 173 174 #ifdef i386 175 static void tss_init(struct i386tss *, void *, void *); 176 #endif 177 178 static void cpu_init_idle_lwp(struct cpu_info *); 179 180 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 181 * [0] basic features %edx 182 * [1] basic features %ecx 183 * [2] extended features %edx 184 * [3] extended features %ecx 185 * [4] VIA padlock features 186 */ 187 188 extern char x86_64_doubleflt_stack[]; 189 190 #ifdef MULTIPROCESSOR 191 bool x86_mp_online; 192 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 193 #endif 194 #if NLAPIC > 0 195 static vaddr_t cmos_data_mapping; 196 #endif 197 struct cpu_info *cpu_starting; 198 199 #ifdef MULTIPROCESSOR 200 void cpu_hatch(void *); 201 static void cpu_boot_secondary(struct cpu_info *ci); 202 static void cpu_start_secondary(struct cpu_info *ci); 203 #endif 204 #if NLAPIC > 0 205 static void cpu_copy_trampoline(void); 206 #endif 207 208 /* 209 * Runs once per boot once multiprocessor goo has been detected and 210 * the local APIC on the boot processor has been mapped. 211 * 212 * Called from lapic_boot_init() (from mpbios_scan()). 213 */ 214 #if NLAPIC > 0 215 void 216 cpu_init_first(void) 217 { 218 219 cpu_info_primary.ci_cpuid = lapic_cpu_number(); 220 cpu_copy_trampoline(); 221 222 cmos_data_mapping = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, UVM_KMF_VAONLY); 223 if (cmos_data_mapping == 0) 224 panic("No KVA for page 0"); 225 pmap_kenter_pa(cmos_data_mapping, 0, VM_PROT_READ|VM_PROT_WRITE, 0); 226 pmap_update(pmap_kernel()); 227 } 228 #endif 229 230 static int 231 cpu_match(device_t parent, cfdata_t match, void *aux) 232 { 233 234 return 1; 235 } 236 237 static void 238 cpu_vm_init(struct cpu_info *ci) 239 { 240 int ncolors = 2, i; 241 242 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 243 struct x86_cache_info *cai; 244 int tcolors; 245 246 cai = &ci->ci_cinfo[i]; 247 248 tcolors = atop(cai->cai_totalsize); 249 switch(cai->cai_associativity) { 250 case 0xff: 251 tcolors = 1; /* fully associative */ 252 break; 253 case 0: 254 case 1: 255 break; 256 default: 257 tcolors /= cai->cai_associativity; 258 } 259 ncolors = max(ncolors, tcolors); 260 /* 261 * If the desired number of colors is not a power of 262 * two, it won't be good. Find the greatest power of 263 * two which is an even divisor of the number of colors, 264 * to preserve even coloring of pages. 265 */ 266 if (ncolors & (ncolors - 1) ) { 267 int try, picked = 1; 268 for (try = 1; try < ncolors; try *= 2) { 269 if (ncolors % try == 0) picked = try; 270 } 271 if (picked == 1) { 272 panic("desired number of cache colors %d is " 273 " > 1, but not even!", ncolors); 274 } 275 ncolors = picked; 276 } 277 } 278 279 /* 280 * Knowing the size of the largest cache on this CPU, potentially 281 * re-color our pages. 282 */ 283 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 284 uvm_page_recolor(ncolors); 285 286 pmap_tlb_cpu_init(ci); 287 } 288 289 static void 290 cpu_attach(device_t parent, device_t self, void *aux) 291 { 292 struct cpu_softc *sc = device_private(self); 293 struct cpu_attach_args *caa = aux; 294 struct cpu_info *ci; 295 uintptr_t ptr; 296 #if NLAPIC > 0 297 int cpunum = caa->cpu_number; 298 #endif 299 static bool again; 300 301 sc->sc_dev = self; 302 303 if (ncpu == maxcpus) { 304 #ifndef _LP64 305 aprint_error(": too many CPUs, please use NetBSD/amd64\n"); 306 #else 307 aprint_error(": too many CPUs\n"); 308 #endif 309 return; 310 } 311 312 /* 313 * If we're an Application Processor, allocate a cpu_info 314 * structure, otherwise use the primary's. 315 */ 316 if (caa->cpu_role == CPU_ROLE_AP) { 317 if ((boothowto & RB_MD1) != 0) { 318 aprint_error(": multiprocessor boot disabled\n"); 319 if (!pmf_device_register(self, NULL, NULL)) 320 aprint_error_dev(self, 321 "couldn't establish power handler\n"); 322 return; 323 } 324 aprint_naive(": Application Processor\n"); 325 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 326 KM_SLEEP); 327 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 328 ci->ci_curldt = -1; 329 #ifdef TRAPLOG 330 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 331 #endif 332 } else { 333 aprint_naive(": %s Processor\n", 334 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 335 ci = &cpu_info_primary; 336 #if NLAPIC > 0 337 if (cpunum != lapic_cpu_number()) { 338 /* XXX should be done earlier. */ 339 uint32_t reg; 340 aprint_verbose("\n"); 341 aprint_verbose_dev(self, "running CPU at apic %d" 342 " instead of at expected %d", lapic_cpu_number(), 343 cpunum); 344 reg = i82489_readreg(LAPIC_ID); 345 i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) | 346 (cpunum << LAPIC_ID_SHIFT)); 347 } 348 if (cpunum != lapic_cpu_number()) { 349 aprint_error_dev(self, "unable to reset apic id\n"); 350 } 351 #endif 352 } 353 354 ci->ci_self = ci; 355 sc->sc_info = ci; 356 ci->ci_dev = self; 357 ci->ci_acpiid = caa->cpu_id; 358 ci->ci_cpuid = caa->cpu_number; 359 ci->ci_func = caa->cpu_func; 360 aprint_normal("\n"); 361 362 /* Must be before mi_cpu_attach(). */ 363 cpu_vm_init(ci); 364 365 if (caa->cpu_role == CPU_ROLE_AP) { 366 int error; 367 368 error = mi_cpu_attach(ci); 369 if (error != 0) { 370 aprint_error_dev(self, 371 "mi_cpu_attach failed with %d\n", error); 372 return; 373 } 374 cpu_init_tss(ci); 375 } else { 376 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 377 } 378 379 pmap_reference(pmap_kernel()); 380 ci->ci_pmap = pmap_kernel(); 381 ci->ci_tlbstate = TLBSTATE_STALE; 382 383 /* 384 * Boot processor may not be attached first, but the below 385 * must be done to allow booting other processors. 386 */ 387 if (!again) { 388 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 389 /* Basic init. */ 390 cpu_intr_init(ci); 391 cpu_get_tsc_freq(ci); 392 cpu_init(ci); 393 cpu_set_tss_gates(ci); 394 pmap_cpu_init_late(ci); 395 #if NLAPIC > 0 396 if (caa->cpu_role != CPU_ROLE_SP) { 397 /* Enable lapic. */ 398 lapic_enable(); 399 lapic_set_lvt(); 400 lapic_calibrate_timer(ci); 401 } 402 #endif 403 /* Make sure DELAY() is initialized. */ 404 DELAY(1); 405 again = true; 406 } 407 408 /* further PCB init done later. */ 409 410 switch (caa->cpu_role) { 411 case CPU_ROLE_SP: 412 atomic_or_32(&ci->ci_flags, CPUF_SP); 413 cpu_identify(ci); 414 x86_errata(); 415 x86_cpu_idle_init(); 416 break; 417 418 case CPU_ROLE_BP: 419 atomic_or_32(&ci->ci_flags, CPUF_BSP); 420 cpu_identify(ci); 421 x86_errata(); 422 x86_cpu_idle_init(); 423 break; 424 425 #ifdef MULTIPROCESSOR 426 case CPU_ROLE_AP: 427 /* 428 * report on an AP 429 */ 430 cpu_intr_init(ci); 431 gdt_alloc_cpu(ci); 432 cpu_set_tss_gates(ci); 433 pmap_cpu_init_late(ci); 434 cpu_start_secondary(ci); 435 if (ci->ci_flags & CPUF_PRESENT) { 436 struct cpu_info *tmp; 437 438 cpu_identify(ci); 439 tmp = cpu_info_list; 440 while (tmp->ci_next) 441 tmp = tmp->ci_next; 442 443 tmp->ci_next = ci; 444 } 445 break; 446 #endif 447 448 default: 449 panic("unknown processor type??\n"); 450 } 451 452 pat_init(ci); 453 454 if (!pmf_device_register1(self, cpu_suspend, cpu_resume, cpu_shutdown)) 455 aprint_error_dev(self, "couldn't establish power handler\n"); 456 457 #ifdef MULTIPROCESSOR 458 if (mp_verbose) { 459 struct lwp *l = ci->ci_data.cpu_idlelwp; 460 struct pcb *pcb = lwp_getpcb(l); 461 462 aprint_verbose_dev(self, 463 "idle lwp at %p, idle sp at %p\n", 464 l, 465 #ifdef i386 466 (void *)pcb->pcb_esp 467 #else 468 (void *)pcb->pcb_rsp 469 #endif 470 ); 471 } 472 #endif 473 474 /* 475 * Postpone the "cpufeaturebus" scan. 476 * It is safe to scan the pseudo-bus 477 * only after all CPUs have attached. 478 */ 479 (void)config_defer(self, cpu_defer); 480 } 481 482 static void 483 cpu_defer(device_t self) 484 { 485 cpu_rescan(self, NULL, NULL); 486 } 487 488 static int 489 cpu_rescan(device_t self, const char *ifattr, const int *locators) 490 { 491 struct cpu_softc *sc = device_private(self); 492 struct cpufeature_attach_args cfaa; 493 struct cpu_info *ci = sc->sc_info; 494 495 memset(&cfaa, 0, sizeof(cfaa)); 496 cfaa.ci = ci; 497 498 if (ifattr_match(ifattr, "cpufeaturebus")) { 499 500 if (ci->ci_frequency == NULL) { 501 cfaa.name = "frequency"; 502 ci->ci_frequency = config_found_ia(self, 503 "cpufeaturebus", &cfaa, NULL); 504 } 505 506 if (ci->ci_padlock == NULL) { 507 cfaa.name = "padlock"; 508 ci->ci_padlock = config_found_ia(self, 509 "cpufeaturebus", &cfaa, NULL); 510 } 511 512 if (ci->ci_temperature == NULL) { 513 cfaa.name = "temperature"; 514 ci->ci_temperature = config_found_ia(self, 515 "cpufeaturebus", &cfaa, NULL); 516 } 517 518 if (ci->ci_vm == NULL) { 519 cfaa.name = "vm"; 520 ci->ci_vm = config_found_ia(self, 521 "cpufeaturebus", &cfaa, NULL); 522 } 523 } 524 525 return 0; 526 } 527 528 static void 529 cpu_childdetached(device_t self, device_t child) 530 { 531 struct cpu_softc *sc = device_private(self); 532 struct cpu_info *ci = sc->sc_info; 533 534 if (ci->ci_frequency == child) 535 ci->ci_frequency = NULL; 536 537 if (ci->ci_padlock == child) 538 ci->ci_padlock = NULL; 539 540 if (ci->ci_temperature == child) 541 ci->ci_temperature = NULL; 542 543 if (ci->ci_vm == child) 544 ci->ci_vm = NULL; 545 } 546 547 /* 548 * Initialize the processor appropriately. 549 */ 550 551 void 552 cpu_init(struct cpu_info *ci) 553 { 554 uint32_t cr4 = 0; 555 556 lcr0(rcr0() | CR0_WP); 557 558 /* 559 * On a P6 or above, enable global TLB caching if the 560 * hardware supports it. 561 */ 562 if (cpu_feature[0] & CPUID_PGE) 563 cr4 |= CR4_PGE; /* enable global TLB caching */ 564 565 /* 566 * If we have FXSAVE/FXRESTOR, use them. 567 */ 568 if (cpu_feature[0] & CPUID_FXSR) { 569 cr4 |= CR4_OSFXSR; 570 571 /* 572 * If we have SSE/SSE2, enable XMM exceptions. 573 */ 574 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 575 cr4 |= CR4_OSXMMEXCPT; 576 } 577 578 /* If xsave is supported, enable it */ 579 if (cpu_feature[1] & CPUID2_XSAVE) 580 cr4 |= CR4_OSXSAVE; 581 582 if (cr4) { 583 cr4 |= rcr4(); 584 lcr4(cr4); 585 } 586 587 /* If xsave is enabled, enable all fpu features */ 588 if (cr4 & CR4_OSXSAVE) 589 wrxcr(0, x86_xsave_features & XCR0_FPU); 590 591 #ifdef MTRR 592 /* 593 * On a P6 or above, initialize MTRR's if the hardware supports them. 594 */ 595 if (cpu_feature[0] & CPUID_MTRR) { 596 if ((ci->ci_flags & CPUF_AP) == 0) 597 i686_mtrr_init_first(); 598 mtrr_init_cpu(ci); 599 } 600 601 #ifdef i386 602 if (strcmp((char *)(ci->ci_vendor), "AuthenticAMD") == 0) { 603 /* 604 * Must be a K6-2 Step >= 7 or a K6-III. 605 */ 606 if (CPUID_TO_FAMILY(ci->ci_signature) == 5) { 607 if (CPUID_TO_MODEL(ci->ci_signature) > 8 || 608 (CPUID_TO_MODEL(ci->ci_signature) == 8 && 609 CPUID_TO_STEPPING(ci->ci_signature) >= 7)) { 610 mtrr_funcs = &k6_mtrr_funcs; 611 k6_mtrr_init_first(); 612 mtrr_init_cpu(ci); 613 } 614 } 615 } 616 #endif /* i386 */ 617 #endif /* MTRR */ 618 619 if (ci != &cpu_info_primary) { 620 /* Synchronize TSC again, and check for drift. */ 621 wbinvd(); 622 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 623 tsc_sync_ap(ci); 624 } else { 625 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 626 } 627 } 628 629 #ifdef MULTIPROCESSOR 630 void 631 cpu_boot_secondary_processors(void) 632 { 633 struct cpu_info *ci; 634 kcpuset_t *cpus; 635 u_long i; 636 637 /* Now that we know the number of CPUs, patch the text segment. */ 638 x86_patch(false); 639 640 kcpuset_create(&cpus, true); 641 kcpuset_set(cpus, cpu_index(curcpu())); 642 for (i = 0; i < maxcpus; i++) { 643 ci = cpu_lookup(i); 644 if (ci == NULL) 645 continue; 646 if (ci->ci_data.cpu_idlelwp == NULL) 647 continue; 648 if ((ci->ci_flags & CPUF_PRESENT) == 0) 649 continue; 650 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 651 continue; 652 cpu_boot_secondary(ci); 653 kcpuset_set(cpus, cpu_index(ci)); 654 } 655 while (!kcpuset_match(cpus, kcpuset_running)) 656 ; 657 kcpuset_destroy(cpus); 658 659 x86_mp_online = true; 660 661 /* Now that we know about the TSC, attach the timecounter. */ 662 tsc_tc_init(); 663 664 /* Enable zeroing of pages in the idle loop if we have SSE2. */ 665 vm_page_zero_enable = ((cpu_feature[0] & CPUID_SSE2) != 0); 666 } 667 #endif 668 669 static void 670 cpu_init_idle_lwp(struct cpu_info *ci) 671 { 672 struct lwp *l = ci->ci_data.cpu_idlelwp; 673 struct pcb *pcb = lwp_getpcb(l); 674 675 pcb->pcb_cr0 = rcr0(); 676 } 677 678 void 679 cpu_init_idle_lwps(void) 680 { 681 struct cpu_info *ci; 682 u_long i; 683 684 for (i = 0; i < maxcpus; i++) { 685 ci = cpu_lookup(i); 686 if (ci == NULL) 687 continue; 688 if (ci->ci_data.cpu_idlelwp == NULL) 689 continue; 690 if ((ci->ci_flags & CPUF_PRESENT) == 0) 691 continue; 692 cpu_init_idle_lwp(ci); 693 } 694 } 695 696 #ifdef MULTIPROCESSOR 697 void 698 cpu_start_secondary(struct cpu_info *ci) 699 { 700 extern paddr_t mp_pdirpa; 701 u_long psl; 702 int i; 703 704 mp_pdirpa = pmap_init_tmp_pgtbl(mp_trampoline_paddr); 705 atomic_or_32(&ci->ci_flags, CPUF_AP); 706 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 707 if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0) { 708 return; 709 } 710 711 /* 712 * Wait for it to become ready. Setting cpu_starting opens the 713 * initial gate and allows the AP to start soft initialization. 714 */ 715 KASSERT(cpu_starting == NULL); 716 cpu_starting = ci; 717 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 718 #ifdef MPDEBUG 719 extern int cpu_trace[3]; 720 static int otrace[3]; 721 if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) { 722 aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n", 723 cpu_trace[0], cpu_trace[1], cpu_trace[2]); 724 memcpy(otrace, cpu_trace, sizeof(otrace)); 725 } 726 #endif 727 i8254_delay(10); 728 } 729 730 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 731 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 732 #if defined(MPDEBUG) && defined(DDB) 733 printf("dropping into debugger; continue from here to resume boot\n"); 734 Debugger(); 735 #endif 736 } else { 737 /* 738 * Synchronize time stamp counters. Invalidate cache and do 739 * twice to try and minimize possible cache effects. Disable 740 * interrupts to try and rule out any external interference. 741 */ 742 psl = x86_read_psl(); 743 x86_disable_intr(); 744 wbinvd(); 745 tsc_sync_bp(ci); 746 x86_write_psl(psl); 747 } 748 749 CPU_START_CLEANUP(ci); 750 cpu_starting = NULL; 751 } 752 753 void 754 cpu_boot_secondary(struct cpu_info *ci) 755 { 756 int64_t drift; 757 u_long psl; 758 int i; 759 760 atomic_or_32(&ci->ci_flags, CPUF_GO); 761 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 762 i8254_delay(10); 763 } 764 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 765 aprint_error_dev(ci->ci_dev, "failed to start\n"); 766 #if defined(MPDEBUG) && defined(DDB) 767 printf("dropping into debugger; continue from here to resume boot\n"); 768 Debugger(); 769 #endif 770 } else { 771 /* Synchronize TSC again, check for drift. */ 772 drift = ci->ci_data.cpu_cc_skew; 773 psl = x86_read_psl(); 774 x86_disable_intr(); 775 wbinvd(); 776 tsc_sync_bp(ci); 777 x86_write_psl(psl); 778 drift -= ci->ci_data.cpu_cc_skew; 779 aprint_debug_dev(ci->ci_dev, "TSC skew=%lld drift=%lld\n", 780 (long long)ci->ci_data.cpu_cc_skew, (long long)drift); 781 tsc_sync_drift(drift); 782 } 783 } 784 785 /* 786 * The CPU ends up here when its ready to run 787 * This is called from code in mptramp.s; at this point, we are running 788 * in the idle pcb/idle stack of the new CPU. When this function returns, 789 * this processor will enter the idle loop and start looking for work. 790 */ 791 void 792 cpu_hatch(void *v) 793 { 794 struct cpu_info *ci = (struct cpu_info *)v; 795 struct pcb *pcb; 796 int s, i; 797 798 cpu_init_msrs(ci, true); 799 cpu_probe(ci); 800 801 ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq; 802 /* cpu_get_tsc_freq(ci); */ 803 804 KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0); 805 806 /* 807 * Synchronize time stamp counters. Invalidate cache and do twice 808 * to try and minimize possible cache effects. Note that interrupts 809 * are off at this point. 810 */ 811 wbinvd(); 812 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 813 tsc_sync_ap(ci); 814 815 /* 816 * Wait to be brought online. Use 'monitor/mwait' if available, 817 * in order to make the TSC drift as much as possible. so that 818 * we can detect it later. If not available, try 'pause'. 819 * We'd like to use 'hlt', but we have interrupts off. 820 */ 821 while ((ci->ci_flags & CPUF_GO) == 0) { 822 if ((cpu_feature[1] & CPUID2_MONITOR) != 0) { 823 x86_monitor(&ci->ci_flags, 0, 0); 824 if ((ci->ci_flags & CPUF_GO) != 0) { 825 continue; 826 } 827 x86_mwait(0, 0); 828 } else { 829 for (i = 10000; i != 0; i--) { 830 x86_pause(); 831 } 832 } 833 } 834 835 /* Because the text may have been patched in x86_patch(). */ 836 wbinvd(); 837 x86_flush(); 838 tlbflushg(); 839 840 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 841 842 #ifdef PAE 843 pd_entry_t * l3_pd = ci->ci_pae_l3_pdir; 844 for (i = 0 ; i < PDP_SIZE; i++) { 845 l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PG_V; 846 } 847 lcr3(ci->ci_pae_l3_pdirpa); 848 #else 849 lcr3(pmap_pdirpa(pmap_kernel(), 0)); 850 #endif 851 852 pcb = lwp_getpcb(curlwp); 853 pcb->pcb_cr3 = rcr3(); 854 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 855 lcr0(pcb->pcb_cr0); 856 857 cpu_init_idt(); 858 gdt_init_cpu(ci); 859 #if NLAPIC > 0 860 lapic_enable(); 861 lapic_set_lvt(); 862 lapic_initclocks(); 863 #endif 864 865 fpuinit(ci); 866 lldt(GSYSSEL(GLDT_SEL, SEL_KPL)); 867 ltr(ci->ci_tss_sel); 868 869 cpu_init(ci); 870 cpu_get_tsc_freq(ci); 871 872 s = splhigh(); 873 #ifdef i386 874 lapic_tpr = 0; 875 #else 876 lcr8(0); 877 #endif 878 x86_enable_intr(); 879 splx(s); 880 x86_errata(); 881 882 aprint_debug_dev(ci->ci_dev, "running\n"); 883 884 idle_loop(NULL); 885 KASSERT(false); 886 } 887 #endif 888 889 #if defined(DDB) 890 891 #include <ddb/db_output.h> 892 #include <machine/db_machdep.h> 893 894 /* 895 * Dump CPU information from ddb. 896 */ 897 void 898 cpu_debug_dump(void) 899 { 900 struct cpu_info *ci; 901 CPU_INFO_ITERATOR cii; 902 903 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 904 for (CPU_INFO_FOREACH(cii, ci)) { 905 db_printf("%p %s %ld %x %x %10p %10p\n", 906 ci, 907 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 908 (long)ci->ci_cpuid, 909 ci->ci_flags, ci->ci_ipis, 910 ci->ci_curlwp, 911 ci->ci_fpcurlwp); 912 } 913 } 914 #endif 915 916 #if NLAPIC > 0 917 static void 918 cpu_copy_trampoline(void) 919 { 920 /* 921 * Copy boot code. 922 */ 923 extern u_char cpu_spinup_trampoline[]; 924 extern u_char cpu_spinup_trampoline_end[]; 925 926 vaddr_t mp_trampoline_vaddr; 927 928 mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 929 UVM_KMF_VAONLY); 930 931 pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr, 932 VM_PROT_READ | VM_PROT_WRITE, 0); 933 pmap_update(pmap_kernel()); 934 memcpy((void *)mp_trampoline_vaddr, 935 cpu_spinup_trampoline, 936 cpu_spinup_trampoline_end - cpu_spinup_trampoline); 937 938 pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE); 939 pmap_update(pmap_kernel()); 940 uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY); 941 } 942 #endif 943 944 #ifdef i386 945 static void 946 tss_init(struct i386tss *tss, void *stack, void *func) 947 { 948 KASSERT(curcpu()->ci_pmap == pmap_kernel()); 949 950 memset(tss, 0, sizeof *tss); 951 tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16); 952 tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 953 tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL); 954 tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL); 955 tss->tss_gs = tss->__tss_es = tss->__tss_ds = 956 tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL); 957 /* %cr3 contains the value associated to pmap_kernel */ 958 tss->tss_cr3 = rcr3(); 959 tss->tss_esp = (int)((char *)stack + USPACE - 16); 960 tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL); 961 tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */ 962 tss->__tss_eip = (int)func; 963 } 964 965 /* XXX */ 966 #define IDTVEC(name) __CONCAT(X, name) 967 typedef void (vector)(void); 968 extern vector IDTVEC(tss_trap08); 969 #if defined(DDB) && defined(MULTIPROCESSOR) 970 extern vector Xintrddbipi; 971 extern int ddb_vec; 972 #endif 973 974 static void 975 cpu_set_tss_gates(struct cpu_info *ci) 976 { 977 struct segment_descriptor sd; 978 979 ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 980 UVM_KMF_WIRED); 981 tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack, 982 IDTVEC(tss_trap08)); 983 setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1, 984 SDT_SYS386TSS, SEL_KPL, 0, 0); 985 ci->ci_gdt[GTRAPTSS_SEL].sd = sd; 986 setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 987 GSEL(GTRAPTSS_SEL, SEL_KPL)); 988 989 #if defined(DDB) && defined(MULTIPROCESSOR) 990 /* 991 * Set up separate handler for the DDB IPI, so that it doesn't 992 * stomp on a possibly corrupted stack. 993 * 994 * XXX overwriting the gate set in db_machine_init. 995 * Should rearrange the code so that it's set only once. 996 */ 997 ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0, 998 UVM_KMF_WIRED); 999 tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack, Xintrddbipi); 1000 1001 setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1, 1002 SDT_SYS386TSS, SEL_KPL, 0, 0); 1003 ci->ci_gdt[GIPITSS_SEL].sd = sd; 1004 1005 setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL, 1006 GSEL(GIPITSS_SEL, SEL_KPL)); 1007 #endif 1008 } 1009 #else 1010 static void 1011 cpu_set_tss_gates(struct cpu_info *ci) 1012 { 1013 1014 } 1015 #endif /* i386 */ 1016 1017 #ifdef MULTIPROCESSOR 1018 int 1019 mp_cpu_start(struct cpu_info *ci, paddr_t target) 1020 { 1021 unsigned short dwordptr[2]; 1022 int error; 1023 1024 /* 1025 * Bootstrap code must be addressable in real mode 1026 * and it must be page aligned. 1027 */ 1028 KASSERT(target < 0x10000 && target % PAGE_SIZE == 0); 1029 1030 /* 1031 * "The BSP must initialize CMOS shutdown code to 0Ah ..." 1032 */ 1033 1034 outb(IO_RTC, NVRAM_RESET); 1035 outb(IO_RTC+1, NVRAM_RESET_JUMP); 1036 1037 /* 1038 * "and the warm reset vector (DWORD based at 40:67) to point 1039 * to the AP startup code ..." 1040 */ 1041 1042 dwordptr[0] = 0; 1043 dwordptr[1] = target >> 4; 1044 1045 #if NLAPIC > 0 1046 memcpy((uint8_t *)cmos_data_mapping + 0x467, dwordptr, 4); 1047 #endif 1048 1049 if ((cpu_feature[0] & CPUID_APIC) == 0) { 1050 aprint_error("mp_cpu_start: CPU does not have APIC\n"); 1051 return ENODEV; 1052 } 1053 1054 /* 1055 * ... prior to executing the following sequence:". We'll also add in 1056 * local cache flush, in case the BIOS has left the AP with its cache 1057 * disabled. It may not be able to cope with MP coherency. 1058 */ 1059 wbinvd(); 1060 1061 if (ci->ci_flags & CPUF_AP) { 1062 error = x86_ipi_init(ci->ci_cpuid); 1063 if (error != 0) { 1064 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n", 1065 __func__); 1066 return error; 1067 } 1068 i8254_delay(10000); 1069 1070 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1071 if (error != 0) { 1072 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n", 1073 __func__); 1074 return error; 1075 } 1076 i8254_delay(200); 1077 1078 error = x86_ipi_startup(ci->ci_cpuid, target / PAGE_SIZE); 1079 if (error != 0) { 1080 aprint_error_dev(ci->ci_dev, "%s: IPI not taken (3)\n", 1081 __func__); 1082 return error; 1083 } 1084 i8254_delay(200); 1085 } 1086 1087 return 0; 1088 } 1089 1090 void 1091 mp_cpu_start_cleanup(struct cpu_info *ci) 1092 { 1093 /* 1094 * Ensure the NVRAM reset byte contains something vaguely sane. 1095 */ 1096 1097 outb(IO_RTC, NVRAM_RESET); 1098 outb(IO_RTC+1, NVRAM_RESET_RST); 1099 } 1100 #endif 1101 1102 #ifdef __x86_64__ 1103 typedef void (vector)(void); 1104 extern vector Xsyscall, Xsyscall32; 1105 #endif 1106 1107 void 1108 cpu_init_msrs(struct cpu_info *ci, bool full) 1109 { 1110 #ifdef __x86_64__ 1111 wrmsr(MSR_STAR, 1112 ((uint64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1113 ((uint64_t)LSEL(LSYSRETBASE_SEL, SEL_UPL) << 48)); 1114 wrmsr(MSR_LSTAR, (uint64_t)Xsyscall); 1115 wrmsr(MSR_CSTAR, (uint64_t)Xsyscall32); 1116 wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C); 1117 1118 if (full) { 1119 wrmsr(MSR_FSBASE, 0); 1120 wrmsr(MSR_GSBASE, (uint64_t)ci); 1121 wrmsr(MSR_KERNELGSBASE, 0); 1122 } 1123 #endif /* __x86_64__ */ 1124 1125 if (cpu_feature[2] & CPUID_NOX) 1126 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1127 } 1128 1129 void 1130 cpu_offline_md(void) 1131 { 1132 int s; 1133 1134 s = splhigh(); 1135 fpusave_cpu(true); 1136 splx(s); 1137 } 1138 1139 /* XXX joerg restructure and restart CPUs individually */ 1140 static bool 1141 cpu_stop(device_t dv) 1142 { 1143 struct cpu_softc *sc = device_private(dv); 1144 struct cpu_info *ci = sc->sc_info; 1145 int err; 1146 1147 KASSERT((ci->ci_flags & CPUF_PRESENT) != 0); 1148 1149 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1150 return true; 1151 1152 if (ci->ci_data.cpu_idlelwp == NULL) 1153 return true; 1154 1155 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1156 1157 if (sc->sc_wasonline) { 1158 mutex_enter(&cpu_lock); 1159 err = cpu_setstate(ci, false); 1160 mutex_exit(&cpu_lock); 1161 1162 if (err != 0) 1163 return false; 1164 } 1165 1166 return true; 1167 } 1168 1169 static bool 1170 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1171 { 1172 struct cpu_softc *sc = device_private(dv); 1173 struct cpu_info *ci = sc->sc_info; 1174 1175 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1176 return true; 1177 else { 1178 cpufreq_suspend(ci); 1179 } 1180 1181 return cpu_stop(dv); 1182 } 1183 1184 static bool 1185 cpu_resume(device_t dv, const pmf_qual_t *qual) 1186 { 1187 struct cpu_softc *sc = device_private(dv); 1188 struct cpu_info *ci = sc->sc_info; 1189 int err = 0; 1190 1191 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1192 return true; 1193 1194 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1195 goto out; 1196 1197 if (ci->ci_data.cpu_idlelwp == NULL) 1198 goto out; 1199 1200 if (sc->sc_wasonline) { 1201 mutex_enter(&cpu_lock); 1202 err = cpu_setstate(ci, true); 1203 mutex_exit(&cpu_lock); 1204 } 1205 1206 out: 1207 if (err != 0) 1208 return false; 1209 1210 cpufreq_resume(ci); 1211 1212 return true; 1213 } 1214 1215 static bool 1216 cpu_shutdown(device_t dv, int how) 1217 { 1218 struct cpu_softc *sc = device_private(dv); 1219 struct cpu_info *ci = sc->sc_info; 1220 1221 if ((ci->ci_flags & CPUF_BSP) != 0) 1222 return false; 1223 1224 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1225 return true; 1226 1227 return cpu_stop(dv); 1228 } 1229 1230 void 1231 cpu_get_tsc_freq(struct cpu_info *ci) 1232 { 1233 uint64_t last_tsc; 1234 1235 if (cpu_hascounter()) { 1236 last_tsc = cpu_counter_serializing(); 1237 i8254_delay(100000); 1238 ci->ci_data.cpu_cc_freq = 1239 (cpu_counter_serializing() - last_tsc) * 10; 1240 } 1241 } 1242 1243 void 1244 x86_cpu_idle_mwait(void) 1245 { 1246 struct cpu_info *ci = curcpu(); 1247 1248 KASSERT(ci->ci_ilevel == IPL_NONE); 1249 1250 x86_monitor(&ci->ci_want_resched, 0, 0); 1251 if (__predict_false(ci->ci_want_resched)) { 1252 return; 1253 } 1254 x86_mwait(0, 0); 1255 } 1256 1257 void 1258 x86_cpu_idle_halt(void) 1259 { 1260 struct cpu_info *ci = curcpu(); 1261 1262 KASSERT(ci->ci_ilevel == IPL_NONE); 1263 1264 x86_disable_intr(); 1265 if (!__predict_false(ci->ci_want_resched)) { 1266 x86_stihlt(); 1267 } else { 1268 x86_enable_intr(); 1269 } 1270 } 1271 1272 /* 1273 * Loads pmap for the current CPU. 1274 */ 1275 void 1276 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1277 { 1278 #ifdef PAE 1279 struct cpu_info *ci = curcpu(); 1280 bool interrupts_enabled; 1281 pd_entry_t *l3_pd = ci->ci_pae_l3_pdir; 1282 int i; 1283 1284 /* 1285 * disable interrupts to block TLB shootdowns, which can reload cr3. 1286 * while this doesn't block NMIs, it's probably ok as NMIs unlikely 1287 * reload cr3. 1288 */ 1289 interrupts_enabled = (x86_read_flags() & PSL_I) != 0; 1290 if (interrupts_enabled) 1291 x86_disable_intr(); 1292 1293 for (i = 0 ; i < PDP_SIZE; i++) { 1294 l3_pd[i] = pmap->pm_pdirpa[i] | PG_V; 1295 } 1296 1297 if (interrupts_enabled) 1298 x86_enable_intr(); 1299 tlbflush(); 1300 #else /* PAE */ 1301 lcr3(pmap_pdirpa(pmap, 0)); 1302 #endif /* PAE */ 1303 } 1304 1305 /* 1306 * Notify all other cpus to halt. 1307 */ 1308 1309 void 1310 cpu_broadcast_halt(void) 1311 { 1312 x86_broadcast_ipi(X86_IPI_HALT); 1313 } 1314 1315 /* 1316 * Send a dummy ipi to a cpu to force it to run splraise()/spllower() 1317 */ 1318 1319 void 1320 cpu_kick(struct cpu_info *ci) 1321 { 1322 x86_send_ipi(ci, 0); 1323 } 1324
Indexes created Wed Sep 24 15:09:51 GMT 2025